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| REJ09B0328-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2194 Group, H8S/2194C Group, H8S/2194F-ZTATTM, H8S/2194C F-ZTATTM Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2194 H8S/2193 H8S/2192 H8S/2191 H8S/2194C H8S/2194B H8S/2194A HD6432194 HD64F2194 HD6432193 HD6432192 HD6432191 HD6432194C HD64F2194C HD6432194B HD6432194A Rev.3.00 Revision Date: Jan. 10, 2007 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.3.00 Jan. 10, 2007 page ii of xxxvi REJ09B0328-0300 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.3.00 Jan. 10, 2007 page iii of xxxvi REJ09B0328-0300 Rev.3.00 Jan. 10, 2007 page iv of xxxvi REJ09B0328-0300 Main Revisions for This Edition Item All Page -- Revision (See Manual for Details) * Notification of change in company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. * Product naming convention amended (Before) H8S/2194 Series (After) H8S/2194 Group (Before) H8S/2194C Series (After) H8S/2194C Group 2.8.1 Overview Figure 2.15 State Transitions 4.2.3 Timer Register A (TMA) 79 54 Figure 2.15 amended RES = High SLEEP instruction with LSON = 0, TMA3 = 0, SSBY = 0 Table amended * Timer A counts -based prescalar (PSS) divided clock pulses * Timer A counts w-based prescalar (PSW) divided clock pulses 4.6.1 Standby Mode 4.6.2 Clearing Standby Mode 6.2.6 Port Mode Register (PMR1) 7.2.5 Register Configuration Table 7.3 Flash Memory Registers 7.4.1 Boot Mode 143 (1) Automatic SCI Bit Rate Adjustment Description amended ... bit rate should be set to (4800, or 9600) bps. ... 8.4.1 Boot Mode 191 (1) Automatic SCI Bit Rate Adjustment Description amended ... bit rate should be set to (4800, or 9600) bps. ... 8.5 Programming/Erasing Flash Memory 195 Description amended ... PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2. ... 83 83 Description amended ... RAM as well as functions of the SCI1, timer X1 ... (1) Clearing with an Interrupt ... in bits STS2 to STS0 in SBYCR, stable clocks are supplied ... 106 132 Table amended P1n/IRQn pin functions as the IRQn input pin Access size description deleted from table 7.3 Rev.3.00 Jan. 10, 2007 page v of xxxvi REJ09B0328-0300 Item Page Revision (See Manual for Details) Section 8.5.1 title amended 8.5.1 Program Mode 195 (n = 1 for addresses H'00000 to H'1FFFF and n= 2 for addresses H'20000 to H'3FFFF) 8.5.3 Erase Mode (n = 198 1 for Addresses H'00000 to H'1FFFF and N = 2 for Addresses H'20000 to H'3FFFF) 8.8.1 Program Mode Setting 8.8.3 Programmer Mode Operation Table 8.10 Settings for Each Operating Mode in Programmer Mode 8.8.5 Auto-Program Mode 11.1.2 Port Input Table 11.1 Port Functions 11.1.3 MOS Pull-Up Transistors Figure 11.1 Circuit Configuration of Pin with MOS Pull-Up Transistor 11.2.4 Pin States Table 11.4 Port 0 Pin States 11.4.1 Overview 248 240 237 211 236 205 Description amended ... is switched to erase mode by setting the En bit in FLMCRn. The time during ... Description amended ... Renesas Technology microcomputer device type with 256kbyte on-chip flash memory. ... 206 Table 8.10 amended Pin Names Mode Read Output disable Command write Chip disable*1 FWE H or L H or L H or L* H or L 3 CE L L L H OE L H H X WE H H L X FO0 to FO7 Data output Hi-Z Data input Hi-Z FA0 to FA17 Ain X Ain*2 X Description amended (d) ... Do not perform transfer after the third cycle. Pin description for port 0 in table 11.1 amended P07/AN7 to P00/AN0 Figure 11.1 amended Input data Table 11.4 amended P07/AN7 to P00/AN0 (1) Port Mode Register 2 (PMR2) Description amended Port mode register 2 (PMR2) controls switching ... If the SCK1, SCK2, SI1, and SI2 input pins are set, ... Rev.3.00 Jan. 10, 2007 page vi of xxxvi REJ09B0328-0300 Item 11.10.2 Register Configuration Page 284 Revision (See Manual for Details) (1) Port Mode Register 8 (PMR8) Description amended Bit 1P81/EXCAP Pin Switching (PMR81): PMR81 sets whether the P81/EXCAP pin is used as a P81 I/O pin or an EXCAP pin for the capstan external synchronous signal input. 15.2.1 Timer L Mode Register (LMR) 324 325 Bit figure amended Bits 3 to 0 (Before) IMR (After) LMR Bits 2 to 0Clock Selection Bit table amended (Before) R2 (After) LMR2 16.2.2 Timer R Mode Register 2 (TMRM2) 335 Bit 7Selection of Capture Signals of the TMRU-2 (LAT) Bit table amended Captures at the rising edge of the CFG 17.6 Exemplary Uses of the Timer X1 379 Description amended (2) Each time a comparing match occurs, the OLVLA bit and ... Figure 22.1 amended (Before) 2 (After) 2 8 0 22.1.2 Block Diagram 424 Figure 22.1 Block Diagram of Prescalar Unit 23.2.5 Serial Mode Register (SMR1) 440 Bit 4Parity Mode (O/E) Bit table amended Odd parity* 2 23.2.7 Serial Status Register (SSR1) 448 Bit 4Parity Error (PER) Bit table amended (Before) Bit 4 (After) Bit 3 23.2.8 Bit Rate Register (BRR1) Table 23.4 BRR1 Settings for Various Bit Rates (Clock Synchronous Mode) 452 Table 23.4 amended Operating Frequency (MHz) Bit Rate (bits/s) 110 250 500 2 n 3 2 1 N 70 124 249 4 n -- 2 2 N -- 249 124 3 2 124 249 8 n N Table 23.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) 455 Table 23.6 amended (MHz) External Input Clock (MHz) 1.500 0 Maximum Bit Rate (bits/s) 93750 6 Rev.3.00 Jan. 10, 2007 page vii of xxxvi REJ09B0328-0300 Item Page Revision (See Manual for Details) Bit 0Serial Communication Interface Mode Select (SMIF) Bit table amended Normal SCI1 mode (2) Clock Description amended ... For details on SCI1 clock source selection, ... 23.2.9 Serial Interface 457 Mode Register (SCMR1) 23.3.4 Operation in Clock Synchronous Mode 23.5 Usage Notes 478 488 (1) Relation between Writes to TDR1 and the TDRE Flag Description amended ... TDR1 to TSR. When the SCI1 transfers data from TDR1 to TSR, ... 24.2.4 Serial Control Status Register 2 (SCSR2) 499 Bit 1Abort Flag (ABT) Description amended ... while this bit is set to 1. Resume transfer after clearing to 0. Bit 0Start Flag (STF) Description amended ... other than the SCSR2 and serial data buffer (32 bytes) are retained. 24.3.3 Data Transfer Operations 504 (1) SCI2 Initialization Description amended (2) The SCI2 pin is also used as a port. Switching of a port is performed on PMR3. 505 25.2.5 I C Bus Control 521 Register (ICCR) 2 Description amended ... While PMR30 of PMR3 is set to 1, transmission is ... Bit 7I C Bus Interface Enable (ICE) Description amended I C Bus interface module enabled for transfer operations (pins SCL and SDA are driving the bus) ... 2 2 25.2.7 Serial/Timer Control Register (STCR) 25.3.2 Master Transmit Operation 533 Bit 5I C Controller Reset (IICRST) Description amended ... Therefore, be sure to clear the IICRST bit after setting it. 2 537 Description amended [11] ...When there is data to be transmitted, go to the step [9] to continue next transmission. ... Rev.3.00 Jan. 10, 2007 page viii of xxxvi REJ09B0328-0300 Item 25.3.3 Master Receive Operation Figure 25.7 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) 25.3.8 Sample Flowcharts Figure 25.14 Flowchart for Master Transmit Mode (Example) Page 540 Revision (See Manual for Details) Figure 25.7 amended [4] IRIC clearance 548 Figure 25.14 amended Read IRIC in ICCR No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC in ICCR [6] Set transmit data for the first byte (slave address + R/W). (After writing ICDR, clear IRIC immediately) [5] Wait for a start condition generation 25.4 Usage Notes 554 Description amended (1) ... then issue the instruction that generates the stop condition. Note that the SCL may briefly remain at a high level immediately after BBSY is cleared to 0. 559 to 566 (10) Notes on WAIT Function (11) Notes on ICDR Reads and ICCR Access in Slave Transmit Mode (12) Notes on TRS Bit Setting in Slave Mode (13) Notes on Arbitration Lost in Master Mode (14) Notes on Interrupt Occurrence after ACKB Reception (15) Notes on TRS Bit Setting and ICDR Register Access Description added 28.2.3 Pin Configuration 28.3.4 Register Descriptions 610 Description amended ... P6n, P7n, P80 to P83, and PS1 to PS4 are general-purpose ports. ... 626 (5) Reference Period Mode Register 2 (RFM2) Description amended ... signal generators. Bits 6 to 1 are reserved. ... Rev.3.00 Jan. 10, 2007 page ix of xxxvi REJ09B0328-0300 Item 28.11.2 Block Diagram Figure 28.38 Block Diagram of Digital Filter Circuit Page 713 Revision (See Manual for Details) Figure 28.38 amended A, B, G, etc. 28.11.5 Register Descriptions 721 (6) Capstan System Digital Filter Control Register (CFIC) Bit figure amended Bit : Initial value : R/W : 7 -- 1 -- 6 CROV 0 R/(W)* 5 CPHA 0 R/(W) 4 CZPON 0 R/W 3 CZSON 0 R/W 2 CSG2 0 R/W 1 CSG1 0 R/W 0 CSG0 0 R/W 28.12.5 Additional V Pulse Signal 732 Description amended Additional V Pulses when Sync Signal Is Not Detected: ... depending on the HRTR and HPWR setting, with resultant discontinuity. ... 28.13.5 Register Descriptions 740 (2) CTL Mode Register (CTLM) Description amended Bits 7 and 6: Record/Playback Mode Bits (ASM, REC/PB): 745 (6) REC-CTL Duty Data Register 4 (RCDR4) Description amended ... RCDR4 = T4 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T4 is ... 746 (7) REC-CTL Duty Data Register 5 (RCDR5) Description amended ... RCDR5 = T5 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T5 is ... 747 Bit 0Duty I/O Register (DI/O) Description amended ... the VISS control circuit. In VISS record or rewrite mode ... Rev.3.00 Jan. 10, 2007 page x of xxxvi REJ09B0328-0300 Calculation buffer Coefficient register Constant register Buffer circuit D Item 28.13.6 Operation Figure 28.50 Example of CTLM Switchover Timing (When Phase Control Is Performed by REF30P and DVCFG2 in REC Mode) Page 751 Revision (See Manual for Details) Figure 28.50 amended (Before) PDCR3 (After) PCDR3 Figure 28.51 Example 752 of CTLM Switchover Timing (When Phase Control Is Performed by CREF and DVCFG2 in REC Mode) 28.18.9 CTL Output Section Table 28.21 REC-CTL Duty Register and CTL Outputs 28.15.6 Noise Detection 790 762 Figure 28.51 amended Ta is the interval calculated from RCDR3. ... Table 28.21 amended (Before) 65.5 0.5% (After) 62.5 0.5% (1) Example of Setting Description amended HPWR3 - 0 = H'B 29.2.7 Flash Memory Characteristics Table 29.12 Flash Memory Characteristics (Preliminary) 824 Table 29.12 amended Item Erasing time*1*3*5 Reprogramming count 9 Data retention time* Symbol tE NWEC tDRP Min Typ 100 Max Unit Test Conditions 1200 ms/ block Times Years s 100 10000 -- *7 *8 10 10 -- -- -- -- 1 At Wait time after SWE-bit setting* x Programming 825 Notes 7 to 9 added Notes: 7. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 8. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 9. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. Rev.3.00 Jan. 10, 2007 page xi of xxxvi REJ09B0328-0300 Item A.1 Instructions Table A.1 List of Instruction Set Page 856 Revision (See Manual for Details) (7) System Control Instructions in table A.1 amended No of Execution States *1 Mnemonic Advanced Mode TRAPA TRAPA #xx:2 RTE RTE 8 [9] 5 [9] 2 1 2 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 2 1 2 1 2 1 SLEEP SLEEP LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR STC CCR,Rd STC STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ORC ORC #xx:8,CCR ORC #xx:8,EXR XORC XORC #xx:8,CCR XORC #xx:8,EXR NOP NOP A.4 Number of Execution States Table A.4 Number of States Required for Each Execution Status (Cycle) 872 873 Description amended ... for each instruction of the H8S/2000 CPU. Table A.5 ... Table A.4 amended Target of Access On-Chip Supporting Module Execution Status (Cycle) Byte data access SL Word data access SM Internal operation SN 1 On-Chip Memory 8-Bit Bus 2 4 1 16-Bit Bus 2 2 1 A.6 Change of Condition Codes Table A.7 Change of Condition Codes 902 Table A.7 amended (Before) C=D0 (In case of 1 bit), C=D-1 (In case of 2 bits) (After) C=D0 (In case of 1 bit), C=D1 (In case of 2 bits) Rev.3.00 Jan. 10, 2007 page xii of xxxvi REJ09B0328-0300 Item B.2 Function List Page 918 Revision (See Manual for Details) H'D029: CFIC: Digital Filter Figure amended 2 CSG2 0 R/W 1 CSG1 0 R/W 0 CSG0 0 R/W Capstan system gain control bit CSG1 CSG0 Description 0 0 x1 1 x2 1 0 x4 1 x8 1 0 0 x16 1 (x32)* 1 0 (x64)* 1 Invalid (do not set) Note: * Setting optional CSG2 0 919 H'D031: DFPR: Drum Error Detector H'D033: DFER: Drum Error Detector Subheading deleted 919 H'D032: DFER: Drum Error Detector Note * added Note: * Note that only detected error data can be read. 920 H'D035: DFRUDR: Drum Error Detector H'D037: DFRLDR: Drum Error Detector Subheading deleted 927 H'D060: HSM1: HSW Timing Generator Figure amended FIFO1 overwrite flag 0 Normal operation 1 Data is written to FIFO2 while it is full. Write 0 to clear the flag. 941 Table amended Video FF signal turns counter set ON Rev.3.00 Jan. 10, 2007 page xiii of xxxvi REJ09B0328-0300 Item B.2 Function List Page 954 Revision (See Manual for Details) H'D0E2: SCR2: 32-byte Buffer SCI2 Figure amended Transfer clock select bits CKS2 CKS1 CKS0 SCK2 pin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SCK2 input External clock SCK2 output Clock source Sprescaler S Prescaler frequency Transfer clock frequency division rate = 10 MHz = 5 MHz /256 25.6 s 51.2 s /64 /32 /16 /8 /4 /2 6.4 s 3.2 s 1.6 s 0.8 s 0.4 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s 0.4 s -- -- -- -- Transfer data interval select bits GAP1 GAP0 Transfer data interval 0 0 No interval 0 1 8-clock interval 1 0 24-clock interval 1 1 56-clock interval 956 H'D100: ITER: Timer X1 Figure amended Output compare interrupt enable bit 0 1 OFV interrupt request (FOVI) is disabled OFV interrupt request (FOVI) is enabled 962 H'D100: TMB: Timer B Figure amended Clock select bit Count at rising/falling edge of external event (TMBI)* 984 H'D14C: SSR1: SCI1 Figure amended Parity error (Before) (even or odd) specified by the O/E bit in SMR1 2 (After) (even or odd) specified by the O/E bit in SMR1 2 986 H'D158: ICCR: IIC Bus Interface Figure amended I C bus interface enable I C bus interface module enabled for transfer operation (pins SCL and SDA are driving the bus) 2 2 Rev.3.00 Jan. 10, 2007 page xiv of xxxvi REJ09B0328-0300 Item B.2 Function List Page 1000 Revision (See Manual for Details) H'FFD4: PCR4: I/O Port Figure amended Bit : Initial value : R/W : 7 PCR47 0 W 6 PCR46 0 W 5 PCR45 0 W 4 PCR44 0 W 3 PCR43 0 W 2 PCR42 0 W 1 PCR41 0 W 0 PCR40 0 W 0 1 P4n pin functions as input port P4n pin functions as output port Note: n = 7 to 0 1002 H'FFDC: PMR5: I/O Port Figure amended P52/TRIG pin function select bit P52/TMBI pin functions as TMBI input port 1004 H'FFE3: PUR3: I/O Port Figure amended Bit : Initial value : R/W : 7 PUR37 0 R/W 6 PUR36 0 R/W 5 PUR35 0 R/W 4 PUR34 0 R/W 3 PUR33 0 R/W 2 PUR32 0 R/W 1 PUR31 0 R/W 0 PUR30 0 R/W 0 1 P3n pin has no pull-up MOS transistor P3n pin has pull-up MOS transistor Note: n = 7 to 0 1010 C.1 Pin Circuit Diagrams Table C.1 Pin Circuit Diagrams 1024 1025 1019 to 1024 Table amended (Before) IRQ0EG2 (After) IRQ0EG0 Circuit diagram description amended PUR1n PCR1n PUR21 PCR21 PUR26 PCR26 PUR30 PCR30 PUR17 PCR17 PUR22 PCR22 PUR25 PCR25 PUR3n PCR3n PUR20 PCR20 PUR2n PCR2n PUR27 PCR27 Circuit diagram description amended (Before) OUR: (After) OUT: Pin name description amended P42/FTIB P46/FTOB G. External Dimensions Figure G.1 External Dimensions (FP-112) 1037 Figure G.1 replaced Rev.3.00 Jan. 10, 2007 page xv of xxxvi REJ09B0328-0300 All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Jan. 10, 2007 page xvi of xxxvi REJ09B0328-0300 Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Arrangement and Functions........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... Differences between H8S/2194C Group and H8S/2194 Group ........................................ 1 1 6 7 7 8 14 1.4 Section 2 CPU ...................................................................................................................... 15 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU............................................................................. 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... 2.2.1 Normal Mode....................................................................................................... 2.2.2 Advanced Mode ................................................................................................... Address Space ................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values.......................................................................................... Data Formats ..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function ....................................................... 2.6.4 Basic Instruction Formats .................................................................................... 2.6.5 Notes on Use of Bit-Manipulation Instructions ................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode ................................................................................................. 2.7.2 Effective Address Calculation.............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 15 15 16 17 17 18 18 20 23 24 24 25 26 28 28 29 31 32 32 34 35 45 46 46 46 49 53 53 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Rev.3.00 Jan. 10, 2007 page xvii of xxxvi REJ09B0328-0300 2.8.2 Reset State ........................................................................................................... 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State...................................................................................... 2.8.5 Power-Down State ............................................................................................... 2.9 Basic Timing..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.10 Usage Note........................................................................................................................ 54 55 56 57 58 58 58 59 59 Section 3 MCU Operating Modes .................................................................................. 61 3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 1 ................................................................................................................. Address Map ..................................................................................................................... 61 61 61 62 62 62 63 63 64 3.2 3.3 3.4 Section 4 Power-Down State............................................................................................ 69 4.1 4.2 Overview........................................................................................................................... 4.1.1 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 4.2.1 Standby Control Register (SBYCR) .................................................................... 4.2.2 Low-Power Control Register (LPWRCR) ........................................................... 4.2.3 Timer Register A (TMA) ..................................................................................... 4.2.4 Module Stop Control Register (MSTPCR) .......................................................... Medium-Speed Mode........................................................................................................ Sleep Mode ....................................................................................................................... 4.4.1 Sleep Mode .......................................................................................................... 4.4.2 Clearing Sleep Mode............................................................................................ Module Stop Mode ........................................................................................................... 4.5.1 Module Stop Mode .............................................................................................. Standby Mode ................................................................................................................... 4.6.1 Standby Mode ...................................................................................................... 4.6.2 Clearing Standby Mode ....................................................................................... 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode.......................... Watch Mode...................................................................................................................... 69 73 74 74 76 78 79 80 81 81 81 82 82 83 83 83 83 85 4.3 4.4 4.5 4.6 4.7 Rev.3.00 Jan. 10, 2007 page xviii of xxxvi REJ09B0328-0300 4.7.1 Watch Mode......................................................................................................... 4.7.2 Clearing Watch Mode .......................................................................................... 4.8 Subsleep Mode.................................................................................................................. 4.8.1 Subsleep Mode..................................................................................................... 4.8.2 Clearing Subsleep Mode ...................................................................................... 4.9 Subactive Mode................................................................................................................. 4.9.1 Subactive Mode ................................................................................................... 4.9.2 Clearing Subactive Mode..................................................................................... 4.10 Direct Transition ............................................................................................................... 4.10.1 Overview of Direct Transition ............................................................................. 85 85 86 86 86 87 87 87 88 88 Section 5 Exception Handling ......................................................................................... 89 5.1 Overview........................................................................................................................... 5.1.1 Exception Handling Types and Priority ............................................................... 5.1.2 Exception Handling Operation............................................................................. 5.1.3 Exception Sources and Vector Table ................................................................... Reset.................................................................................................................................. 5.2.1 Overview.............................................................................................................. 5.2.2 Reset Sequence .................................................................................................... 5.2.3 Interrupts after Reset............................................................................................ Interrupts ........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Use of the Stack ................................................................................................. 89 89 90 90 92 92 92 93 94 95 96 97 5.2 5.3 5.4 5.5 5.6 Section 6 Interrupt Controller .......................................................................................... 99 6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 System Control Register (SYSCR) ...................................................................... 6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) ........................................... 6.2.3 IRQ Enable Register (IENR) ............................................................................... 6.2.4 IRQ Edge Select Registers (IEGR) ...................................................................... 6.2.5 IRQ Status Register (IRQR) ................................................................................ 6.2.6 Port Mode Register (PMR1) ................................................................................ Interrupt Sources ............................................................................................................... 6.3.1 External Interrupts ............................................................................................... 99 99 100 101 101 102 102 103 104 104 105 106 108 108 6.2 6.3 Rev.3.00 Jan. 10, 2007 page xix of xxxvi REJ09B0328-0300 6.4 6.5 6.3.2 Internal Interrupts ................................................................................................ 6.3.3 Interrupt Exception Vector Table ........................................................................ Interrupt Operation............................................................................................................ 6.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 6.4.2 Interrupt Control Mode 0 ..................................................................................... 6.4.3 Interrupt Control Mode 1 ..................................................................................... 6.4.4 Interrupt Exception Handling Sequence .............................................................. 6.4.5 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 6.5.1 Contention between Interrupt Generation and Disabling..................................... 6.5.2 Instructions That Disable Interrupts..................................................................... 6.5.3 Interrupts during Execution of EEPMOV Instruction.......................................... 6.5.4 When NMI Is Disabled ........................................................................................ 110 110 113 113 115 117 120 121 122 122 123 123 123 Section 7 ROM (H8S/2194 Group)................................................................................ 125 7.1 7.2 Overview........................................................................................................................... 7.1.1 Block Diagram..................................................................................................... Overview of Flash Memory .............................................................................................. 7.2.1 Features................................................................................................................ 7.2.2 Block Diagram..................................................................................................... 7.2.3 Flash Memory Operating Modes ......................................................................... 7.2.4 Pin Configuration................................................................................................. 7.2.5 Register Configuration......................................................................................... Flash Memory Register Descriptions................................................................................ 7.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 7.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 7.3.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 7.3.4 Serial/Timer Control Register (STCR) ................................................................ On-Board Programming Modes........................................................................................ 7.4.1 Boot Mode ........................................................................................................... 7.4.2 User Program Mode............................................................................................. Programming/Erasing Flash Memory ............................................................................... 7.5.1 Program Mode ..................................................................................................... 7.5.2 Program-Verify Mode.......................................................................................... 7.5.3 Erase Mode .......................................................................................................... 7.5.4 Erase-Verify Mode .............................................................................................. Flash Memory Protection.................................................................................................. 7.6.1 Hardware Protection ............................................................................................ 7.6.2 Software Protection.............................................................................................. 7.6.3 Error Protection.................................................................................................... 125 125 126 126 127 128 132 132 133 133 136 138 139 140 141 146 147 147 148 150 150 152 152 153 153 7.3 7.4 7.5 7.6 Rev.3.00 Jan. 10, 2007 page xx of xxxvi REJ09B0328-0300 7.7 7.8 Interrupt Handling when Programming/Erasing Flash Memory....................................... Flash Memory Programmer Mode .................................................................................... 7.8.1 Programmer Mode Setting ................................................................................... 7.8.2 Socket Adapters and Memory Map...................................................................... 7.8.3 Programmer Mode Operation .............................................................................. 7.8.4 Memory Read Mode ............................................................................................ 7.8.5 Auto-Program Mode ............................................................................................ 7.8.6 Auto-Erase Mode ................................................................................................. 7.8.7 Status Read Mode ................................................................................................ 7.8.8 Status Polling ....................................................................................................... 7.8.9 Programmer Mode Transition Time..................................................................... 7.8.10 Notes On Memory Programming......................................................................... 7.9 Flash Memory Programming and Erasing Precautions ..................................................... 7.10 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 155 156 156 156 157 158 161 163 164 166 166 167 168 170 Section 8 ROM (H8S/2194C Group)............................................................................. 171 8.1 8.2 Overview........................................................................................................................... 8.1.1 Block Diagram ..................................................................................................... Overview of Flash Memory .............................................................................................. 8.2.1 Features................................................................................................................ 8.2.2 Block Diagram ..................................................................................................... 8.2.3 Flash Memory Operating Modes ......................................................................... 8.2.4 Pin Configuration................................................................................................. 8.2.5 Register Configuration......................................................................................... Flash Memory Register Descriptions................................................................................ 8.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 8.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 8.3.3 Erase Block Registers 1 (EBR1) .......................................................................... 8.3.4 Erase Block Registers 2 (EBR2) .......................................................................... 8.3.5 Serial/Timer Control Register (STCR) ................................................................ On-Board Programming Modes ........................................................................................ 8.4.1 Boot Mode ........................................................................................................... 8.4.2 User Program Mode............................................................................................. Programming/Erasing Flash Memory ............................................................................... 8.5.1 Program Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF).......................................................................... 8.5.2 Program-Verify Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) .................................................................... 8.5.3 Erase Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) ........................................................................................... 171 171 172 172 173 174 178 178 179 179 183 186 186 187 188 189 193 195 195 196 198 8.3 8.4 8.5 Rev.3.00 Jan. 10, 2007 page xxi of xxxvi REJ09B0328-0300 Erase-Verify Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) .................................................................... 8.6 Flash Memory Protection.................................................................................................. 8.6.1 Hardware Protection ............................................................................................ 8.6.2 Software Protection.............................................................................................. 8.6.3 Error Protection.................................................................................................... 8.7 Interrupt Handling when Programming/Erasing Flash Memory....................................... 8.8 Flash Memory Programmer Mode .................................................................................... 8.8.1 Programmer Mode Setting................................................................................... 8.8.2 Socket Adapters and Memory Map ..................................................................... 8.8.3 Programmer Mode Operation .............................................................................. 8.8.4 Memory Read Mode ............................................................................................ 8.8.5 Auto-Program Mode ............................................................................................ 8.8.6 Auto-Erase Mode................................................................................................. 8.8.7 Status Read Mode ................................................................................................ 8.8.8 Status Polling ....................................................................................................... 8.8.9 Programmer Mode Transition Time .................................................................... 8.8.10 Notes On Memory Programming......................................................................... 8.9 Flash Memory Programming and Erasing Precautions..................................................... 8.10 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 8.5.4 198 200 200 201 202 204 205 205 205 206 207 211 213 214 216 217 217 218 220 Section 9 RAM..................................................................................................................... 221 9.1 Overview........................................................................................................................... 221 9.1.1 Block Diagram..................................................................................................... 221 Section 10 Clock Pulse Generator .................................................................................. 223 10.1 Overview........................................................................................................................... 10.1.1 Block Diagram..................................................................................................... 10.1.2 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Standby Control Register (SBYCR) .................................................................... 10.2.2 Low-Power Control Register (LPWRCR) ........................................................... 10.3 Oscillator........................................................................................................................... 10.3.1 Connecting a Crystal Resonator........................................................................... 10.3.2 External Clock Input............................................................................................ 10.4 Duty Adjustment Circuit................................................................................................... 10.5 Medium-Speed Clock Divider .......................................................................................... 10.6 Bus Master Clock Selection Circuit.................................................................................. 10.7 Subclock Oscillator Circuit............................................................................................... 10.7.1 Connecting 32.768 kHz Crystal Resonator .......................................................... Rev.3.00 Jan. 10, 2007 page xxii of xxxvi REJ09B0328-0300 223 223 223 224 224 225 226 226 228 230 230 230 231 231 10.7.2 External Clock Input ............................................................................................ 10.7.3 When Subclock Is Not Needed ............................................................................ 10.8 Subclock Waveform Shaping Circuit................................................................................ 10.9 Notes on the Resonator ..................................................................................................... 232 232 233 233 Section 11 I/O Port.............................................................................................................. 235 11.1 Overview........................................................................................................................... 11.1.1 Port Functions ...................................................................................................... 11.1.2 Port Input ............................................................................................................. 11.1.3 MOS Pull-Up Transistors..................................................................................... 11.2 Port 0................................................................................................................................. 11.2.1 Overview.............................................................................................................. 11.2.2 Register Configuration......................................................................................... 11.2.3 Pin Functions ....................................................................................................... 11.2.4 Pin States.............................................................................................................. 11.3 Port 1................................................................................................................................. 11.3.1 Overview.............................................................................................................. 11.3.2 Register Configuration......................................................................................... 11.3.3 Pin Functions ....................................................................................................... 11.3.4 Pin States.............................................................................................................. 11.4 Port 2................................................................................................................................. 11.4.1 Overview.............................................................................................................. 11.4.2 Register Configuration......................................................................................... 11.4.3 Pin Functions ....................................................................................................... 11.4.4 Pin States.............................................................................................................. 11.5 Port 3................................................................................................................................. 11.5.1 Overview.............................................................................................................. 11.5.2 Register Configuration......................................................................................... 11.5.3 Pin Functions ....................................................................................................... 11.5.4 Pin States.............................................................................................................. 11.6 Port 4................................................................................................................................. 11.6.1 Overview.............................................................................................................. 11.6.2 Register Configuration......................................................................................... 11.6.3 Pin Functions ....................................................................................................... 11.6.4 Pin States.............................................................................................................. 11.7 Port 5................................................................................................................................. 11.7.1 Overview.............................................................................................................. 11.7.2 Register Configuration......................................................................................... 11.7.3 Pin Functions ....................................................................................................... 11.7.4 Pin States.............................................................................................................. 235 235 235 237 238 238 238 240 240 241 241 241 245 246 247 247 247 251 253 254 254 254 258 260 261 261 261 263 266 267 267 267 270 271 Rev.3.00 Jan. 10, 2007 page xxiii of xxxvi REJ09B0328-0300 11.8 Port 6................................................................................................................................. 11.8.1 Overview.............................................................................................................. 11.8.2 Register Configuration......................................................................................... 11.8.3 Pin Functions ....................................................................................................... 11.8.4 Operation ............................................................................................................. 11.8.5 Pin States ............................................................................................................. 11.9 Port 7................................................................................................................................. 11.9.1 Overview.............................................................................................................. 11.9.2 Register Configuration......................................................................................... 11.9.3 Pin Functions ....................................................................................................... 11.9.4 Pin States ............................................................................................................. 11.10 Port 8................................................................................................................................. 11.10.1 Overview.............................................................................................................. 11.10.2 Register Configuration......................................................................................... 11.10.3 Pin Functions ....................................................................................................... 11.10.4 Pin States ............................................................................................................. 272 272 273 276 277 278 279 279 279 281 281 282 282 282 285 287 Section 12 Timer A............................................................................................................. 289 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram..................................................................................................... 12.1.3 Register Configuration......................................................................................... 12.2 Descriptions of Respective Registers................................................................................ 12.2.1 Timer Mode Register A (TMA)........................................................................... 12.2.2 Timer Counter A (TCA) ...................................................................................... 12.2.3 Module Stop Control Register (MSTPCR) .......................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Operation as the Interval Timer ........................................................................... 12.3.2 Operation of the Timer for Clocks....................................................................... 12.3.3 Initializing the Counts.......................................................................................... 289 289 290 290 291 291 293 293 294 294 294 294 Section 13 Timer B ............................................................................................................. 295 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Descriptions of Respective Registers................................................................................ 13.2.1 Timer Mode Register B (TMB) ........................................................................... 13.2.2 Timer Counter B (TCB)....................................................................................... Rev.3.00 Jan. 10, 2007 page xxiv of xxxvi REJ09B0328-0300 295 295 295 296 296 297 297 299 13.2.3 Timer Load Register B (TLB) ............................................................................. 13.2.4 Port Mode Register 5 (PMR5) ............................................................................. 13.2.5 Module Stop Control Register (MSTPCR) .......................................................... 13.3 Operation........................................................................................................................... 13.3.1 Operation as the Interval Timer ........................................................................... 13.3.2 Operation as the Auto Reload Timer ................................................................... 13.3.3 Event Counter ...................................................................................................... 299 299 300 301 301 301 301 Section 14 Timer J............................................................................................................... 303 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Descriptions of Respective Registers ................................................................................ 14.2.1 Timer Mode Register J (TMJ) ............................................................................. 14.2.2 Timer J Control Register (TMJC) ........................................................................ 14.2.3 Timer J Status Register (TMJS)........................................................................... 14.2.4 Timer Counter J (TCJ) ......................................................................................... 14.2.5 Timer Counter K (TCK) ...................................................................................... 14.2.6 Timer Load Register J (TLJ)................................................................................ 14.2.7 Timer Load Register K (TLK) ............................................................................. 14.2.8 Module Stop Control Register (MSTPCR) .......................................................... 14.3 Operation........................................................................................................................... 14.3.1 8-Bit Reload Timer (TMJ-1)................................................................................ 14.3.2 8-Bit Reload Timer (TMJ-2)................................................................................ 14.3.3 Remote Controlled Data Transmission ................................................................ 303 303 303 305 305 306 306 309 311 312 313 313 314 314 315 315 315 316 Section 15 Timer L.............................................................................................................. 321 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Register Configuration......................................................................................... 15.2 Descriptions of Respective Registers ................................................................................ 15.2.1 Timer L Mode Register (LMR)............................................................................ 15.2.2 Linear Time Counter (LTC)................................................................................. 15.2.3 Reload/Compare Match Register (RCR).............................................................. 15.2.4 Module Stop Control Register (MSTPCR) .......................................................... 15.3 Operation........................................................................................................................... 15.3.1 Compare Match Clear Operation ......................................................................... 321 321 322 323 324 324 326 326 326 327 327 Rev.3.00 Jan. 10, 2007 page xxv of xxxvi REJ09B0328-0300 Section 16 Timer R ............................................................................................................. 329 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Descriptions of Respective Registers................................................................................ 16.2.1 Timer R Mode Register 1 (TMRM1)................................................................... 16.2.2 Timer R Mode Register 2 (TMRM2)................................................................... 16.2.3 Timer R Control/Status Register (TMRCS)......................................................... 16.2.4 Timer R Capture Register 1 (TMRCP1) .............................................................. 16.2.5 Timer R Capture Register 2 (TMRCP2) .............................................................. 16.2.6 Timer R Load Register 1 (TMRL1) ..................................................................... 16.2.7 Timer R Load Register 2 (TMRL2) ..................................................................... 16.2.8 Timer R Load Register 3 (TMRL3) ..................................................................... 16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 16.3 Operation .......................................................................................................................... 16.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1.................. 16.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2.................. 16.3.3 Reload Counter Timer TMRU-3.......................................................................... 16.3.4 Mode Identification.............................................................................................. 16.3.5 Reeling Controls .................................................................................................. 16.3.6 Acceleration and Braking Processes of the Capstan Motor ................................. 16.3.7 Slow Tracking Mono-Multi Function .................................................................. 16.4 Interrupt Cause.................................................................................................................. 16.5 Exemplary Settings for Respective Functions .................................................................. 16.5.1 Mode Identification.............................................................................................. 16.5.2 Reeling Controls .................................................................................................. 16.5.3 Slow Tracking Mono-Multi Function .................................................................. 16.5.4 Acceleration and Braking Processes of the Capstan Motor ................................. 329 329 329 331 331 332 332 334 337 339 340 340 341 341 342 343 343 344 344 345 345 345 346 348 349 349 350 350 351 Section 17 Timer X1........................................................................................................... 353 17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 Block Diagram..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 Descriptions of Respective Registers................................................................................ 17.2.1 Free Running Counter (FRC)............................................................................... 17.2.2 Output Comparing Register A and B (OCRA and OCRB).................................. Rev.3.00 Jan. 10, 2007 page xxvi of xxxvi REJ09B0328-0300 353 353 353 355 356 357 357 357 17.3 17.4 17.5 17.6 17.7 17.2.3 Input Capture Register A Through D (ICRA Through ICRD)............................. 17.2.4 Timer Interrupt Enabling Register (TIER)........................................................... 17.2.5 Timer Control/Status Register X (TCSRX) ......................................................... 17.2.6 Timer Control Register X (TCRX) ...................................................................... 17.2.7 Timer Output Comparing Control Register (TOCR) ........................................... 17.2.8 Module Stop Control Register (MSTPCR) .......................................................... Operation........................................................................................................................... 17.3.1 Operation of the Timer X1................................................................................... 17.3.2 Counting Timing of the FRC ............................................................................... 17.3.3 Output Comparing Signal Outputting Timing ..................................................... 17.3.4 FRC Clearing Timing .......................................................................................... 17.3.5 Input Capture Signal Inputting Timing ................................................................ 17.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing............................. 17.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing ........................ 17.3.8 Overflow Flag (CVF) Setting Up Timing ............................................................ Operation Mode of the Timer X1...................................................................................... Interrupt Causes ................................................................................................................ Exemplary Uses of the Timer X1...................................................................................... Precautions when Using the Timer X1 ............................................................................. 17.7.1 Competition between Writing and Clearing with the FRC .................................. 17.7.2 Competition between Writing and Counting Up with the FRC ........................... 17.7.3 Competition between Writing and Comparing Match with the OCR .................. 17.7.4 Changing over the Internal Clocks and Counter Operations................................ 358 360 362 366 368 371 372 372 373 374 374 375 376 377 377 378 378 379 380 380 381 382 383 Section 18 Watchdog Timer (WDT).............................................................................. 385 18.1 Overview........................................................................................................................... 18.1.1 Features................................................................................................................ 18.1.2 Block Diagram ..................................................................................................... 18.1.3 Register Configuration......................................................................................... 18.2 Register Descriptions ........................................................................................................ 18.2.1 Watchdog Timer Counter (WTCNT)................................................................... 18.2.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 18.2.3 System Control Register (SYSCR) ...................................................................... 18.2.4 Notes on Register Access..................................................................................... 18.3 Operation........................................................................................................................... 18.3.1 Watchdog Timer Operation ................................................................................. 18.3.2 Interval Timer Operation ..................................................................................... 18.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 18.4 Interrupts ........................................................................................................................... 18.5 Usage Notes ...................................................................................................................... 385 385 386 387 388 388 388 391 391 393 393 394 395 396 396 Rev.3.00 Jan. 10, 2007 page xxvii of xxxvi REJ09B0328-0300 18.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment 396 18.5.2 Changing Value of CKS2 to CKS0...................................................................... 397 18.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 397 Section 19 8-Bit PWM....................................................................................................... 399 19.1 Overview........................................................................................................................... 19.1.1 Features................................................................................................................ 19.1.2 Block Diagram..................................................................................................... 19.1.3 Pin Configuration................................................................................................. 19.1.4 Register Configuration......................................................................................... 19.2 Register Descriptions ........................................................................................................ 19.2.1 Bit PWM Data Registers 0, 1, 2, and 3 (PWR0, PWR1, PWR2, PWR3) ............ 19.2.2 8-Bit PWM Control Register (PW8CR) .............................................................. 19.2.3 Port Mode Register 3 (PMR3) ............................................................................. 19.2.4 Module Stop Control Register (MSTPCR) .......................................................... 19.3 8-Bit PWM Operation....................................................................................................... 399 399 399 400 400 401 401 402 402 403 404 Section 20 12-Bit PWM .................................................................................................... 405 20.1 Overview........................................................................................................................... 20.1.1 Features................................................................................................................ 20.1.2 Block Diagram..................................................................................................... 20.1.3 Pin Configuration................................................................................................. 20.1.4 Register Configuration......................................................................................... 20.2 Register Descriptions ........................................................................................................ 20.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR) .......................................... 20.2.2 12-Bit PWM Data Registers (CPWDR, DPWDR) .............................................. 20.2.3 Module Stop Control Register (MSTPCR) .......................................................... 20.3 Operation .......................................................................................................................... 20.3.1 Output Waveform ................................................................................................ 405 405 406 407 407 408 408 410 411 412 412 Section 21 14-Bit PWM .................................................................................................... 415 21.1 Overview........................................................................................................................... 21.1.1 Features................................................................................................................ 21.1.2 Block Diagram..................................................................................................... 21.1.3 Pin Configuration................................................................................................. 21.1.4 Register Configuration......................................................................................... 21.2 Register Descriptions ........................................................................................................ 21.2.1 PWM Control Register (PWCR).......................................................................... 21.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 21.2.3 Module Stop Control Register (MSTPCR) .......................................................... Rev.3.00 Jan. 10, 2007 page xxviii of xxxvi REJ09B0328-0300 415 415 416 416 417 418 418 419 420 21.3 14-Bit PWM Operation ..................................................................................................... 421 Section 22 Prescalar Unit .................................................................................................. 423 22.1 Overview........................................................................................................................... 22.1.1 Features................................................................................................................ 22.1.2 Block Diagram ..................................................................................................... 22.1.3 Pin Configuration................................................................................................. 22.1.4 Register Configuration......................................................................................... 22.2 Registers............................................................................................................................ 22.2.1 Input Capture Register 1 (ICR1) .......................................................................... 22.2.2 Prescalar Unit Control/Status Register (PCSR) ................................................... 22.2.3 Port Mode Register 1 (PMR1) ............................................................................. 22.3 Noise Cancel Circuit ......................................................................................................... 22.4 Operation........................................................................................................................... 22.4.1 Prescalar S (PSS) ................................................................................................. 22.4.2 Prescalar W (PSW) .............................................................................................. 22.4.3 Stable Oscillation Wait Time Count .................................................................... 22.4.4 8-Bit PWM........................................................................................................... 22.4.5 8-Bit Input Capture Using IC Pin......................................................................... 22.4.6 Frequency Division Clock Output ....................................................................... 423 423 424 425 425 426 426 426 428 429 429 429 430 430 431 431 431 Section 23 Serial Communication Interface 1 (SCI1)............................................... 433 23.1 Overview........................................................................................................................... 23.1.1 Features................................................................................................................ 23.1.2 Block Diagram ..................................................................................................... 23.1.3 Pin Configuration................................................................................................. 23.1.4 Register Configuration......................................................................................... 23.2 Register Descriptions ........................................................................................................ 23.2.1 Receive Shift Register (RSR) .............................................................................. 23.2.2 Receive Data Register (RDR1) ............................................................................ 23.2.3 Transmit Shift Register (TSR) ............................................................................. 23.2.4 Transmit Data Register (TDR1)........................................................................... 23.2.5 Serial Mode Register (SMR1).............................................................................. 23.2.6 Serial Control Register (SCR1)............................................................................ 23.2.7 Serial Status Register (SSR1) .............................................................................. 23.2.8 Bit Rate Register (BRR1) .................................................................................... 23.2.9 Serial Interface Mode Register (SCMR1) ............................................................ 23.2.10 Module Stop Control Register (MSTPCR) .......................................................... 23.3 Operation........................................................................................................................... 23.3.1 Overview.............................................................................................................. 433 433 435 436 436 437 437 437 438 438 439 442 445 449 456 457 458 458 Rev.3.00 Jan. 10, 2007 page xxix of xxxvi REJ09B0328-0300 23.3.2 Operation in Asynchronous Mode ....................................................................... 23.3.3 Multiprocessor Communication Function............................................................ 23.3.4 Operation in Clock Synchronous Mode............................................................... 23.4 SCI1 Interrupts.................................................................................................................. 23.5 Usage Notes ...................................................................................................................... 460 470 478 487 488 Section 24 Serial Communication Interface 2 (SCI2) .............................................. 491 24.1 Overview........................................................................................................................... 24.1.1 Features................................................................................................................ 24.1.2 Block Diagram..................................................................................................... 24.1.3 Pin Configuration................................................................................................. 24.1.4 Register Configuration......................................................................................... 24.2 Register Descriptions ........................................................................................................ 24.2.1 Starting Address Register (STAR)....................................................................... 24.2.2 Ending Address Register (EDAR) ....................................................................... 24.2.3 Serial Control Register 2 (SCR2)......................................................................... 24.2.4 Serial Control Status Register 2 (SCSR2)............................................................ 24.2.5 Module Stop Control Register (MSTPCR) .......................................................... 24.3 Operation .......................................................................................................................... 24.3.1 Clock.................................................................................................................... 24.3.2 Data Transfer Format........................................................................................... 24.3.3 Data Transfer Operations..................................................................................... 24.4 Interrupt Sources............................................................................................................... 491 491 492 493 493 494 494 494 495 497 500 501 501 501 504 508 Section 25 I2C Bus Interface (IIC).................................................................................. 509 25.1 Overview........................................................................................................................... 25.1.1 Features................................................................................................................ 25.1.2 Block Diagram..................................................................................................... 25.1.3 Pin Configuration................................................................................................. 25.1.4 Register Configuration......................................................................................... 25.2 Register Descriptions ........................................................................................................ 2 25.2.1 I C Bus Data Register (ICDR) ............................................................................. 25.2.2 Slave Address Register (SAR) ............................................................................. 25.2.3 Second Slave Address Register (SARX) ............................................................. 2 25.2.4 I C Bus Mode Register (ICMR)........................................................................... 2 25.2.5 I C Bus Control Register (ICCR) ......................................................................... 2 25.2.6 I C Bus Status Register (ICSR)............................................................................ 25.2.7 Serial/Timer Control Register (STCR) ................................................................ 25.2.8 Module Stop Control Register (MSTPCR) .......................................................... 25.3 Operation .......................................................................................................................... Rev.3.00 Jan. 10, 2007 page xxx of xxxvi REJ09B0328-0300 509 509 510 511 512 513 513 515 516 517 521 527 532 533 535 25.3.1 I C Bus Data Format ............................................................................................ 25.3.2 Master Transmit Operation .................................................................................. 25.3.3 Master Receive Operation.................................................................................... 25.3.4 Slave Receive Operation...................................................................................... 25.3.5 Slave Transmit Operation .................................................................................... 25.3.6 IRIC Setting Timing and SCL Control ................................................................ 25.3.7 Noise Canceler ..................................................................................................... 25.3.8 Sample Flowcharts............................................................................................... 25.3.9 Initialization of Internal State .............................................................................. 25.4 Usage Notes ...................................................................................................................... 2 535 536 539 541 544 545 547 547 552 554 Section 26 A/D Converter................................................................................................. 567 26.1 Overview........................................................................................................................... 26.1.1 Features................................................................................................................ 26.1.2 Block Diagram ..................................................................................................... 26.1.3 Pin Configuration................................................................................................. 26.1.4 Register Configuration......................................................................................... 26.2 Register Descriptions ........................................................................................................ 26.2.1 Software-Triggered A/D Result Register (ADR) ................................................. 26.2.2 Hardware-Triggered A/D Result Register (AHR)................................................ 26.2.3 A/D Control Register (ADCR) ............................................................................ 26.2.4 A/D Control/Status Register (ADCSR) ............................................................... 26.2.5 Trigger Select Register (ADTSR) ........................................................................ 26.2.6 Port Mode Register 0 (PMR0) ............................................................................. 26.2.7 Module Stop Control Register (MSTPCR) .......................................................... 26.3 Interface to Bus Master ..................................................................................................... 26.4 Operation........................................................................................................................... 26.4.1 Software-Triggered A/D Conversion ................................................................... 26.4.2 Hardware- or External-Triggered A/D Conversion.............................................. 26.5 Interrupt Sources ............................................................................................................... 567 567 568 569 570 571 571 571 572 575 578 578 579 580 581 581 582 583 Section 27 Address Trap Controller (ATC)................................................................. 585 27.1 Overview........................................................................................................................... 27.1.1 Features................................................................................................................ 27.1.2 Block Diagram ..................................................................................................... 27.1.3 Register Configuration......................................................................................... 27.2 Register Descriptions ........................................................................................................ 27.2.1 Address Trap Control Register (ATCR) .............................................................. 27.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) ................................................... 27.3 Precautions in Usage......................................................................................................... 585 585 585 586 586 586 587 588 Rev.3.00 Jan. 10, 2007 page xxxi of xxxvi REJ09B0328-0300 27.3.1 27.3.2 27.3.3 27.3.4 27.3.5 27.3.6 27.3.7 27.3.8 27.3.9 Basic Operations .................................................................................................. Enable .................................................................................................................. Bcc Instruction..................................................................................................... BSR Instruction.................................................................................................... JSR Instruction..................................................................................................... JMP Instruction.................................................................................................... RTS Instruction.................................................................................................... SLEEP Instruction ............................................................................................... Competing Interrupt............................................................................................. 588 590 590 594 595 596 597 597 600 Section 28 Servo Circuits.................................................................................................. 605 28.1 Overview........................................................................................................................... 28.1.1 Functions.............................................................................................................. 28.1.2 Block Diagram..................................................................................................... 28.2 Servo Port ......................................................................................................................... 28.2.1 Overview.............................................................................................................. 28.2.2 Block Diagram..................................................................................................... 28.2.3 Pin Configuration................................................................................................. 28.2.4 Register Configuration......................................................................................... 28.2.5 Register Descriptions ........................................................................................... 28.2.6 DFG/DPG Input Signals ...................................................................................... 28.3 Reference Signal Generators............................................................................................. 28.3.1 Overview.............................................................................................................. 28.3.2 Block Diagram..................................................................................................... 28.3.3 Register Configuration......................................................................................... 28.3.4 Register Descriptions ........................................................................................... 28.3.5 Description of Operation...................................................................................... 28.4 HSW (Head-Switch) Timing Generator............................................................................ 28.4.1 Overview.............................................................................................................. 28.4.2 Block Diagram..................................................................................................... 28.4.3 Composition......................................................................................................... 28.4.4 Register Configuration......................................................................................... 28.4.5 Register Descriptions ........................................................................................... 28.4.6 Description of Operation...................................................................................... 28.4.7 Interrupt ............................................................................................................... 28.4.8 Cautions ............................................................................................................... 28.5 Four-Head High-Speed Switching Circuit for Special Playback ...................................... 28.5.1 Overview.............................................................................................................. 28.5.2 Block Diagram..................................................................................................... 28.5.3 Pin Configuration................................................................................................. Rev.3.00 Jan. 10, 2007 page xxxii of xxxvi REJ09B0328-0300 605 605 607 608 608 608 610 611 612 618 619 619 619 621 622 627 642 642 642 644 645 645 660 666 667 668 668 668 669 28.5.4 Register Description............................................................................................. 28.6 Drum Speed Error Detector .............................................................................................. 28.6.1 Overview.............................................................................................................. 28.6.2 Block Diagram ..................................................................................................... 28.6.3 Register Configuration......................................................................................... 28.6.4 Register Descriptions ........................................................................................... 28.6.5 Description of Operation...................................................................................... 28.6.6 fH Correction in Trick Play Mode......................................................................... 28.7 Drum Phase Error Detector............................................................................................... 28.7.1 Overview.............................................................................................................. 28.7.2 Block Diagram ..................................................................................................... 28.7.3 Register Configuration......................................................................................... 28.7.4 Register Descriptions ........................................................................................... 28.7.5 Description of Operation...................................................................................... 28.7.6 Phase Comparison................................................................................................ 28.8 Capstan Speed Error Detector ........................................................................................... 28.8.1 Overview.............................................................................................................. 28.8.2 Block Diagram ..................................................................................................... 28.8.3 Register Configuration......................................................................................... 28.8.4 Register Descriptions ........................................................................................... 28.8.5 Description of Operation...................................................................................... 28.9 Capstan Phase Error Detector ........................................................................................... 28.9.1 Overview.............................................................................................................. 28.9.2 Block Diagram ..................................................................................................... 28.9.3 Register Configuration......................................................................................... 28.9.4 Register Descriptions ........................................................................................... 28.9.5 Description of Operation...................................................................................... 28.10 X-Value and Tracking Adjustment Circuit ....................................................................... 28.10.1 Overview.............................................................................................................. 28.10.2 Block Diagram ..................................................................................................... 28.10.3 Register Descriptions ........................................................................................... 28.11 Digital Filters .................................................................................................................... 28.11.1 Overview.............................................................................................................. 28.11.2 Block Diagram ..................................................................................................... 28.11.3 Arithmetic Buffer................................................................................................. 28.11.4 Register Configuration......................................................................................... 28.11.5 Register Descriptions ........................................................................................... 28.11.6 Filter Characteristics ............................................................................................ 28.11.7 Operations in Case of Transient Response........................................................... -1 28.11.8 Initialization of Z ................................................................................................ 670 672 672 672 674 675 680 682 683 683 683 685 686 689 690 691 691 691 693 693 697 699 699 699 701 702 705 707 707 707 709 712 712 713 715 716 717 725 727 727 Rev.3.00 Jan. 10, 2007 page xxxiii of xxxvi REJ09B0328-0300 28.12 Additional V Signal Generator ......................................................................................... 28.12.1 Overview ............................................................................................................ 28.12.2 Pin Configuration ............................................................................................... 28.12.3 Register Configuration ....................................................................................... 28.12.4 Register Description ........................................................................................... 28.12.5 Additional V Pulse Signal .................................................................................. 28.13 CTL Circuit....................................................................................................................... 28.13.1 Overview ............................................................................................................ 28.13.2 Block Diagram ................................................................................................... 28.13.3 Pin Configuration ............................................................................................... 28.13.4 Register Configuration ....................................................................................... 28.13.5 Register Descriptions ......................................................................................... 28.13.6 Operation............................................................................................................ 28.13.7 CTL Input Section .............................................................................................. 28.13.8 Duty Discriminator............................................................................................. 28.13.9 CTL Output Section ........................................................................................... 28.13.10 Trapezoid Waveform Circuit.............................................................................. 28.13.11 Note on CTL Interrupt........................................................................................ 28.14 Frequency Dividers........................................................................................................... 28.14.1 Overview ............................................................................................................ 28.14.2 CTL Frequency Divider ..................................................................................... 28.14.3 CFG Frequency Divider ..................................................................................... 28.14.4 DFG Noise Removal Circuit .............................................................................. 28.15 Sync Signal Detector......................................................................................................... 28.15.1 Overview ............................................................................................................ 28.15.2 Block Diagram ................................................................................................... 28.15.3 Pin Configuration ............................................................................................... 28.15.4 Register Configuration ....................................................................................... 28.15.5 Register Descriptions ......................................................................................... 28.15.6 Noise Detection .................................................................................................. 28.15.7 Sync Signal Detector Activation ........................................................................ 28.16 Servo Interrupt .................................................................................................................. 28.16.1 Overview ............................................................................................................ 28.16.2 Register Configuration ....................................................................................... 28.16.3 Register Description ........................................................................................... 28.17 Module Stop Control Reigster (MSTPCR) ....................................................................... 729 729 730 730 730 732 735 735 736 737 737 738 750 753 756 762 765 766 766 766 766 770 778 781 781 781 783 783 784 790 793 794 794 794 794 801 Section 29 Electrical Characteristics ............................................................................. 803 29.1 Absolute Maximum Ratings ............................................................................................. 803 29.2 Electrical Characteristics of HD64F2194 ......................................................................... 804 Rev.3.00 Jan. 10, 2007 page xxxiv of xxxvi REJ09B0328-0300 29.2.1 DC Characteristics of HD64F2194 ...................................................................... 804 29.2.2 Allowable Output Currents of HD64F2194 and HD64F2194C........................... 810 29.2.3 AC Characteristics of HD64F2194 and HD64F2194C........................................ 811 29.2.4 Serial Interface Timing of HD64F2194 and HD64F2194C ................................. 815 29.2.5 A/D Converter Characteristics of HD64F2194 and HD64F2194C...................... 820 29.2.6 Servo Section Electrical Characteristics of HD64F2194 and HD64F2194C ....... 821 29.2.7 FLASH Memory Characteristics.......................................................................... 824 29.2.8 Usage Note........................................................................................................... 825 29.3 Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A............................................................. 826 29.3.1 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A................................................ 826 29.3.2 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A .......................... 832 29.3.3 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A................................................ 833 29.3.4 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A................................................ 837 29.3.5 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A .......................... 842 29.3.6 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A .......................... 843 Appendix A Instruction Set .............................................................................................. 847 A.1 A.2 A.3 A.4 A.5 A.6 Instructions........................................................................................................................ Instruction Codes .............................................................................................................. Operation Code Map......................................................................................................... Number of Execution States.............................................................................................. Bus Status during Instruction Execution ........................................................................... Change of Condition Codes .............................................................................................. 847 858 868 872 883 899 Appendix B Internal I/O Registers ................................................................................. 904 B.1 B.2 Addresses .......................................................................................................................... 904 Function List ..................................................................................................................... 913 Appendix C Pin Circuit Diagrams................................................................................. 1018 C.1 Pin Circuit Diagrams........................................................................................................ 1018 Appendix D Port States in the Difference Processing States................................. 1032 D.1 Pin Circuit Diagrams........................................................................................................ 1032 Rev.3.00 Jan. 10, 2007 page xxxv of xxxvi REJ09B0328-0300 Appendix E Usage Notes ................................................................................................. 1033 E.1 E.2 E.3 Power Supply Rise and Fall Order................................................................................... 1033 Pin Handling when the High-Speed Switching Circuit for Four-Head Special Playback Is Not Used ...................................................................................................................... 1034 Sample External Circuits ................................................................................................. 1035 Appendix F List of Product Codes ................................................................................ 1036 Appendix G External Dimensions................................................................................. 1037 Rev.3.00 Jan. 10, 2007 page xxxvi of xxxvi REJ09B0328-0300 Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2194 Group and H8S/2194C Group comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. The H8S/2194 Group and H8S/2194C Group are incorporated with digital servo circuit, ROM, RAM, seven types of timers, three types of PWM, two types of serial communication interface, 2 I C bus interface, A/D converter, and I/O port as on-chip supporting modules. The on-chip ROM is either flash memory (F-ZTATTM*) or mask ROM, with a capacity of 256, 192, 160, 128, 112, 96, or 80 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. The features of the H8S/2194 Group and H8S/2194C Group are shown in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Rev.3.00 Jan. 10, 2007 page 1 of 1038 REJ09B0328-0300 Section 1 Overview Table 1.1 Item CPU Features Specifications * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for real-time control Maximum operating frequency: 10 MHz/4 to 5.5 V Operable by 32-kHz subclock High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 100 ns (10-MHz operation) 16 x 16-bit register-register multiply: 2000 ns (10-MHz operation) 32 / 16-bit register-register divide: 2000 ns (10-MHz operation) * Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions * CPU operating modes Advanced mode: 16-Mbyte address space Timer Seven types of timer are incorporated * Timer A 8-bit interval timer Clock source can be selected among 8 types of internal clock of which frequencies are divided from the system clock () and subclock (SUB) Functions as clock time base by subclock input * Timer B Functions as 8-bit interval timer or reload timer Clock source can be selected among 7 types of internal clock or external event input * Timer J Functions as two 8-bit down counters or one 16-bit down counter (reload timer/event counter timer/timer output, etc., 5 types of operation modes) Remote controlled transmit function Take up/Supply Reel Pulse Frequency division Rev.3.00 Jan. 10, 2007 page 2 of 1038 REJ09B0328-0300 Section 1 Overview Item Timer Specifications * Timer L 8-bit up/down counter Clock source can be selected among 2 types of internal clock, CFG frequency division signal, and PB and REC-CTL (control pulse) Compare-match clearing function/auto reload function * Timer R Three reload timers Mode discrimination Reel control Capstan motor acceleration/deceleration detection function Slow tracking mono-multi * Timer X1 16-bit free-running counter Clock source can be selected among 3 types of internal clock and DVCFG Two output compare outputs Four input capture inputs * Watchdog timer Functions as watchdog timer or 8-bit interval timer Generates reset signal or NMI at overflow Prescaler unit * * * * * PWM * * * Divides system clock frequency and generates frequency division clock for supporting module functions Divides subclock frequency and generates input clock for Timer A (clock time base) Generates 8-bit PWM frequency and duty period 8-bit input capture at external signal edge Frequency division clock output enabled 14-bit PWM: Pulse resolution type x 1 channel 8-bit PWM: Duty control type x 4 channels 12-bit PWM: Pulse pitch control type x 2 channels Three types of PWM are incorporated Rev.3.00 Jan. 10, 2007 page 3 of 1038 REJ09B0328-0300 Section 1 Overview Item Serial communication interface (SCI) Specifications Two types of serial communication interface is incorporated * SCI1 Asynchronous mode or synchronous mode selectable Desired bit rate selectable with built-in baud rate generator Multiprocessor communication function * SCI2 32-byte data automatically transferrable Transfer clock selectable among seven types of internal/external clock I C bus interface 2 * * * * Conforms to Phillips I C bus interface standard Single master mode/slave mode Arbitration lost condition can be identified Supports two slave addresses Resolution: 10 bits Input: 12 channels High-speed conversion: 13.4 s minimum conversion time (10-MHz operation) Sample-and-hold function A/D conversion can be activated by software or external trigger Interrupt occurs when the preset address is found during bus cycle To-be-trapped addresses can be individually set at three different locations 60 input/output pins 8 input-only pins Can be switched for each supporting module Input and output circuits Error detection circuit Phase and gain compensation Can separately detect horizontal and vertical sync signals Noise detection function 2 A/D converter * * * * * Address trap controller I/O port * * * * * Servo circuit Digital servo circuits on-chip * * * Sync signal detector On-chip sync signal detection circuit * * Rev.3.00 Jan. 10, 2007 page 4 of 1038 REJ09B0328-0300 Section 1 Overview Item Memory Specifications * * Flash memory or mask ROM High-speed static RAM Product Name H8S/2194C H8S/2194B H8S/2194A H8S/2194 H8S/2193 H8S/2192 H8S/2191 Power-down state * * * * * Interrupt controller * * * Clock pulse generator * * Packages Product lineup Group H8S/2194C ROM 256 kbytes 192 kbytes 160 kbytes 128 kbytes 112 kbytes 96 kbytes 80 kbytes RAM 6 kbytes 6 kbytes 6 kbytes 3 kbytes 3 kbytes 3 kbytes 3 kbytes Medium-speed mode Sleep mode Module stop mode Standby mode Subclock operation Subactive mode, watch mode, subsleep mode Seven external interrupt pins (NMI, IRQ5 to IRQ0) 38 internal interrupt sources Three priority levels settable System clock pulse generator: 8 to 10 MHz Subclock pulse generator: 32.768 kHz 112-pin plastic QFP (FP-112) Part No. Mask ROM Versions HD6432194C HD6432194B HD6432194A H8S/2194 HD6432194 HD6432193 HD6432192 HD6432191 F-ZTAT Versions HD64F2194C HD64F2194 ROM/RAM (bytes) 256 k/6 k 192 k/6 k 160 k/6 k 128 k/3 k 112 k/3 k 96 k/3 k 80 k/3 k Packages FP-112 FP-112 FP-112 FP-112 FP-112 FP-112 FP-112 Two types of clock pulse generator on-chip * Rev.3.00 Jan. 10, 2007 page 5 of 1038 REJ09B0328-0300 Section 1 Overview 1.2 Internal Block Diagram An internal block diagram of the chip is shown in figure 1.1. X1 X2 OSC1 OSC2 External address bus NMI RES FWE MD0 VCC VCC VCC VCC VSS VSS VSS VSS VSS External address bus External data bus External data bus P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 P17/TMOW P16/IC P15/IRQ5 P14/IRQ4 P13/IRQ3 P12/IRQ2 P11/IRQ1 P10/IRQ0 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AN8 AN9 ANA ANB AVCC AVSS P87 P86 P85 P84 P83/SV2 P82/SV1 P81/EXCAP P80/EXTTRG Port 2 Internal data bus ROM Internal address bus Bus controller Address trap controller Prescaler unit Port 3 H8S/2000 CPU P37/TMO P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/STRB P30/CS P47 P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/PWM14 P53/TRIG P52/TMBI P51 P50/ADTRG P67/RP7 P66/RP6 P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 P77/PPG7 P76/PPG6 P75/PPG5 P74/PPG4 P73/PPG3 P72/PPG2 P71/PPG1 P70/PPG0 Port 1 Subclock pulse generator System clock pulse generator RAM Interrupt controller 8-bit PWM Watchdog timer Port 0 Timer L Timer B SCI1 SCI2 Timer J analog port I 2 C bus interface A/D converter Timer R Timer X1 Servo circuit Port 8 14-bit PWM Port 7 Sync signal detection Servo pins (CTL input/output amplifier, three-level output, etc.) SVCC SVSS Figure 1.1 Internal Block Diagram of H8S/2194 Group Rev.3.00 Jan. 10, 2007 page 6 of 1038 REJ09B0328-0300 H.Amp SW/PS1 C.Rotary/PS0 COMP/PS2 DPG/PS3 EXCTL/PS4 DFG DRMPWM CAPPWM AUDIO FF VIDEO FF Vpulse CLT(+) CLT(-) CTLBias CTLAmp(o) CTLSMT(i) CTLFB CTL REF CFG Csync Port 6 Port 5 Timer A Port 4 Section 1 Overview 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement The pin arrangement of the chip is shown in figure 1.2. VSS P72/PPG2 VCC P71/PPG1 P70/PPG0 P67/RP7 P66/RP6 P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 MD0 VCC OSC2 VSS OSC1 RES X1 X2 NMI FWE P17/TMOW P16/IC P15/IRQ5 P14/IRQ4 P13/IRQ3 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P73/PPG3 P74/PPG4 P75/PPG5 P76/PPG6 P77/PPG7 P80/EXTTRG P81/EXCAP P82/SV1 P83/SV2 P84 P85 P86 P87 Csync AUDIO FF VIDEO FF CAP PWM DRM PWM C.Rotary/PS0 H.Amp sw/PS1 COMP/PS2 EXCTL/PS4 DPG/PS3 DFG VCC Vpulse VSS CTLREF P12/IRQ2 P11/IRQ1 P10/IRQ0 P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 VCC P37/TMO VSS P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/STRB P30/CS P47 P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA FP-112 (Top view) CTL(+) SVSS CTL(-) CTLBias CTLFB CTLAmp(o) CTLSMT(i) CFG SVCC AVCC P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 AN8 AN9 ANA ANB AVSS P50/ADTRG P51 P52/TMBI P53/TRIG P40/PWM14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 1.2 Pin Arrangement of H8S/2194 Group Rev.3.00 Jan. 10, 2007 page 7 of 1038 REJ09B0328-0300 Section 1 Overview 1.3.2 Pin Functions Table 1.2 summarizes the functions of the chip's pins. Table 1.2 Type Pin Functions Symbol Pin No. I/O Name and Function Power supply: All Vcc pins should be connected to the system power supply (+ 5V) Ground: All Vss pins should be connected to the system power supply (0 V) Servo power supply: SVcc pin should be connected to the servo analog power supply (+5 V) Servo ground: SVss pin should be connected to the servo analog power supply (0 V) Analog power supply: Power supply pin for A/D converter. It should be connected to the system power supply (+5 V) when the A/D converter is not used Analog ground: Ground pin for A/D converter. It should be connected to the system power supply (0 V) Connected to a crystal oscillator. It can also input an external clock. See section 10, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input Connected to a 32.768 kHz crystal oscillator. See section 10, Clock Pulse Generator, for typical connection diagrams Mode pins: These pins set the operating mode. These pins should not be changed while the MCU is in operation Power supply Vcc 45, 70, 82, Input 109 43, 68, 84, Input 111 9 Input Vss SVcc SVss 2 Input AVcc 10 Input AVss 23 Input Clock OSC1 OSC2 67 69 Input Output X1 X2 Operating MD0 mode control 65 64 71 Input Output Input Rev.3.00 Jan. 10, 2007 page 8 of 1038 REJ09B0328-0300 Section 1 Overview Type System control Symbol RES FWE Pin No. 66 62 I/O Input Input Name and Function Reset input: When this pin is driven low, the chip is reset Flash memory enable: Enables/disables flash memory programming. This pin is available only with MCU with flash memory on-chip. For mask ROM type, do not connect anything to this pin External interrupt request 0: External interrupt input pin for which rising edge sense, falling edge sense or both edges sense are selectable External interrupt requests 1 to 5: External interrupt input pins for which rising or falling edge sense are selectable Interrupts IRQ0 54 Input IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 NMI 55 56 57 58 59 63 Input Input Nonmaskable interrupt: Nonmaskable interrupt input pin for which rising edge sense, falling edge sense or both edges sense are selectable Input capture input: Input capture input pin for prescaler unit Frequency division clock output: Output pin for clock of which frequency is divided by prescaler Timer B event input: Input pin for events to be input to Timer B counter Timer J event input: Input pin for events to be input to Timer J RDT1or RDT-2 counter Timer J timer output: Output pin for toggle at underflow of RDT-1 of Timer J, or remote controlled transmit data Timer J buzzer output: Output pin for toggle which is selectable among fixed frequency, 1 Hz frequency divided from subclock (32 kHz), and frequency division CTL signal Prescaler unit IC TMOW 60 61 Input Output Timers TMBI 26 Input IRQ1 IRQ2 TMO 55 56 44 Input Output BUZZ 42 Output Rev.3.00 Jan. 10, 2007 page 9 of 1038 REJ09B0328-0300 Section 1 Overview Type Timers Symbol IRQ3 Pin No. 57 I/O Input Name and Function Timer R input capture: Input pin for input capture of Timer R TMRU-1 or TMRU-2 Timer X1 output compare A and B output: Output pin for output compare A and B of Timer X1 Timer X1 input capture A, B, C, and D input: Input pin for input capture A, B, C, and D of Timer X1 8-bit PWM square waveform output: Output pin for waveform generated by 8-bit PWM 0, 1, 2, and 3 14-bit PWM square waveform output: Output pin for waveform generated by 14-bit PWM SCI clock input/output: Clock input pins for SCI 1 and 2 SCI receive data input: Receive data input pins for SCI 1 and 2 SCI transmit data output: Transmit data output pins for SCI 1 and 2 SCI2 strobe output: This pin outputs strobe pulse for each byte transmit by SCI2 SCI2 chip select input: This pin controls the transfer start of SCI2 I C bus interface clock input/output: 2 Clock input/output pin for I C bus interface I C bus interface data input/output: 2 Data input/output pin for I C bus interface 2 2 FTOA FTOB FTIA FTIB FTIC FTID PWM PWM0 PWM1 PWM2 PWM3 PWM14 33 34 29 30 31 32 38 39 40 41 28 Output Input Output Output Serial communication interface (SCI) SCK1 SCK2 SI1 SI2 SO1 SO2 STRB 48 53 46 51 47 52 37 Input/ output Input Output Output CS I C bus interface 2 36 50 49 Input Input/ output Input/ output SCL SDA Rev.3.00 Jan. 10, 2007 page 10 of 1038 REJ09B0328-0300 Section 1 Overview Type A/D converter Symbol Pin No. I/O Input Name and Function Analog input channels 7 to 0: Analog data input pins. A/D conversion is started by a software triggering Analog input channels 8, 9, A, and B: Analog data input pins. A/D conversion is started by an external, hardware, or software triggering A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion Audio FF: Output pin for audio head switching signal Video FF: Output pin for video head switching signal Capstan mix: 12-bit PWM output pin giving result of capstan speed error and phase error after filtering Drum mix: 12-bit PWM output pin giving result of drum speed error and phase error after filtering Additional V pulse: Three-level output pin for additional V signal synchronized to the Video FF signal Color rotary signal: Output pin for color signal processing control signal in four-head special-effects playback Head-amp switch: Output pin for preamplifier output select signal in four-head special-effects playback. This pin can also be used as a general port when not used AN7 to AN0 18 to 11 AN8 AN9 ANA ANB ADTRG 19 20 21 22 24 Input Input Servo circuits AUDIO FF VIDEO FF CAPPWM 99 100 101 Output Output Output DRMPWM 102 Output Vpulse 110 Output C.Rotary/ PS0 103 Output, input/ output Output, input/ output H.AmpSW/P 104 S1 COMP/ PS2 105 Input, input/ Compare input: output Input pin for signal giving the result of preamplifier output comparison in four-head special-effects playback. This pin can also be used as a general port when not used Input/ output Input CTL head (+) and (-) pins: I/O pins for CTL signals CTL primary amp bias supply: Bias supply pin for CTL primary amp CTL (+) CTL (-) CTL Bias 1 3 4 Rev.3.00 Jan. 10, 2007 page 11 of 1038 REJ09B0328-0300 Section 1 Overview Type Servo circuits Symbol Pin No. I/O Output Input Input Name and Function CTL amp output: Output pin for CTL amp CTL Schmitt amp input: Input pin for CTL Schmitt amp CLT feedback input: Input pin for CTL amp high-range characteristics control CTL amp reference voltage output: Output pin for 1/2 Vcc (SV) Capstan FG input: Schmitt comparator input pin for CFG signal Drum FG input: Schmitt input pin for DFG signal CTL Amp (o) 6 CTL SMT (l) 7 CTLFB 5 CTLREF CFG DFG DPG/PS3 112 8 108 107 Output Input Input Input, input/ Drum PG input: output Schmitt input pin for DPG signal. This pin can also be used as a general port when not used Input, input/ External CTL input: output Input pin for external CTL signal. This pin can also be used as a general port when not used Input Input Mixed sync signal input: Input pin for mixed sync signal Capstan external sync signal input: Signal input pin for external synchronization of capstan phase control External trigger signal input: Signal input pin for synchronization with reference signal generator Servo monitor output pin 1: Output pin for servo module internal signal Servo monitor output pin 2: Output pin for servo module internal signal PPG: Output pin for HSW timing generator. To be used when head switching is required as well as Audio FF and Video FF EXCTL/ PS4 Csync EXCAP 106 98 91 EXTTRG 90 Input SV1 SV2 PPG7 to PPG0 92 93 Output Output 89 to 85, Output 83, 81, 80 Rev.3.00 Jan. 10, 2007 page 12 of 1038 REJ09B0328-0300 Section 1 Overview Type I/O port Symbol P07 to P00 P17 to P10 P27 to P20 P37 to P30 P47 to P40 P53 to P50 P67 to P60 P77 to P70 P87 to P80 RP7 to RP0 TRIG Pin No. 11 to 18 61 to 54 53 to 46 44, 42 to 36 35 to 28 27 to 24 79 to 72 I/O Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Name and Function Port 0: 8-bit input pins Port 1: 8-bit I/O pins Port 2: 8-bit I/O pins Port 3: 8-bit I/O pins Port 4: 8-bit I/O pins Port 5: 4-bit I/O pins Port 6: 8-bit I/O pins Port 7: 8-bit I/O pins Port 8: 8-bit I/O pins Realtime output port: 8-bit realtime output pins Realtime output port trigger input: Input pin for realtime output port trigger 89 to 85, Input/ 83, 81, 80 output 97 to 90 79 to 72 27 Input/ output Output Input Rev.3.00 Jan. 10, 2007 page 13 of 1038 REJ09B0328-0300 Section 1 Overview 1.4 Differences between H8S/2194C Group and H8S/2194 Group Though the H8S/2194C Group is compatible with the H8S/2194 Group and their supporting modules are almost identical, there are some differences between them as shown below. For details, see the following sections. Table 1.3 Differences between H8S/2194C Group and H8S/2194 Group H8S/2194C Group ROM H8S/2194C: 256 kbytes H8S/2194B: 192 kbytes H8S/2194A: 160 kbytes H8S/2194 Group H8S/2194: 128 kbytes H8S/2193: 112 kbytes H8S/2192: 96 kbytes H8S/2191: 80 kbytes RAM H8S/2194C: 6 kbytes H8S/2194B: 6 kbytes H8S/2194A: 6 kbytes H8S/2194: 3 kbytes H8S/2193: 3 kbytes H8S/2192: 3 kbytes H8S/2191: 3 kbytes Timer J Five operating modes: TMJ-2 input clock Four operating modes: TMJ-2 input sources: PSS = /16384, /2048, or clock sources: PSS = /16384 or /1024; underflow of TMJ-1, external /2048; underflow of TMJ-1, external clock (IRQ2) clock (IRQ2) In the reference signal generator, the servo circuit selects whether reference signals are generated with VD when it is in PB mode, or in free-run 256 kbytes In the reference signal generator, when the servo circuit is in PB mode, reference signals are generated in free-run 128 kbytes Servo circuit Flash ROM When the flash ROM control flag is set, When the flash ROM control flag is use the E (erase) bit and the P (program) set, use the E (erase) bit and the P bit in flash memory control register 1 (program) bit in flash memory control (FMLCR1). register 2 (FMLCR2). Rev.3.00 Jan. 10, 2007 page 14 of 1038 REJ09B0328-0300 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) Rev.3.00 Jan. 10, 2007 page 15 of 1038 REJ09B0328-0300 Section 2 CPU * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8 x 8-bit register-register multiply: 16 / 8-bit register-register divide: 16 x 16-bit register-register multiply: 32 / 16-bit register-register divide: * Two CPU operating modes Normal mode*/Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available for this LSI. 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU 10 MHz 1200 ns 1200 ns 2000 ns 2000 ns 8/16/32-bit register-register add/subtract: 100 ns The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of execution states of the MULXU and MULXS instructions differ as follows. Number of Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, Erd MULXS MULXS.B Rs, Rd MULXS.W Rs, Erd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, EXR register functions, power-down state, etc., depending on the product. Rev.3.00 Jan. 10, 2007 page 16 of 1038 REJ09B0328-0300 Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers, and one 8-bit control register, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing mode The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev.3.00 Jan. 10, 2007 page 17 of 1038 REJ09B0328-0300 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected by the mode pins of the microcontroller. Maximum 64 kbytes for program and data areas combined Normal mode* CPU operating mode Advanced mode Note: * Normal mode is not available for this LSI. Maximum 16 Mbytes for program and data areas combined Figure 2.1 CPU Operating Modes 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev.3.00 Jan. 10, 2007 page 18 of 1038 REJ09B0328-0300 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 5, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 5, Exception Handling. Rev.3.00 Jan. 10, 2007 page 19 of 1038 REJ09B0328-0300 Section 2 CPU SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.3 Stack Structure in Normal Mode 2.2.2 Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 5, Exception Handling. Rev.3.00 Jan. 10, 2007 page 20 of 1038 REJ09B0328-0300 Section 2 CPU H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 5, Exception Handling. Rev.3.00 Jan. 10, 2007 page 21 of 1038 REJ09B0328-0300 Section 2 CPU SP Reserved PC (24 bits) SP CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.5 Stack Structure in Advanced Mode Rev.3.00 Jan. 10, 2007 page 22 of 1038 REJ09B0328-0300 Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used with this LSI H'FFFFFFFF (a) Normal mode* (b) Advanced mode Note: * Normal mode is not available for this LSI. Figure 2.6 Memory Map Rev.3.00 Jan. 10, 2007 page 23 of 1038 REJ09B0328-0300 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 76543210 * T - - - - I2 I1 I0 EXR 76543210 CCR I UI H U N Z V C Legend: : SP : PC EXR : : T I2 to I0 : CCR : : I : UI Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * Does not affect operation in this LSI. Figure 2.7 CPU Registers Rev.3.00 Jan. 10, 2007 page 24 of 1038 REJ09B0328-0300 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. Address registers 32-bit registers 16-bit registers 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Rev.3.00 Jan. 10, 2007 page 25 of 1038 REJ09B0328-0300 Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) An 8-bit register. In this LSI, this register does not affect operation. Bit 7Trace Bit (T): This bit is reserved. In this LSI, this bit does not affect operation. Bits 6 to 3Reserved: This bit is reserved. In this LSI, this bit does not affect operation. Bits 2 to 0Interrupt Mask Bits (I2 to I0):These bits are reserved. In this LSI, these bits do not affect operation. (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Rev.3.00 Jan. 10, 2007 page 26 of 1038 REJ09B0328-0300 Section 2 CPU Bit 7Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, see section 6, Interrupt Controller. Bit 6User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, see section 6, Interrupt Controller. Bit 5Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Bit 0Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the carry The carry flag is also used as a bit accumulator by bit-manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, see appendix A.1, Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Rev.3.00 Jan. 10, 2007 page 27 of 1038 REJ09B0328-0300 Section 2 CPU 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. Rev.3.00 Jan. 10, 2007 page 28 of 1038 REJ09B0328-0300 Section 2 CPU 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data type General Register Data Format 7 0 Don't care 1-bit data RnH 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 4-bit BCD data RnH 7 43 0 Don't care Upper digit Lower digit 4-bit BCD data RnL Don't care 7 43 0 Upper digit Lower digit Byte data RnH 7 0 Don't care MSB LSB Byte data RnL Don't care 7 0 MSB LSB Figure 2.10 General Register Data Formats (1) Rev.3.00 Jan. 10, 2007 page 29 of 1038 REJ09B0328-0300 Section 2 CPU Data Type General Register Data format Word data Rn 15 0 MSB Word data 15 En 0 LSB MSB Longword data 31 ERn LSB 16 15 0 MSB En Rn LSB Legend: ERn : General register ER En Rn : General register E : General register R RnH : General register RH RnL : General register RL MSB : Most significant bit LSB : Least significant bit Figure 2.10 General Register Data Formats (2) Rev.3.00 Jan. 10, 2007 page 30 of 1038 REJ09B0328-0300 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 Data Format 0 5 4 3 2 1 0 Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev.3.00 Jan. 10, 2007 page 31 of 1038 REJ09B0328-0300 Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* 1 1 Size BWL WL L B BWL B BWL L BW WL B BWL Types 5 LDM, STM 3 3 MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* Logic operations Shift Bit manipulation Branch System control Block data transfer Legend: B: Byte W: Word L: Longword AND, OR, XOR, NOT 19 4 8 14 5 9 1 Total: 65 types SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, BWL ROTXR RSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, B BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* , JMP, BSR, JSR, RTS 2 TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Rev.3.00 Jan. 10, 2007 page 32 of 1038 REJ09B0328-0300 Section 2 CPU Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @SP. 2. Bcc is the general name for conditional branch instructions. 3. Not available in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Jan. 10, 2007 page 33 of 1038 REJ09B0328-0300 Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes @-ERn/@ERn+ Function @(d:16, ERn) @(d:32, ERn) @(d:8, PC) @(d:16, PC) @aa:16 @aa:24 @aa:32 @aa:8 @ERn #xx Rn @@aa:8 Instruction MOV POP, PUSH LDM, STM MOVFPE, MOVTPE*1 ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS*2 AND, OR, XOR NOT Data transfer BWL -- -- -- BWL WL B -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- B -- B -- -- BWL -- -- -- BWL BWL B L BWL B BW BW BWL WL -- BWL BWL BWL B -- -- -- -- -- -- B B -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- B -- -- -- -- -- -- W W -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- BWL -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Shift Bit manipulation Bcc, BSR Branch JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer System control Logic operation Arithmetic operations -- -- -- BW Legend: B: Byte W: Work L: Longword Notes: 1. Cannot be used in this LSI. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Jan. 10, 2007 page 34 of 1038 REJ09B0328-0300 -- Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 to 2.10 summarize the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM Disp + - x / :8/:16/:24/:32 Note: * General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.3.00 Jan. 10, 2007 page 35 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI Cannot be used in this LSI @SP+ Rn Pops a general register from the stack POP.W Rn is identical to MOV.W @SP+, Rn POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn @-SP Pushes a general register onto the stack PUSH.W Rn is identical to MOV.W Rn, @-SP PUSH.L ERn is identical to MOV.L ERn, @-SP LDM STM Note: * L L @SP+ Rn (register list) Pops two or more general registers from the stack Rn (register list) @-SP Pushes two or more general registers onto the stack Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Jan. 10, 2007 page 36 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Instructions Size* 1 Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction) B/W/L ADDX SUBX B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register INC DEC ADDS SUBS DAA DAS MULXU B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only) B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register B/W Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x16 bits 32 bits MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x16 bits 32 bits DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits x 8-bit quotient and 8-bit remainder or 32 bits / 16 bits x 16-bit quotient and 16-bit remainder Rev.3.00 Jan. 10, 2007 page 37 of 1038 REJ09B0328-0300 Section 2 CPU Instruction DIVXS Size* B/W 1 Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit TAS B @ERd - 0, 1 ( 2 Tests memory contents, and sets the most significant bit (bit 7) to 1 Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Jan. 10, 2007 page 38 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.5 Instruction AND Logic Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B/W/L ~ Rd Rd Takes the one's complement (logical complement) of general register contents Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents A 1-bit or 2-bit shift is possible B/W/L Rd (shift) Rd Performs a logical shift on general register contents A 1-bit or 2-bit shift is possible B/W/L Rd (rotate) Rd Rotates general register contents 1-bit or 2-bit rotation is possible B/W/L Rd (rotate) Rd Rotates general register contents through the carry flag 1-bit or 2-bit rotation is possible Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Jan. 10, 2007 page 39 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions Size* B Function 1 ( BCLR B 0 ( BNOT B ~ ( BTST B ~ ( BAND B C ( BIAND B C [~( BOR B C ( BIOR B C [~( Rev.3.00 Jan. 10, 2007 page 40 of 1038 REJ09B0328-0300 Section 2 CPU Instruction BOXR Size* B Function C ( Rev.3.00 Jan. 10, 2007 page 41 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size* Function Branches to a specified address if a specified condition is true The branching conditions are listed below Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (True) Never (False) HIgh Low of Same Carry Clear (High or Same) Carry Set (LOw) Not Equal EQual oVerflow Clear oVerflow Set PLus MInus Greater or Equal Less Than Greater Than Less or Equal Condition Always Never CVZ = 0 CVZ = 1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev.3.00 Jan. 10, 2007 page 42 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* B/W Function Starts trap-instruction exception handling Returns from an exception-handling routine Causes a transition to a power-down state (EAs) CCR, (EAs) EXR Moves contents of a general register or memory or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid ANDC ORC XORC B B B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data NOP Note: * PC + 2 PC Only increments the program counter Size refers to the operand size. B: Byte W: Word Rev.3.00 Jan. 10, 2007 page 43 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size* Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6 R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed EEPMOV.W Rev.3.00 Jan. 10, 2007 page 44 of 1038 REJ09B0328-0300 Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. rn rm MOV.B@(d:16, Rn), Rm, etc. Figure 2.12 Instruction Formats (Examples) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. Condition Field: Specifies the branching condition of Bcc instructions. Rev.3.00 Jan. 10, 2007 page 45 of 1038 REJ09B0328-0300 Section 2 CPU 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/#@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register DirectRn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Rev.3.00 Jan. 10, 2007 page 46 of 1038 REJ09B0328-0300 Section 2 CPU (2) Register Indirect@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand in memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn * Register indirect with post-increment@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. (5) Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 indicates the accessible absolute address ranges. Rev.3.00 Jan. 10, 2007 page 47 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF (6) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Rev.3.00 Jan. 10, 2007 page 48 of 1038 REJ09B0328-0300 Section 2 CPU Note that the first part of the address range is also the exception vector area. For further details, see section 5, Exception Handling. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev.3.00 Jan. 10, 2007 page 49 of 1038 REJ09B0328-0300 Section 2 CPU Table 2.13 Effective Address Calculation No. 1 Addressing Mode and Instruction Format Register direct (Rn) op rm rn Effective Address Calculation Effective Address (EA) Operand is general register contents 2 Register indirect (@ERn) 31 General register contents op r 0 31 24 23 0 Don't care 3 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 31 General register contents 31 op r disp 31 Sign extension disp 0 24 23 0 Don't care 0 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 1, 2, or 4 * Register indirect with pre-decrement @-ERn 31 General register contents 31 op r Operand Size Byte Word Longword Value Added 1 2 4 1, 2, or 4 24 23 0 Don't care 0 Rev.3.00 Jan. 10, 2007 page 50 of 1038 REJ09B0328-0300 Section 2 CPU Addressing Mode and Instruction Format Absolute address @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care No. 5 Effective Address Calculation Effective Address (EA) @aa:16 op abs 31 Don't care 24 23 16 15 Sign extension 0 @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data 7 Program-counter relative @(d:8, PC)/@(d:16, PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care Rev.3.00 Jan. 10, 2007 page 51 of 1038 REJ09B0328-0300 Section 2 CPU Addressing Mode and Instruction Format Memory indirect @@aa:8 * Normal mode* op abs No. 8 Effective Address Calculation Effective Address (EA) 31 H'000000 87 abs 0 31 24 23 16 15 0 Don't care 15 Memory contents 0 H'00 * Advanced mode op abs 31 H'000000 87 abs 0 31 Memory contents 0 31 24 23 0 Don't care Note: * Not available in this LSI. Rev.3.00 Jan. 10, 2007 page 52 of 1038 REJ09B0328-0300 Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has four main processing states: the reset state, exception-handling state, program execution state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Sleep mode Power-down state CPU operation is stopped to conserve power.* Standby mode Note: * The power-down state also includes a medium-speed mode, modue stop mode, sub-active mode, sub-sleep mode and watch mode. Figure 2.14 Processing States Rev.3.00 Jan. 10, 2007 page 53 of 1038 REJ09B0328-0300 Section 2 CPU Program execution state ha nd pt ion ling ha nd lin g S w LE SS ith EP BY LS in Os = N tru 0 = cti 0, on pt io n Sleep mode ce ce tf or En d es Re qu Int upt err req of u est S w LE TM ith EP SS A LS in BY 3 = ON str u = 0, = ctio 0, n 0 ex Exception-handling state ex External interrupt request Standby mode RES = High Power-down state*2 Reset state*1 Notes: 1. From any state, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details, see section 4, Power-Down State. Figure 2.15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are disabled in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, see section 18, Watchdog Timer (WDT). Rev.3.00 Jan. 10, 2007 page 54 of 1038 REJ09B0328-0300 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.14 Exception Handling Types and Priority Priority High Type of Exception Reset Detection Timing Start of Exception Handling Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows End of instruction execution or end of exception-handling 1 sequence* When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Interrupt Low Trap instruction When TRAPA instruction Exception handling starts when a trap 2 is executed (TRAPA) instruction is executed* Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 2. Trap instruction exception handling is always accepted in the program execution state. (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU Rev.3.00 Jan. 10, 2007 page 55 of 1038 REJ09B0328-0300 Section 2 CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. Normal Mode*2 Advanced Mode SP CCR CCR*1 PC (16 bits) SP CCR PC (24 bits) Notes: 1. Ignored when returning. 2. Normal mode is not available for this LSI. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. Rev.3.00 Jan. 10, 2007 page 56 of 1038 REJ09B0328-0300 Section 2 CPU 2.8.5 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU operates on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. For details, see section 4, Power-Down State. (1) Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Standby Mode A transition to standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the TMA3 bit in the TMA (timer A) are both cleared to 0. In standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. Rev.3.00 Jan. 10, 2007 page 57 of 1038 REJ09B0328-0300 Section 2 CPU 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one or two states. Different methods are used to access on-chip memory and on-chip supporting modules. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Bus cycle T1 Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Figure 2.17 On-Chip Memory Access Cycle Rev.3.00 Jan. 10, 2007 page 58 of 1038 REJ09B0328-0300 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.18 shows the access timing for the on-chip supporting modules. Bus cycle T1 Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Address T2 Figure 2.18 On-Chip Supporting Module Access Cycle 2.10 Usage Note Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S or H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. Rev.3.00 Jan. 10, 2007 page 59 of 1038 REJ09B0328-0300 Section 2 CPU Rev.3.00 Jan. 10, 2007 page 60 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection This LSI has one operating mode (mode 1). This mode is selected depending on settings of the mode pin (MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MD0 0 1 CPU Operating Mode Advanced Description Single-chip mode MCU Operating Mode 0 1 The CPU's architecture allows for 4 Gbytes of address space, but this LSI actually accesses a maximum of 16 Mbytes. Mode 1 operation starts in single-chip mode after reset release. This LSI can only be used in mode 1. This means that the mode pins must be set at mode 1. Do not changes the inputs at the mode pins during operation. 3.1.2 Register Configuration This LSI has a mode control register (MDCR) that indicates the inputs at the mode pin (MD0) and a system control register (SYSCR) and that controls the operation of this LSI. Table 3.2 summarizes these registers. Table 3.2 Name Mode control register System control register Note: * MCU Registers Abbreviation MDCR SYSCR R/W R/W R/W Initial Value Undetermined H'09 Address* H'FFE9 H'FFE8 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 61 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes 3.2 3.2.1 Register Descriptions Mode Control Register (MDCR) Bit : 7 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 MDS0 --* R Initial value : R/W : 0 -- Note: * Determined by MD0 pin MDCR is an 8-bit read-only register monitors the current operating mode of this LSI. Bits 7 to 1Reserved: These bits cannot be modified and are always set at 0. Bit 0Mode Select 0 (MDS0): This bit indicates the value which reflects the input levels at mode pin (MD0) (the current operating mode). Bit MDS0 corresponds to MD0 pin. It is read-only bit and cannot be written to. The mode pin (MD0) input levels are latched into these bits when MDCR is read. 3.2.2 System Control Register (SYSCR) Bit : 7 -- Initial value : R/W : 0 -- 6 -- 0 -- 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 1 0 -- 1 -- NMIEG1 NMIEG0 0 R/W 0 R/W Bits 7 and 6Reserved. Bits 5 and 4Interrupt Control Modes 1 and 0 (INTM1, INTM0): These bits are for selecting the interrupt control mode of the interrupt controller. For details of the interrupt control modes, see section 6.4, Interrupt Operation. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 1 2 3 Description Interrupt is controlled by bit I (Initial value) Interrupt is controlled by bits I and UI, and ICR Cannot be used in this LSI Cannot be used in this LSI Rev.3.00 Jan. 10, 2007 page 62 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes Bit 3External Reset (XRST) : Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. Bit 3 XRST 0 1 Description A reset is generated by watchdog timer overflow A reset is generated by an external reset (Initial value) Bits 2 and 1NMI Edge Select 1 and 0 (NMIG1, 0) : Select the input edge for NMI interrupt. Bit 2 NIMIEG1 0 Bit 1 NIMIEG0 0 1 1 * Legend: * Don't care Description An interrupt request occurs at falling edge of NMI input An interrupt request occurs at rising edge of NMI input An interrupt request occurs at rising or falling edge of NMI input (Initial value) Bit 0Reserved. 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 16 Mbyte address space in advanced mode. Rev.3.00 Jan. 10, 2007 page 63 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes 3.4 Address Map H8S/2191 H'000000 Vector area H'0000FF On-chip ROM (80 kbytes) H'007FFF H'013FFF H'017FFF Absolute address, 16 bits Memory indirect branch address H8S/2192 H'000000 Vector area On-chip ROM (96 kbytes) H'FF8000 H'FFF3B0 Absolute address, 16 bits H'FFD000 Internal I/O register H'FFD2FF H'FFD000 Internal I/O register H'FFD2FF H'FFF3B0 3 kbytes H'FFFF00 H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Absolut e address, 8 bits On-chip RAM (3 kbytes) On-chip RAM (3 kbytes) H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Figure 3.1 Address Map (1) Rev.3.00 Jan. 10, 2007 page 64 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes H8S/2193 H'000000 Vector area H'000000 H8S/2194 Vector area On-chip ROM (112 kbytes) On-chip ROM (128 kbytes) H'01BFFF H'01FFFF H'FFD000 Internal I/O register H'FFD2FF H'FFD000 Internal I/O register H'FFD2FF H'FFF3B0 H'FFF3B0 On-chip RAM (3 kbytes) On-chip RAM (3 kbytes) H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Figure 3.2 Address Map (2) Rev.3.00 Jan. 10, 2007 page 65 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes H8S/2191A H'000000 Vector area H'0000FF On-chip ROM (160 kbytes) H'007FFF H'027FFF H'02FFFF Absolute address, 16 bits Memory indirect branch address H8S/2194B H'000000 Vector area On-chip ROM (192 kbytes) H'FF8000 H'FFE7B0 Absolute address, 16 bits H'FFD000 Internal I/O register H'FFD2FF H'FFD000 Internal I/O register H'FFD2FF H'FFE7B0 6 kbytes H'FFFF00 H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Absolute address, 8 bits On-chip RAM (6 kbytes) On-chip RAM (6 kbytes) H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Figure 3.3 Address Map (3) Rev.3.00 Jan. 10, 2007 page 66 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes H8S/2194C H'000000 Vector area On-chip ROM (256 kbytes) H'03FFFF H'FFD000 Internal I/O register H'FFD2FF H'FFE7B0 On-chip RAM (6 kbytes) H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Figure 3.4 Address Map (4) Rev.3.00 Jan. 10, 2007 page 67 of 1038 REJ09B0328-0300 Section 3 MCU Operating Modes Rev.3.00 Jan. 10, 2007 page 68 of 1038 REJ09B0328-0300 Section 4 Power-Down State Section 4 Power-Down State 4.1 Overview In addition to the normal program execution state, this LSI has a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. This LSI operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3. Subactive mode 4. Sleep mode 5. Subsleep mode 6. Watch mode 7. Module stop mode 8. Standby mode Of these, 2 to 8 are power-down modes. Certain combinations of these modes can be set. After a reset, the MCU is in high-speed mode. Table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for transition to the various modes. Figure 4.1 shows a mode transition diagram. Rev.3.00 Jan. 10, 2007 page 69 of 1038 REJ09B0328-0300 Section 4 Power-Down State Table 4.1 Function System clock Subclock pulse generator Internal Chip States in Each Mode MediumHigh-Speed Speed Sleep Module Stop Watch Subactive Halted Subsleep Halted Standby Halted Functioning Functioning Functioning Functioning Halted Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Retained Functioning Halted Retained Subclock operation Halted Retained Halted Retained CPU Instructions Functioning Mediumspeed operation Registers External NIMI interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 On-chip Timer A supporting module operation Timer B Timer J Timer L Timer R Timer X1 Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Halted Functioning Halted Functioning Functioning Functioning Functioning/ Subclock halted operation (retained) Functioning Functioning Functioning Functioning/ Halted halted (retained) (retained) Subclock operation Halted (retained) Subclock operation Halted (retained) Halted (retained) Halted (retained) Functioning/ Halted halted (reset) (reset) Functioning Functioning Functioning Functioning Halted (retained) Functioning Functioning Functioning Functioning Subclock operation Functioning/ Halted halted (reset) (reset) Functioning/ Halted halted (retained) (retained) Functioning/ Halted halted (reset) (reset) Functioning Functioning Retained Functioning Halted Functioning/ Halted halted (reset) (reset) Halted (reset) Halted (retained) Subclock operation Halted (reset) Halted (retained) Halted (reset) Halted (retained) Subclock operation Halted (reset) Halted (retained) Halted (reset) Halted (retained) Halted Halted (reset) Halted (retained) Watchdog timer PSU IIC SCI1 SCI2 14-bit PWM 8-bit PWM A/D Halted (reset) Halted (reset) Halted (reset) Halted Halted (reset) I/O Functioning Retained Halted (reset) Halted (reset) 12-bit PWM Functioning Functioning Halted (reset) Servo Notes: 1. "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." 2. "Halted (reset)" means that internal register values and internal states are initialized. 3. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 4. In the power-down mode, the analog section of the servo circuits are not turned off, therefore Vcc (Servo) current does not go low. When power-down is needed, externally shut down the analog system power. Rev.3.00 Jan. 10, 2007 page 70 of 1038 REJ09B0328-0300 Section 4 Power-Down State Reset state Program-halted state Program execution state Program-halted state Standby mode SLEEP instruction a Interrupt 1 SLEEP instruction a Interrupt 1 SLEEP instruction b Active (high-speed) mode g h SLEEP instruction c SLEEP instruction e Interrupt 3 SLEEP instruction d Sleep (high-speed) mode Interrupt 2 SLEEP instruction b Active (medium-speed) mode SLEEP instruction d SLEEP instruction e Interrupt 3 Sleep (medium-speed) mode SLEEP Interrupt 2 instruction c SLEEP instruction b Interrupt 2 Watch mode Subactive mode SLEEP instruction 1 Interrupt 4 Subsleep mode Power-down mode Conditions for mode transition (1) Flag LSON SSBY TMA3 DTON a b c d e f g h 0 * 0 1 0 1 1 1 1 1 0 0 0 1 1 1 * 1 * 0 1 1 * * 1 2 3 4 Conditions for mode transition (2) Interruption factor NMI, IRQ0 to 1 NMI, IRQ0 to 1, Timer A interruption All interruption (excluding servo system) NMI, IRQ0 to 5, Timer A interruption SCK1 to 0 = 0 SCK1 to 0 0 (either 1 bit = 0) Legend: * Don't care Note: When a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request Figure 4.1 Mode Transitions Rev.3.00 Jan. 10, 2007 page 71 of 1038 REJ09B0328-0300 Section 4 Power-Down State Table 4.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition SSBY TMA3 * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 LSON 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 DTON * * * * 0 0 1 1 * * * * 0 0 1 1 State before Transition State after Transition by SLEEP Instruction Sleep Standby Watch Watch Subactive Subsleep Watch Watch High-speed/ 2 medium-speed* State after Return by Interrupt High-speed/ 1 medium-speed* High-speed/ 1 medium-speed* High-speed/ 1 medium-speed* Subactive Subactive High-speed/ 2 medium-speed* Subactive High-speed/ 0 medium-speed 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 Legend: * Don't care : Do not set. Notes: 1. Returns to the state before transition. 2. Mode varies depending on the state of SCK1 to SCK0. Rev.3.00 Jan. 10, 2007 page 72 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR registers. Table 4.3 summarizes these registers. Table 4.3 Name Standby control register Low-power control register Module stop control register Power-Down State Registers Abbreviation SBYCR LPWRCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'FF H'FF H'30 Address* H'FFEA H'FFEB H'FFEC H'FFED H'FFBA Timer mode register Note: * TMA Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 73 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.2 4.2.1 Register Descriptions Standby Control Register (SBYCR) Bit : 7 SSBY 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 -- 0 -- 2 -- 0 -- 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : 0 R/W SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset. Bit 7Software Standby (SSBY): Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc. Bit 7 SSBY 0 Description Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode (Initial value) 1 Transition to standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode Rev.3.00 Jan. 10, 2007 page 74 of 1038 REJ09B0328-0300 Section 4 Power-Down State Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. With crystal oscillation, see table 4.5 and make a selection according to the operating frequency so that the standby time is at least 10 ms (the oscillation settling time). With an external clock, any selection can be made. (With FLASH ROM version, do not set the standby time to 16 states.) Bit 6 STS2 0 0 0 0 1 1 1 Bit 5 STS1 0 0 1 1 0 0 1 Bit 4 STS0 0 1 0 1 0 1 * Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states 1 Standby time = 16 states* Legend: * Don't care Note: 1. With FLASH ROM version, do not set the standby time to 16 states. The standby time is 32 states when transited to medium-speed mode /32 (SCK1 = 1, SCK0 = 0). Bits 3 and 2Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0System Clock Select 1, 0 (SCK1, SCK0): These bits select the CPU clock for the bus master in high-speed mode and medium-speed mode. Bit 1 SCK1 0 0 1 1 Bit 0 SCK0 0 1 0 1 Description Bus master is in high-speed mode (Initial value) Medium-speed clock is /16 Medium-speed clock is /32 Medium-speed clock is /64 Rev.3.00 Jan. 10, 2007 page 75 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.2.2 Low-Power Control Register (LPWRCR) Bit : 7 DTON 6 LSON 0 R/W 5 NESEL 0 R/W 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 SA1 0 R/W 0 SA0 0 R/W Initial value : R/W : 0 R/W LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset. Bit 7Direct-Transfer on Flag (DTON): Specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a SLEEP instruction. The operating mode to which the transition is made after SLEEP instruction execution is determined by a combination of other control bits. Bit 7 DTON 0 Description * * 1 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) When a SLEEP instruction is executed in high-speed mode or medium-speed mode, transition is made directly to subactive mode, or a transition is made to sleep mode or standby mode When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode * Rev.3.00 Jan. 10, 2007 page 76 of 1038 REJ09B0328-0300 Section 4 Power-Down State Bit 6Low-Speed on Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared. Bit 6 LSON 0 Description * * * 1 * * * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, transition is made to sleep mode, standby mode, or watch mode When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode After watch mode is cleared, a transition is made to high-speed mode (Initial value) When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode, subactive mode, sleep mode or standby mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode After watch mode is cleared, a transition is made to subactive mode Bit 5Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which the subclock (w) generated by the subclock pulse generator is sampled with the clock () generated by the system clock oscillator. When = 5 MHz or higher, clear this bit to 0. Bit 5 NESEL 0 1 Description Sampling at divided by 16 Sampling at divided by 4 Bits 4 to 2Reserved: These bits cannot be modified and are always read as 0. Rev.3.00 Jan. 10, 2007 page 77 of 1038 REJ09B0328-0300 Section 4 Power-Down State Bits 1 and 0Subactive Mode Clock Select 1, 0 (SA1, SA0): These bits select the CPU operating clock in the subactive mode. These bits cannot be modified in the subactive mode. Bit 1 SA1 0 0 1 Bit 0 SA0 0 1 * Description Operating clock of CPU is w/8 Operating clock of CPU is w/4 Operating clock of CPU is w/2 (Initial value) Legend: * Don't care 4.2.3 Timer Register A (TMA) Bit : 7 TMAOV 6 TMAIE 0 R/W 5 -- 1 R/W 4 -- 1 R/W 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W Initial value : R/W : 0 R/(W)* Note: * Only 0 can be written, to clear the flag. The timer register A (TMA) controls timer A interrupts and selects input clock. Only Bit 3 is explained here. For details of other bits, see section 12.2.1, Timer Mode Register A (TMA). TMA is a readable/writable register which is initialized to H'30 by a reset. Rev.3.00 Jan. 10, 2007 page 78 of 1038 REJ09B0328-0300 Section 4 Power-Down State Bit 3Clock Source, Prescaler Select (TMA3): Selects Timer A clock source between PSS and PSW. Also controls transition operation to the power-down mode. The operation mode to which the MCU is transited after SLEEP instruction execution is determined by the combination with other control bits than this bit. For details, see the description of Clock Select 2 to 0 in section 12.2.1, Timer Mode Register A (TMA). Bit 3 TMA3 0 Description * * Timer A counts -based prescaler (PSS) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (Initial value) Timer A counts w-based prescaler (PSW) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode, or subactive mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode 1 * * * 4.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control. MSTPCR is initialized to H'FFFF by a reset. MSTRCRH and MSTPCRL Bits 7 to 0Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 4.4 for the method of selecting on-chip supporting modules. MSTPCRH, MSTPCRL Bits 7 to 0 MSTP 15 to MSTP 0 0 1 Description Module stop mode is cleared Module stop mode is set (Initial value) Rev.3.00 Jan. 10, 2007 page 79 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.3 Medium-Speed Mode When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (16, 32 or 64) specified by the SCK1 and SCK0 bits. The onchip supporting modules other than the CPU always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if 16 is selected as the operating clock, on-chip memory is accessed in 16 states, and internal I/O registers in 32 states. Medium-speed mode is cleared by clearing the both bits SCK1 and SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the TMA3 bit in TMA (Timer A) are both cleared to 0, a transition is made to software standby mode. When standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. Figure 4.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode Internal , supporting module clock CPU clock Internal address bus SBYCR SBYCR Internal write signal Figure 4.2 Medium-Speed Mode Transition and Clearance Timing Rev.3.00 Jan. 10, 2007 page 80 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.4 4.4.1 Sleep Mode Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules (excluding the servo circuit and 12-bit PWM) do not stop. 4.4.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt, or with the RES pin. (1) Clearing with an Interrupt When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI have been masked by the CPU. (2) Clearing with the RES Pin When the RES pin is driven low, the reset state is entered. When the RES pin is driven high after the prescribed reset input period, the CPU begins reset exception handling. Rev.3.00 Jan. 10, 2007 page 81 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.5 4.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 4.4 shows MSTP bits and the on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI1, A/D converter, Timer X1, and Servo circuit, are retained. After reset release, all modules are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Table 4.4 Register MSTPCRH MSTP Bits and Corresponding On-Chip Supporting Modules Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Module Timer A Timer B Timer J Timer L Timer R Timer X1 Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) I C bus interface (IIC) 14-bit PWM 8-bit PWM A/D converter Servo circuit, 12-bit PWM 2 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Rev.3.00 Jan. 10, 2007 page 82 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.6 4.6.1 Standby Mode Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator (except for subclock oscillator) all stop. However, contents of the CPU's internal registers and data in the built-in RAM as well as functions of the SCI1, timer X1 and built-in peripheral circuits (except the servo circuit) are maintained in the current state. The I/O port, at this time, is caused to the high impedance state. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 4.6.2 Clearing Standby Mode Standby mode is cleared by an external interrupt (NMI pin, or pin IRQ0 and IRQ1, or by means of the RES pin. (1) Clearing with an Interrupt When an NMI, IRQ0 and IRQ1 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, standby mode is cleared, and interrupt exception handling is started. Standby mode cannot be cleared with an IRQ0 and IRQ1 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the CPU. (2) Clearing with the RES Pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. (1) Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 10 ms (the oscillation settling time). Table 4.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Rev.3.00 Jan. 10, 2007 page 83 of 1038 REJ09B0328-0300 Section 4 Power-Down State Table 4.5 STS2 0 Oscillation Settling Time Settings STS1 0 STS0 0 1 1 0 1 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states 1 16 states* 10 MHz 0.8 1.6 3.3 6.6 13.1 26.2 1.6 8 MHz 1.0 2.0 4.1 8.2 16.4 32.8 2.0 s Unit ms 1 0 0 1 1 * : Recommended time setting Legend: * Don't care Note: 1. With Flash memory version, do not set the standby time to 16 states. The standby time is 32 states when transited to medium-speed mode /32 (SCK1 = 1, SCK0 = 0). (2) Using an External Clock Any value can be set. Rev.3.00 Jan. 10, 2007 page 84 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.7 4.7.1 Watch Mode Watch Mode If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU and all on-chip supporting modules except Timer A stop. As long as the prescribed voltage is supplied, the contents of some of the CPU's internal registers and on-chip RAM are retained, and I/O ports are placed in the high-impedance state. 4.7.2 Clearing Watch Mode Watch mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin IRQ0 and IRQ1), or by means of the RES pin. (1) Clearing with an Interrupt When an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to medium-speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, and interrupt exception handling is started. Watch mode cannot be cleared with an IRQ0 and IRQ1 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the oscillation settling time setting when making a transition from watch mode to high-speed mode. (2) Clearing with the RES Pin See (2) Clearing with the RES Pin in section 4.6.2, Clearing Standby Mode. Rev.3.00 Jan. 10, 2007 page 85 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.8 4.8.1 Subsleep Mode Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as the prescribed voltage is supplied, the contents of the CPU, some of its on-chip registers and on-chip RAM are retained, and I/O ports retain their states prior to the transition. 4.8.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin IRQ0 to IRQ5), or by means of the RES pin. (1) Clearing with an Interrupt When an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to IRQ5 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. (2) Clearing with the RES Pin See (2) Clearing with the RES Pin in section 4.6.2, Clearing Standby Mode. Rev.3.00 Jan. 10, 2007 page 86 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.9 4.9.1 Subactive Mode Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU performs sequential program execution at low speed on the subclock. In this mode, all on-chip supporting modules other than Timer A stop. 4.9.2 Clearing Subactive Mode Subsleep mode is cleared by a SLEEP instruction, or by means of the RES pin. (1) Clearing with a SLEEP Instruction When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, a transition is made to subsleep mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made directly to high-speed or medium-speed mode. Fort details of direct transition, see section 4.10, Direct Transition. (2) Clearing with the RES Pin See (2) Clearing with the RES Pin in section 4.6.2, Clearing Standby Mode. Rev.3.00 Jan. 10, 2007 page 87 of 1038 REJ09B0328-0300 Section 4 Power-Down State 4.10 4.10.1 Direct Transition Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, medium-speed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program* is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition, direct transition interrupt exception handling is started. (1) Direct Transition from High-Speed Mode to Subactive Mode If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, a transition is made to subactive mode. (2) Direct Transition from Subactive Mode to High-Speed Mode/Medium-Speed Mode If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the TMA3 bit in TMA (Timer A) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to high-speed mode. Note: * At the time of transition from subactive mode to high- or medium-speed mode, an oscillation stabilization wait time is generated. Rev.3.00 Jan. 10, 2007 page 88 of 1038 REJ09B0328-0300 Section 5 Exception Handling Section 5 Exception Handling 5.1 5.1.1 Overview Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR. Table 5.1 Priority High Exception Types and Priority Exception Type Reset 1 Trace* Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception 2 handling ends, if an interrupt request has been issued* Started by a direct transition resulting from execution of a SLEEP instruction Started by execution of a trap instruction (TRAPA) Interrupt Direct transition Trap instruction 3 (TRAPA)* Low Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in this LSI.) Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. Rev.3.00 Jan. 10, 2007 page 89 of 1038 REJ09B0328-0300 Section 5 Exception Handling 5.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: [1] The program counter (PC) and condition-code register (CCR) are pushed onto the stack. [2] The interrupt mask bits are updated. The T bit is cleared to 0. [3] A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps [2] and [3] above are carried out. 5.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 5.1. Different vector addresses are assigned to different exception sources. Table 5.2 lists the exception sources and their vector addresses. * Reset * Trace (cannot be used in this LSI) External interrupts ... NMI, IRQ5 to IRQ0 Exception sources * Interrupts Internal interrupts ... Interrupt sources in on-chip supporting modules * Direct transition * Trap instruction Figure 5.1 Exception Sources Rev.3.00 Jan. 10, 2007 page 90 of 1038 REJ09B0328-0300 Section 5 Exception Handling Table 5.2 Exception Vector Table Vector Number 0 1 2 3 4 5 Vector Address* H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'0064 to H'0067 1 Exception Source Reset Reserved for system use Direct transition External interrupt NMI 6 7 8 9 10 11 Trap instruction (4 sources) Reserved for system use 12 13 14 15 Address trap #0 #1 #2 16 17 18 19 20 21 22 23 24 25 Internal interrupt (IC) Internal interrupt (HSW1) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 26 H'0068 to H'006B Reserved 27 H'006C to H'006F 33 H'0084 to H'0087 *2 Internal interrupt 30 H'0088 to H'008B 67 H'010C to H'010F Notes: 1. Lower 16 bits of the address. 2. For details on internal interrupt vectors, see section 6.3.3, Interrupt Exception Vector Table. Rev.3.00 Jan. 10, 2007 page 91 of 1038 REJ09B0328-0300 Section 5 Exception Handling 5.2 5.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The MCUs can also be reset by overflow of the watchdog timer. For details, see section 18, Watchdog Timer (WDT). 5.2.2 Reset Sequence The MCU enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low during the oscillation stabilizing time of the clock oscillator when powering on. To reset the chip during operation, hold the RES pin low for at least 20 states. For pin states in a reset, see appendix D.1, Pin Circuit Diagrams. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: [1] The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. [2] The reset exception vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 5.2 shows examples of the reset sequence. Rev.3.00 Jan. 10, 2007 page 92 of 1038 REJ09B0328-0300 Section 5 Exception Handling Vector fetch Internal Fetch of first program processing instruction RES Internal address bus (1) (3) Internal read signal Internal write signal High level Internal data bus (2) (4) (1) (2) (3) (4) : Reset exception vector address ((1) = H'0000 or H'000000) : Start address (contents of reset exception vector address) : Start address ((3) = (2)) : First program instruction Figure 5.2 Reset Sequence (Mode 1) 5.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). Rev.3.00 Jan. 10, 2007 page 93 of 1038 REJ09B0328-0300 Section 5 Exception Handling 5.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI and IRQ5 to IRQ0) and internal sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI), 2 A/D converter (ADC), I C bus interface (IIC), servo circuits, synchronized detection, address trap, etc. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to either three priority/mask levels to enable multiplexed interrupt control. For details on interrupts, see section 6, Interrupt Controller. NMI (1) External interrupts IRQ5 to IRQ0 (6) WDT* (1) Interrupts PSU (1) TMR (15) SCI (6) Internal interrupts ADC (1) IIC (1) Servo circuits (9) Synchronized detection (1) Address trap (3) Notes: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 5.3 Interrupt Sources and Number of Interrupts Rev.3.00 Jan. 10, 2007 page 94 of 1038 REJ09B0328-0300 Section 5 Exception Handling 5.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 5.3 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 5.3 Status of CCR and EXR after Trap Instruction Exception Handling CCR I 1 1 UI 1 EXR* I2 to I0 T Interrupt Control Mode 0 1 Legend: 1: Set to 1 0: Cleared to 0 : Retains value prior to execution. *: Does not affect operation in this LSI. Rev.3.00 Jan. 10, 2007 page 95 of 1038 REJ09B0328-0300 Section 5 Exception Handling 5.5 Stack Status after Exception Handling Figure 5.4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 5.4 (1) Stack Status after Exception Handling (Normal Mode)* Note: * Normal mode is not available for this LSI. SP CCR PC (24 bits) Interrupt control modes 0 and 1 Figure 5.4 (2) Stack Status after Exception Handling (Advanced Mode) Rev.3.00 Jan. 10, 2007 page 96 of 1038 REJ09B0328-0300 Section 5 Exception Handling 5.6 Notes on Use of the Stack When accessing word data or longword data, this chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn (or MOV.W Rn, @-SP) ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.WRn (or MOV.W @SP+, Rn) POP.LERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 5.5 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF MOV.B R1L, @-ER7 Contents of CCR lost Data saved above SP Legend: CCR : Condition-code register PC : Program counter R1L : General register R1L SP : Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, is advanced mode. Figure 5.5 Operation when SP Value Is Odd Rev.3.00 Jan. 10, 2007 page 97 of 1038 REJ09B0328-0300 Section 5 Exception Handling Rev.3.00 Jan. 10, 2007 page 98 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Section 6 Interrupt Controller 6.1 6.1.1 Overview Features This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two Interrupt Control Modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities Settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI. * Independent Vector Addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven External Interrupt Pins NMI is the highest-priority interrupt, and is accepted at all times. Falling edge, rising edge, or both edge detection can be selected for the NMI interrupt. Falling edge, rising edge, or both edge detection can be selected for interrupt IRQ0. Falling edge or rising edge can be individually selected for interrupts IRQ5 to IRQ1. Rev.3.00 Jan. 10, 2007 page 99 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 6.1. INTM1, INTM0 SYSCR NMIEG1, NMIEG0 NM input NMI input unit Interrupt request Vector number IRQ input IRQ input unit IRQR IEGR Internal interrupt requests IENR Priority determination I, UI CCR CPU ICR Interrupt controller Legend: IEGR IENR IRQR ICR : IRQ edge select register : IRQ enable register : IRQ status register : Interrupt control register SYSCR : System control register Figure 6.1 Block Diagram of Interrupt Controller Rev.3.00 Jan. 10, 2007 page 100 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the interrupt controller. Table 6.1 Name Interrupt Controller Pins Symbol I/O Input Input Input Function Nonmaskable external interrupt; rising, falling, or both edges can be selected Maskable external interrupts; rising, falling, or both edges can be selected Maskable external interrupts: rising, or falling edges can be selected Nonmaskable interruptNMI External interrupt request External interrupt requests 1 to 5 IRQ0 IRQ1 to IRQ5 6.1.4 Register Configuration Table 6.2 summarizes the registers of the interrupt controller. Table 6.2 Name System control register IRQ edge select register IRQ enable register IRQ status register Interrupt control register A Interrupt control register B Interrupt control register C Interrupt control register D Port mode register 1 Interrupt Controller Registers Abbreviation SYSCR IEGR IENR IRQR ICRA ICRB ICRC ICRD PMR1 R/W R/W R/W R/W R/ (W)* R/W R/W R/W R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 1 Address* H'FFE8 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFCE Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. Rev.3.00 Jan. 10, 2007 page 101 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.2 6.2.1 Register Descriptions System Control Register (SYSCR) Bit : 7 -- 0 -- 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 XRST 0 R 2 NMIEG1 0 R/W 1 NMIEG0 0 R/W 0 -- 0 -- Initial value : R/W : SYSCR is an 8-bit readable register that selects the interrupt control mode and the detected edge for NMI. Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'00 by a reset. Bits 5 and 4--Interrupt Control Mode (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 1 Description Interrupts are controlled by I bit (Initial value) Interrupts are controlled by I and UI bits and ICR Cannot be used in this LSI Cannot be used in this LSI Bits 2 and 1--NMI Pin Detected Edge Select (NMIEG1, NMIEG0): Selects the detected edge for the NMI pin. Bit 2 NIMIEG1 0 Bit 1 NIMIEG0 0 1 1 * Legend: * Don't care Description Interrupt request generated at falling edge of NMI pin Interrupt request generated at rising edge of NMI pin Interrupt request generated at both falling and rising edges of NMI pin (Initial value) Rev.3.00 Jan. 10, 2007 page 102 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) Bit : 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W 3 ICR3 0 R/W 2 ICR2 0 R/W 1 ICR1 0 R/W 0 ICR0 0 R/W Initial value : R/W : The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI. The correspondence between ICR settings and interrupt sources is shown in table 6.3. The ICR registers are initialized to H'00 by a reset. Bits 7 to 0--Interrupt Control Level (ICR7 to ICR0): Sets the control level for the corresponding interrupt source. Bit n ICRn 0 1 Description Corresponding interrupt source is control level 0 (non-priority) Corresponding interrupt source is control level 1 (priority) (Initial value) Note: n = 7 to 0 Table 6.3 ICRA Correspondence between Interrupt Sources and ICR Settings ICRA7 Reserved ICRA6 Input capture ICRB6 Reserved ICRA5 HSW1 ICRB5 Servo (drum, capstan latch) ICRC5 Watchdog timer ICRD5 Reserved ICRA4 IRQ0 ICRB4 Timer A ICRA3 IRQ1 ICRB3 Timer B ICRA2 IRQ2 IRQ3 ICRB2 Timer J ICRA1 IRQ4 IRQ5 ICRB1 Timer R CIRA0 Reserved ICRB0 Timer L ICRB ICRB7 Reserved ICRC ICRC7 Timer X1 ICRC6 Synchronized detection ICRD6 Reserved ICRC4 Servo ICRC3 IIC ICRC2 SCI1 (UART) ICRD2 ICRC1 ICRC0 SCI2 A/D (with 32-bit buffer) ICRD1 Reserved ICRD0 Reserved ICRD ICRD7 HSW2 ICRD4 Reserved ICRD3 Reserved Reserved Rev.3.00 Jan. 10, 2007 page 103 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.2.3 IRQ Enable Register (IENR) Bit : 7 -- 0 -- 6 -- 0 -- 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value : R/W : IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IENR is initialized to H'00 by a reset. Bits 7 and 6--Reserved: Do not write 1 to them. Bits 5 to 0--IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits select whether IRQ5 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupt disabled IRQn interrupt enabled (Initial value) Note: n = 5 to 0 6.2.4 IRQ Edge Select Registers (IEGR) Bit : 7 -- 6 IRQ5EG 0 R/W 5 IRQ4EG 0 R/W 4 IRQ3EG 0 R/W 3 IRQ2EG 0 R/W 2 1 0 IRQ1EG IRQ0EG1 IRQ0EG0 0 R/W 0 R/W 0 R/W Initial value : R/W : 0 -- IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins IRQ5 to IRQ0. IEGR register is initialized to H'00 by a reset. Bit 7--Reserved: Do not write 1 to it. Rev.3.00 Jan. 10, 2007 page 104 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Bits 6 to 2--IRQ5 to IRQ1 Pins Detected Edge Select (IRQ5EG to IRQ1EG): These bits select detected edge for interrupts IRQ5 to IRQ1. Bits 6 to 2 IRQnEG 0 1 Description Interrupt request generated at falling edge of IRQn pin input Interrupt request generated at rising edge of IRQn pin input (Initial value) Note: n = 5 to 1 Bits 1 and 0--IRQ0 Pin Detected Edge Select (IRQ0EG1, IRQ0EG0): These bits select detected edge for interrupt IRQ0. Bit 1 IRQ0EG1 0 0 1 Bit 0 IRQ0EG0 0 1 * Description Interrupt request generated at falling edge of IRQ0 pin input (Initial value) Interrupt request generated at rising edge of IRQ0 pin input Interrupt request generated at both falling and rising edges of IRQ0 pin input Legend: * Don't care 6.2.5 IRQ Status Register (IRQR) Bit : 7 -- 0 -- 6 -- 0 -- 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value : R/W : Note: * Only 0 can be written, to clear the flag. IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests. IRQR is initialized to H'00 by a reset. Bits 7 and 6--Reserved: Do not write 1 to them. Rev.3.00 Jan. 10, 2007 page 105 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Bits 5 to 0--IRQ5 to IRQ0 Flags: These bits indicate the status of IRQ5 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing condition] Cleared by reading IRQnF set to 1, then writing 0 in IRQnF When IRQn interrupt exception handling is executed 1 [Setting conditions] (1) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnEG = 0) (2) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnEG = 0) (3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is set (IRQ0EG1 = 1) Note: n = 5 to 0 (Initial value) 6.2.6 Port Mode Register (PMR1) Bit : 7 PMR17 0 R/W 6 PMR16 0 R/W 5 PMR15 0 R/W 4 PMR14 0 R/W 3 PMR13 0 R/W 2 PMR12 0 R/W 1 PMR11 0 R/W 0 PMR10 0 R/W Initial value : R/W : Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is specified for each bit. PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Only bits 5 to 0 are explained here. For details, see section 11, I/O Port. Bits 5 to 0--P15/IRQ5 to P10/IRQ0 Pin Switching (PMR15 to PMR10): These bits are for setting the P1n/IRQn pin as the input/output pin for P1n or as the IRQn pin for external interrupt request input. Bit n PMR1n 0 1 Description P1n/IRQn pin functions as the P1n input/output pin P1n/IRQn pin functions as the IRQn input pin (Initial value) Note: n = 5 to 0 Rev.3.00 Jan. 10, 2007 page 106 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller The following is the notes on switching the pin function by PMR1. (1) When the port is set as the IC input pin or IRQ5 to IRQ0 input pin, the pin level must be High or Low regardless of active mode or power-down mode. Do not set the pin level at Medium. (2) Switching the pin function of P16/IC or P15/IRQ5 to P10/IRQ0 may be mistakenly identified as edge detection and detection signal may be generated. To prevent this, operate as follows: (a) Set the interrupt enable/disable flag to disable before switching the pin function. (b) Clear the applicable interrupt request flag to 0 after switching the pin function and executing another instruction. (Program example) : MOV.B R0L,@IENR Interrupt disabled MOV.B R1L,@PMR1 Pin function change NOP BCLR m @IRQR Optional instruction Applicable interrupt clear MOV.B R1L,@IENR Interrupt enabled : Rev.3.00 Jan. 10, 2007 page 107 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts. 6.3.1 External Interrupts There are seven external interrupt sources; NMI and IRQ5 to IRQ0. Of these, NMI, and IRQ1 to IRQ0 can be used to restore this chip from standby mode. (1) NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The NMIEG1 and NMIEG0 bits in SYSCR can be used to select whether an interrupt is requested at a rising, falling edge or both edges on the NMI pin. The vector number for NMI interrupt exception handling is 7. (2) IRQ5 to IRQ0 Interrupts Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5 to IRQ0. Interrupts IRQ5 to IRQ0 have the following features: (a) Using IEGR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pin IRQ0. (b) Using IEGR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ5 to IRQ0. (c) Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IENR. (d) The interrupt control level can be set with ICR. (e) The status of interrupt requests IRQ5 to IRQ0 is indicated in IRQR. IRQR flags can be cleared to 0 by software. A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 6.2. Rev.3.00 Jan. 10, 2007 page 108 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller IRQnE IRQnEG Edge detection circuit IRQn input IRQnF S Q R IRQn interrupt request Clear signal Note: n = 5 to 0 Figure 6.2 Block Diagram of Interrupts IRQ5 to IRQ0 Figure 6.3 shows the timing of IRQnF setting. Internal IRQn input pin IRQnF Figure 6.3 Timing of IRQnF Setting The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 26. Upon detection of IRQ5 to IRQ0 interrupts, the applicable pin is set in the port mode register 1 (PMR1) as IRQn pin. Rev.3.00 Jan. 10, 2007 page 109 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.3.2 Internal Interrupts There are 38 sources for internal interrupts from on-chip supporting modules. (1) For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. (2) The interrupt control level can be set by means of ICR. 6.3.3 Interrupt Exception Vector Table Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 6.4. Table 6.4 Priority High Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source Reset Reserved Origin of Interrupt Source External pin Direct transition NMI Trap instruction TRAPA#0 TRAPA#1 TRAPA#2 TRAPA#3 Reserved Instruction External pin Instruction Vector No. Vector Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F ICR Remarks Low 15 Rev.3.00 Jan. 10, 2007 page 110 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Origin of Interrupt Source #0 #1 #2 IC HSW1 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved PSU Servo circuit External pin ATC Vector No. Vector Address 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Drum latch 1 (speed) Capstan latch 1 (speed) TMAI TMBI TMJ1I TMJ2I TMR1I TMR2I TMR3I Low TMLI Timer L Timer R Timer A Timer B Timer J Servo circuit 34 35 36 37 38 39 40 41 42 43 H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 H'0074 to H'0077 H'0078 to H'007B H'007C to H'007F H'0080 to H'0083 H'0084 to H'0087 H'0088 to H'008B H'008C to H'008F H'0090 to H'0093 H'0094 to H'0097 H'0098 to H'009B H'009C to H'009F H'00A0 to H'00A3 H'00A4 to H'00A7 H'00A8 to H'00AB H'00AC to H'00AF ICRB0 ICRB1 ICRB4 ICRB3 ICRB2 ICRB5 ICRA1 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 Priority Interrupt Source High Address trap ICR Remarks Rev.3.00 Jan. 10, 2007 page 111 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Origin of Interrupt Source Timer X1 Vector No. Vector Address 44 45 46 47 48 49 50 Sync signal detection Watchdog timer Servo circuit 51 52 53 54 55 56 57 58 IIC ERI RXI TXI TEI SCI2 TEI ABTI A/D conversion end Low HSW2 A/D Servo circuit SCI2 SCI1 (UART) 59 60 61 62 63 64 65 66 67 H'00B0 to H'00B3 H'00B4 to H'00B7 H'00B8 to H'00BB H'00BC to H'00BF H'00C0 to H'00C3 H'00C4 to H'00C7 H'00C8 to H'00CB H'00CC to H'00CF ICRC6 H'00D0 to H'00D3 H'00D4 to H'00D7 ICRC5 H'00D8 to H'00DB ICRC4 H'00DC to H'00DF H'00E0 to H'00E3 H'00E4 to H'00D7 H'00E8 to H'00EB H'00EC to H'00EF ICRC3 H'00F0 to H'00F3 H'00F4 to H'00F7 H'00F8 to H'00FB H'00FC to H'00FF H'0100 to H'0103 H'0104 to H'0107 H'0108 to H'010B H'010C to H'010F ICRC0 ICRD7 ICRC1 ICRC2 Priority Interrupt Source High ICXA ICXB ICXC ICXD OCX1 OCX2 OVFX VD interrupts Reserved 8-bit interval timer CTL Drum latch 2 (speed) Capstan latch 2 (speed) Drum latch 3 (phase) Capstan latch 3 (phase) IIC SCI1 ICR ICRC7 Remarks Rev.3.00 Jan. 10, 2007 page 112 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.4 6.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI interrupts and address trap interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 6.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated by the I and UI bits in the CPU's CCR. Table 6.5 Interrupt Control Mode 0 Interrupt Control Modes SYSCR INTM1 0 INTM0 0 Priority Setting Register ICR Interrupt Mask Bits I Description Interrupt mask control is performed by the I bit Priority can be set with ICR 3-level interrupt mask control is performed by the I and UI bits Priority can be set with ICR 1 1 ICR I, UI Figure 6.4 shows a block diagram of the priority decision circuit. Rev.3.00 Jan. 10, 2007 page 113 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller ICR I UI Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 6.4 Block Diagram of Interrupt Priority Determination Operation (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 6.6 shows the interrupts selected in each interrupt control mode. Table 6.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bit I 0 1 1 0 1 Legend: * Don't care UI * * * 0 1 Selected Interrupts All interrupts (control level 1 has priority) NMI and address trap interrupts All interrupts (control level 1 has priority) NMI, address trap and control level 1 interrupts NMI and address trap interrupts Interrupt Control Mode 0 (2) Default Priority Determination The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 6.7 shows operations and control signal functions in each interrupt control mode. Rev.3.00 Jan. 10, 2007 page 114 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Table 6.7 Operations and Control Signal Functions in Each Interrupt Control Mode Setting INTM1 0 INTM0 0 1 Interrupt Acceptance Control, 3-Level Control I IM IM UI IM ICR PR PR Interrupt Control Mode 0 1 Default Priority Determination Legend: : Interrupt operation control performed IM: Used as interrupt mask bit PR: Sets priority : Not used 6.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case. (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 6.4 is selected. (3) The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI or an address trap interrupt is accepted, and other interrupt requests are held pending. (4) When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. (5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. (6) Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address trap. (7) A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.3.00 Jan. 10, 2007 page 115 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI No Yes Address trap interrupt? No Control level 1 interrupt? No Hold pending Yes IC Yes HSW1 Yes No No IC Yes HSW1 Yes No No HSW2 Yes HSW2 Yes I=0 Yes Save PC and CCR I1 No Read vector address Branch to interrupt handling routine Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.3.00 Jan. 10, 2007 page 116 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU's CCR, and ICR. (1) Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. (2) Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'04, H'00, H'00 and H'00 are set in ICRA, ICRB, ICRC, and ICRD respectively, (i.e. IRQ2 interrupt is set to control level 1 and other interrupts to control level 0), the situation is as follows: (1) When I = 0, all interrupts are enabled (Priority order: NMI > IRQ2 > IC > HSW1 > ...) (2) When I = 1 and UI = 0, only NMI, address trap and IRQ2 interrupts are enabled (3) When I = 1 and UI = 1, only NMI and address trap interrupts are enabled Figure 6.6 shows the state transitions in these cases. I0 All interrupts enabled I 1, UI 0 I0 Exception handling execution or I 1, UI 1 Only NMI, address trap and IRQ2 interrupts enabled UI 0 Exception handling execution or UI 1 Only NMI and address trap interrupts enabled Figure 6.6 Example of State Transitions in Interrupt Control Mode 1 Figure 6.7 shows an operation flowchart of interrupt reception. Rev.3.00 Jan. 10, 2007 page 117 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 6.4 is selected. (3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect. An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If the I bit is set to 1, only NMI and address trap interrupts are accepted, and other interrupt requests are held pending. An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and the UI bit is cleared to 0. When both the I bit and the UI bit are set to 1, only NMI and address trap interrupts are accepted, and other interrupt requests are held pending. (4) When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. (5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. (6) Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI and address trap. (7) A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.3.00 Jan. 10, 2007 page 118 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI No Yes Address trap interrupt? No Control level 1 interrupt? No Hold pending Yes IC Yes HSW1 Yes No No IC Yes HSW1 Yes No No HSW2 Yes HSW2 Yes I=0 No No I=0 Yes UI = 0 No Yes Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 6.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev.3.00 Jan. 10, 2007 page 119 of 1038 REJ09B0328-0300 6.4.4 Interrupt acceptance Interrupt handling routine instruction prefetch Interrupt level determination Wait for end of instruction Instruction prefetch Internal operation Stack Vector fetch Internal operation Section 6 Interrupt Controller Interrupt request signal Rev.3.00 Jan. 10, 2007 page 120 of 1038 REJ09B0328-0300 (1) (3) (5) (7) (9) (11) (13) Internal address bus Interrupt Exception Handling Sequence Internal read signal Internal write signal Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control 0 is set in advanced mode, and the program area and stack area are in onchip memory. Figure 6.8 Interrupt Exception Handling (2) (4) (6) (8) (10) (12) (14) (6)(8) (9)(11) (10)(12) (13) (14) First instruction of interrupt handling routine Internal data bus (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2)(4) Instruction code (Not executed.) Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) Interrupt handling routine start address ((13) = (10)(12)) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 Section 6 Interrupt Controller 6.4.5 Interrupt Response Times Table 6.8 shows interrupt response times-the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 6.8 are explained in table 6.9. Table 6.8 No. 1 2 3 4 5 6 Interrupt Response Times Advanced Mode 3 1 to 19 + 2 SI 2 Sk 2 SI 3 4 Number of States 1 Interrupt priority determination* 2 Number of wait states until executing instruction ends* PC, CCR stack save Vector fetch Instruction fetch* Internal processing* 2 SI 2 12 to 32 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 6.9 Number of States in Interrupt Handling Routine Execution Object of Access Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK Internal Memory 1 Rev.3.00 Jan. 10, 2007 page 121 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller 6.5 6.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0. TIER write cycle by CPU OCIA interrupt exception handling Internal address bus TIER address Internal write signal OCIAE OCFA OCIA interrupt signal Figure 6.9 Contention between Interrupt Generation and Disabling Rev.3.00 Jan. 10, 2007 page 122 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 6.5.2 Instructions That Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts except NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 6.5.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 6.5.4 When NMI Is Disabled When NMI is disabled, the input level to the NMI pin must be fixed high or low. It is recommended that the NMI interrupt exception handling address be set to the NMI vector address (H'00001C to H'00001F) and that the RTE instruction also be set to the NMI exception handling address. Rev.3.00 Jan. 10, 2007 page 123 of 1038 REJ09B0328-0300 Section 6 Interrupt Controller .ORG .DATA.L . . . . NMI:RTE H'00001C NMI Rev.3.00 Jan. 10, 2007 page 124 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Section 7 ROM (H8S/2194 Group) 7.1 Overview The H8S/2194 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2193 has 112 kbytes, the H8S/2192 has 96 kbytes, and the H8S/2191 has 80 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. The flash memory versions of the H8S/2194 can be erased and programmed on-board as well as with a general-purpose PROM programmer. 7.1.1 Block Diagram Figure 7.1 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'01FFFE H'01FFFF Figure 7.1 ROM Block Diagram (H8S/2194) Rev.3.00 Jan. 10, 2007 page 125 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.2 7.2.1 Overview of Flash Memory Features The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing all blocks, the individual blocks must be erased sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-kbyte, and 32kbyte blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and MCU's bit rates. * Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Rev.3.00 Jan. 10, 2007 page 126 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.2.2 Block Diagram Internal address bus Internal data bus (16 bits) STCR FLMCR1 * FLMCR2 * EBR1 EBR2 * * Bus interface/controller Operating mode FWE pin Mode pin Module bus Flash memory (128 kbytes) Legend: : Serial/timer control register STCR FLMCR1 : Flash memory control register 1 FLMCR2 : Flash memory control register 2 : Erase block register 1 EBR1 : Erase block register 2 EBR2 Note: * These registers are exclusively used for the flash memory. If you try to read these addresses with the mask ROM version, values read becomes uncertain. Data write is also disabled with the above version. Figure 7.2 Block Diagram of Flash Memory Rev.3.00 Jan. 10, 2007 page 127 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.2.3 Flash Memory Operating Modes (1) Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. =0 M User mode 1, D0 = FWE Reset state FWE = 1, MD0 = 0, P12 = P13 = P14 = 1 RES =0 RES = 0 * FWE = 1 SWE = 1 RES = 0 FWE = 0 or SWE = 0 User program mode RE S = 0 Programmer mode Boot mode On-board program mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, P12 = P13 = 1, P14 = 0 Figure 7.3 Flash Memory Mode Transitions Rev.3.00 Jan. 10, 2007 page 128 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (2) On-Board Programming Modes (a) Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the LSI (originally incorporated in the chip) is started and the programing control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program This LSI Boot program Flash memory RAM SCI This LSI Boot program Flash memory New application program SCI RAM Boot program area Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program This LSI Boot program Flash memory RAM Boot program area Flash memory preprograming erase Programming control program New application program SCI This LSI Boot program Flash memory RAM Boot program area Programming control program SCI Program execution state Figure 7.4 Boot Mode Rev.3.00 Jan. 10, 2007 page 129 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (b) User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/erase control program from the flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. 3. Flash memory initialization The programming/erase control program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. New application program Program execution state Figure 7.5 User Program Mode (Example) Rev.3.00 Jan. 10, 2007 page 130 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (3) Differences between Boot Mode and User Program Mode Table 7.1 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Note: * Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify Program/program-verify To be provided by the user, in accordance with the recommended algorithm. (4) Block Configuration The flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 16 kbytes 128 kbytes 8 kbytes 8 kbytes 32 kbytes 32 kbytes Address H'1FFFF 128-kbyte version Figure 7.6 Flash Memory Block Configuration Rev.3.00 Jan. 10, 2007 page 131 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 7.2. Table 7.2 Pin Name Reset Flash write enable Mode 0 Port 12 Port 13 Port 14 Transmit data Receive data Flash Memory Pins Abbreviation RES FWE MD0 P12 P13 P14 SO1 SI1 I/O Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI operating mode Sets this LSI operating mode when MD0 = 0 Sets this LSI operating mode when MD0 = 0 Sets this LSI operating mode when MD0 = 0 Serial transmit data output Serial receive data input 7.2.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 7.3. In order to access these registers, the FLSHE bit in STCR must be set to 1. Table 7.3 Flash Memory Registers Abbreviation FLMCR1* 4 FLMCR2* 4 4 EBR1* 4 EBR2* Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Serial/timer control register R/W R/W* 1 R/W* 1 1 R/W* 1 R/W* Initial Value H'00* 3 H'00* 2 3 H'00* 3 H'00* Address* H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFEE 5 STCR R/W H'00 Notes: 1. When the FWE bit in FLMCR1 is not set at 1, writes are disabled. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 4. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 5. Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 132 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.3 7.3.1 Flash Memory Register Descriptions Flash Memory Control Register 1 (FLMCR1) Bit : 7 FWE --* R 6 SWE 0 R/W 5 -- 0 -- 4 -- 0 -- 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Initial value : R/W : Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), or when a low level is input to the FWE pin. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to the EV and PV bits only when FEW = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7Flash Write Enable (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Rev.3.00 Jan. 10, 2007 page 133 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Bit 6Software Write Enable (SWE): Enables or disables flash memory programming. SWE should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be cleared at the same time as these bits. Bit 6 SWE 0 1 Description Writes are disabled Writes are enabled [Setting condition] Setting is available when FWE = 1 is selected (Initial value) Bits 5 and 4Reserved: These bits cannot be modified and are always read as 0. Bit 3Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected (Initial value) Bit 2Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected (Initial value) Rev.3.00 Jan. 10, 2007 page 134 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Bit 1Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and ESU = 1 are selected (Initial value) Bit 0Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and PSU = 1 are selected (Initial value) Rev.3.00 Jan. 10, 2007 page 135 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.3.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 FLER 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 ESU 0 R/W 0 PSU 0 R/W Initial value : R/W : FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset. The ESU and PSU bits are cleared to 0 in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), hardware protect mode, or software protect mode. Bit 7Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 7.6.3, Error Protection (Initial value) Bits 6 to 2Reserved: These bits cannot be modified and are always read as 0. Rev.3.00 Jan. 10, 2007 page 136 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Bit 1Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 1 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1, and SWE = 1 (Initial value) Bit 0Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 0 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1, and SWE = 1 (Initial value) Rev.3.00 Jan. 10, 2007 page 137 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.3.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit : EBR1 : 7 -- 0 -- 7 EB7 0 R/W 6 -- 0 -- 6 EB6 0 R/W 5 -- 0 -- 5 EB5 0 R/W 4 -- 0 -- 4 EB4 0 R/W 3 -- 0 -- 3 EB3 0 R/W 2 -- 0 -- 2 EB2 0 R/W 1 EB9 0 R/W 1 EB1 0 R/W 0 EB8 0 R/W 0 EB0 0 R/W Initial value : R/W : Bit : EBR2 : Initial value : R/W : EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and 0 in EBR1 (128-kbyte versions only) and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). The flash memory block configuration is shown in table 7.4. Table 7.4 Block (Size) 128-kbyte Versions EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF Flash Memory Erase Blocks Rev.3.00 Jan. 10, 2007 page 138 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.3.4 Bit Serial/Timer Control Register (STCR) : : : 7 -- 0 -- 6 IICX 0 R/W 5 IICRST 0 R/W 4 -- 0 -- 3 FLSHE 0 R/W 2 -- 0 -- 2 1 -- 0 -- 0 -- 0 -- Initial value R/W STCR is an 8-bit readable/writable register that controls register access, the I C bus interface 2 operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the I C bus interface serial clock frequency. For details on functions not related to on-chip flash memory, see section 25.2.7, Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset. Bits 6 and 5I C Control (IICX, IICRST): These bits control the operation of the I C bus 2 interface. For details, see section 25, I C Bus Interface (IIC). Bit 3Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE 0 1 Description Flash memory control registers deselected Flash memory control registers selected (Initial value) 2 2 Bits 7, 4, and 2 to 0Reserved Rev.3.00 Jan. 10, 2007 page 139 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 7.5. For a diagram of the transitions to the various flash memory modes, see figure 7.3. Table 7.5 Mode Mode Name Boot mode User program mode Setting On-Board Programming Modes Pin FWE 1 1* 1 MD0 0 1 P12 1* 2 P13 1* 2 P14 1* 2 Notes: 1. In user program mode, the FWE pin should not be constantly set to 1. Set FWE to 1 to make a transition to user program mode before performing a program/erase/verify operation. 2. Can be used as I/O ports after boot mode is initiated. Rev.3.00 Jan. 10, 2007 page 140 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the MCU's pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI1. In the MCU, the programming control program received via the SCI1 is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 7.7, and the boot program mode execution procedure in figure 7.8. This LSI Flash memory Host Write data reception Verify data transmission SI1 SCI1 SO1 On-chip RAM Figure 7.7 System Configuration in Boot Mode Rev.3.00 Jan. 10, 2007 page 141 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00) and transmits one H'55 data byte Upon receiving H'55, this LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte This LSI transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units This LSI transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, this LSI transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM Note : If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. n+1n n = N? Figure 7.8 Boot Mode Execution Procedure Rev.3.00 Jan. 10, 2007 page 142 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (1) Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 7.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the MCU's system clock frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation, the host's transfer bit rate should be set to (4800 or 9600) bps. Table 7.6 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU's bit rate is possible. The boot program should be executed within this system clock range. Table 7.6 System Clock Frequencies for Which Automatic Adjustment of This LSI Bit Rate Is Possible System Clock Frequency for Which Automatic Adjustment of This LSI Bit Rate Is Possible 8 MHz to 10 MHz 4 MHz to 10 MHz Host Bit Rate 9600 bps 4800 bps Rev.3.00 Jan. 10, 2007 page 143 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (2) On-Chip RAM Area Divisions in Boot Mode In boot mode, the 2048-byte area from H'FFEFB0 to H'FFF7AF is reserved for use by the boot program, as shown in figure 7.10. The area to which the programming control program is transferred is H'FFF7B0 to H'FFFF2F (1920 bytes). The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFEFB0 Boot program area* (2048 bytes) H'FFF7B0 Programming control program area (1920 bytes) H'FFFF30 H'FFFFAF Reserved area (128 bytes) Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program reamins stored in this area after a branch is made to the programming control program. Figure 7.10 RAM Areas in Boot Mode (3) Notes on Use of Boot Mode: (a) When reset is released in boot mode, it measures the low period of the input at the SCI1's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input. (b) In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. (c) Interrupts cannot be used while the flash memory is being programmed or erased. (d) The SI1 and SO1 pins should be pulled up on the board. Rev.3.00 Jan. 10, 2007 page 144 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (e) Before branching to the programming control program (RAM area H'FFF3B0), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. (f) Boot mode can be entered by making the pin settings shown in table 7.5 and executing a reset-start. 1 When the chip detects the boot mode setting at reset release* , it retains that state internally. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then 1 setting the FWE pin and mode pins, and executing reset release* . Boot mode can also be cleared by a WDT overflow reset. If the mode pin input levels are changed in boot mode, the boot mode state will be maintained in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin must not be driven low while the boot program is running or flash 2 memory is being programmed or erased* . Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For further information on FWE application and disconnection, see section 7.9, Flash Memory Programming and Erasing Precautions. Rev.3.00 Jan. 10, 2007 page 145 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. In this mode, the chip starts up in mode 1 and applies a high level to the FWE pin. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 7.11 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD0 = 1 Reset start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 7.9, Flash Memory Programming and Erasing Precautions. Figure 7.11 User Program Mode Execution Procedure Rev.3.00 Jan. 10, 2007 page 146 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.5 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 7.5.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 7.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. Table 29.12 lists wait time (x, y, z, , , , , and ) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum write count (N). Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set more than (y + z + + ) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. Rev.3.00 Jan. 10, 2007 page 147 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least () s later). The watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 7.12) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least () s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Rev.3.00 Jan. 10, 2007 page 148 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) START Set SWE bit in FLMCR1 Wait (x) s Programming must be excuted in the erased state. Do not perform additional programming on addresses that have already been programmed. *5 *4 Store 32-byte program data in program data area and reprogram data area n=1 m=0 Write 32-byte data in RAM reprogram data area consecutively to flash memory Enable WDT Set PSU bit in FLMCR2 Wait (y) s Set P bit in FLMCR1 Wait (z) s Clear P bit in FLMCR1 Wait () s Clear PSU bit in FLMCR2 Wait () s Disable WDT Set PV bit in FLMCR1 Wait () s H'FF dummy write to verify address Wait () s Read verify data Increment address Program data = verify data? YES Reprogram data computation NO *1 *5 Start of programming *5 End of programming *5 n n +1 *5 *5 *5 *2 m=1 *3 *4 Transfer reprogram data to reprogram data area End of 32-byte data verification? YES Clear PV bit in FLMCR1 Wait () s m = 0? YES Clear SWE bit in FLMCR1 End of programming NO RAM Program data storage area (32 bytes) *5 NO *5 n N? Reprogram data storage area (32 bytes) NO YES Clear SWE bit in FLMCR1 Programming failure Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even in case of the bit which is already-programmed in the 32-byte programming loop, perform additional programming if the bit fails at the next verify. 4. An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten as programming progresses. 5. The values of x, y, z, , , , , , and N are listed in section 29.2.7, Flash Memory Characteristics. Program data 0 0 1 1 Verify data 0 1 0 1 Reprogram data 1 0 1 1 Comments Do not reprogram bits for which programming has been completed. Programming incomplete; reprogramming should be performed. -- Still in erased state; no action Figure 7.12 Program/Program-Verify Flowchart Rev.3.00 Jan. 10, 2007 page 149 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 7.13. Table 29.12 lists wait time (x, y, z, , , , , and ) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum clearing count (N). To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set more than (y + z + + ) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 7.5.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least () s later), the watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. Rev.3.00 Jan. 10, 2007 page 150 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) START *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR2 Wait (y) s Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait () s Clear ESU bit in FLMCR2 Wait () s Disable WDT Set EV bit in FLMCR1 Wait () s Set block start address to verify address H'FF dummy write to verify address Wait () s Read verify data Increment address Verify data = all 1? YES NO Last address of block? YES Clear EV bit in FLMCR1 Wait () s *2 *2 *2 *2 *2 *4 *2 Start of erase *2 Halt erase *2 nn+1 *3 NO Clear EV bit in FLMCR1 Wait () s *2 *2 NO *5 End of erasing of all erase blocks? YES Clear SWE bit in FLMCR1 End of erasing n N? YES Clear SWE bit in FLMCR1 Erase failure NO Notes: 1. 2. 3. 4. 5. Preprogramming (setting erase block data to all 0) is not necessary. The values of x, y, z, , , , , , and N are listed in section 29.2.7, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. Set only one bit in EBR1 or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 7.13 Erase/Erase-Verify Flowchart (Single-Block Erase) Rev.3.00 Jan. 10, 2007 page 151 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 7.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). In error protection mode, FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained. (See table 7.7.) Table 7.7 Hardware Protection Functions Item FWE pin protection Reset/standby protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered Program Erase Yes Yes * Yes In a reset (including a WDT overflow reset) and in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), FLMCR1, FLMCR2 (excluding the FLER bit), EBR1, and EBR2 are initialized, and the program/erase-protected state is entered In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC characteristics section Yes * Rev.3.00 Jan. 10, 2007 page 152 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.6.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 7.8.) Table 7.8 Software Protection Functions Item SWE bit protection Block specification protection Description * Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory) Program Erase Yes Yes * * Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2) Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state Yes 7.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: (1) When flash memory is read during programming/erasing (including a vector read or instruction fetch) (2) Immediately after exception handling (excluding a reset) during programming/erasing (3) When a SLEEP instruction is executed during programming/erasing Error protection is released only by a reset and in hardware standby mode. Rev.3.00 Jan. 10, 2007 page 153 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Figure 7.14 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 E SL rror EE occ P u ex ins rren ec tru ce uti ct on ion Reset (hardware protection) RD VF PR ER FLER = 0 S =0 RE Error occurrence RES = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Power-down state* Power-down state* release Error protection mode (Power-down state)* RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF : Verify-read possible PR : Programming possible ER : Erasing possible RD: Memory read not possible VF : Verify-read not possible PR : Programming not possible ER : Erasing not possible Note: * Watch mode, standby mode, and subactive mode Figure 7.14 Flash Memory State Transitions Rev.3.00 Jan. 10, 2007 page 154 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.7 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased 1 (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation. There are three reasons for this: (1) Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. (2) In the interrupt exception handling sequence during programming or erasing, the vector would 2 not be read correctly* , possibly resulting in MCU runaway. (3) If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI input, must therefore be disabled inside and outside the MCU during FWE application. Interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by the write control program is complete. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the interrupt vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev.3.00 Jan. 10, 2007 page 155 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.8 7.8.1 Flash Memory Programmer Mode Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device type with 128-kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with these device types. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. 7.8.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer. The socket adapter product codes are listed in table 7.9. Figure 7.15 shows the memory map in programmer mode. Table 7.9 Part No. HD64F2194 Socket Adapter Product Codes Package 112-pin QFP Socket Adapter Product Code ME2194ESHF1H MCU mode H'000000 This LSI Programmmer mode H'00000 On-chip ROM area (128 kbytes) H'01FFFF H'1FFFF Figure 7.15 Memory Map in Programmer Mode Rev.3.00 Jan. 10, 2007 page 156 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.8.3 Programmer Mode Operation Table 7.10 shows how the different operating modes are set when using programmer mode, and table 7.11 lists the commands used in programmer mode. Details of each mode are given below. (1) Memory Read Mode Memory read mode supports byte reads. (2) Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. (3) Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. (4) Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO6 signal. In status read mode, error information is output if an error occurs. Table 7.10 Settings for Each Operating Mode in Programmer Mode Pin Names Mode Read Output disable Command write 1 Chip disable* FWE H or L H or L H or L* H or L 3 CE L L L L OE L H H X WE H H L X FO0 to FO7 Data output Hi-Z Data input Hi-Z FA0 to FA17 Ain X Ain* X 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin. Rev.3.00 Jan. 10, 2007 page 157 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Table 7.11 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode write write write write Address X X X X Data H'00 H'40 H'20 H'71 2nd Cycle Mode read write write write Address Data RA WA X X Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 7.8.4 Memory Read Mode (1) After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. (2) Command writes can be performed in memory read mode, just as in the command wait state. (3) Once memory read mode has been entered, consecutive reads can be performed. (4) After power-on, memory read mode is entered. Table 7.12 AC Characteristics in Memory Read Mode (1) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 Max 30 30 Unit s ns ns ns ns ns ns ns Rev.3.00 Jan. 10, 2007 page 158 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Command write ADDRESS Memory read mode ADDRESS STABLE CE OE WE DATA twep tceh tnxtc tces tf tr H'00 tdh tds DATA Note: Data is latched on the rising edge of WE. Figure 7.16 Memory Read Mode Timing Waveforms after Command Write Table 7.13 AC Characteristics when Entering Another Mode from Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 Max 30 30 Unit s ns ns ns ns ns ns ns Rev.3.00 Jan. 10, 2007 page 159 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) XX mode command write ADDRESS ADDRESS STABLE CE OE WE DATA DATA tnxtc tces tf twep tceh tr H'XX tdh Note: Do not enable WE and OE at the same time. tds Figure 7.17 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 7.14 AC Characteristics in Memory Read Mode (2) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min 5 Max 20 150 150 100 Unit s ns ns ns ns ADDRESS ADDRESS STABLE ADDRESS STABLE CE OE WE tacc DATA DATA toh DATA toh tacc VIL VIL VIH Figure 7.18 Timing Waveforms for CE/OE Enable State Read Rev.3.00 Jan. 10, 2007 page 160 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) ADDRESS ADDRESS STABLE ADDRESS STABLE tacc CE OE WE DATA tce toe tdf DATA toh tce toe VIH tdf DATA toh tacc Figure 7.19 Timing Waveforms for CE/OE Clocked Read 7.8.5 Auto-Program Mode (a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. (b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. (c) The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. (d) Memory address transfer is performed in the second cycle (figure 7.20). Do not perform transfer after the second cycle. (e) Do not perform a command write during a programming operation. (f) Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. (g) Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-program operation end identification pin). (h) The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. Rev.3.00 Jan. 10, 2007 page 161 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Table 7.15 AC Characteristics in Auto-Program (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf tpns tpnh Min 20 0 0 50 50 70 1 0 60 1 100 100 Max 150 3000 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns FWE ADDRESS CE OE WE FO7 tpns ADDRESS STABLE tceh tnxtc twep tces tf tds tdh tr tas tah tpnh tnxtc Data transfer 1 byte to 128 bytes twsts tspa twrite(1 to 3,000 ms) Programming operation end identification signal FO6 Programming normal end identification signal Programming wait DATA H'40 DATA DATA FO0 to 5 = 0 Figure 7.20 Auto-Program Mode Timing Waveforms Rev.3.00 Jan. 10, 2007 page 162 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.8.6 Auto-Erase Mode (a) Auto-erase mode supports only entire memory erasing. (b) Do not perform a command write during auto-erasing. (c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin). (d) The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. Table 7.16 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf tens tenh Min 20 0 0 50 50 70 1 100 100 100 Max 150 40000 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Rev.3.00 Jan. 10, 2007 page 163 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) FWE tens ADDRESS tenh CE OE WE FO7 FO6 tces tceh tspa tnxtc twep tests terase (100 to 40000 ms) Erase end identification signal Erase normal end identification signal CLin DLin H'20 FO0 to 5 = 0 tnxtc tf tds tr tdh FO5 to FO0 H'20 Figure 7.21 Auto-Erase Mode Timing Waveforms 7.8.7 Status Read Mode (1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. (2) The return code is retained until a command write for other than status read mode is performed. Rev.3.00 Jan. 10, 2007 page 164 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Table 7.17 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 Max 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns ADDRESS CE tce OE WE tces tf tds twep tceh tr tdh DATA H'71 tnxtc tces tf tds H'71 twep tceh tr tdh DATA tnxtc toe tdf tnxtc Note: FO2 and FO3 are undefined. Figure 7.22 Status Read Mode Timing Waveforms Rev.3.00 Jan. 10, 2007 page 165 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) Table 7.18 Status Read Mode Return Commands Pin Name Attribute FO7 FO6 FO5 FO4 FO3 FO2 FO1 FO0 Normal end Command Programming Erase error identification error error Programming Effective or erase address count error exceeded 0 0 Effective Count exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Initial value 0 0 0 0 0 0 Indications Normal end: Command Programming Erase error: 1 error: 1 error: 1 0 Abnormal end: 1 Otherwise: Otherwise: 0 Otherwise: 0 0 Note: FO2 and FO3 are undefined. 7.8.8 Status Polling (1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. (2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 7.19 Status Polling Output Truth Table Pin Names FO7 FO6 FO0 to FO5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 0 1 0 Normal End 1 1 0 7.8.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 7.20 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 10 10 0 Max Unit ms ms ms Rev.3.00 Jan. 10, 2007 page 166 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) VCC RES FWE tosc1 tbmv Memory read mode Command wait state tdwn Auto-program mode Auto-erase mode Command Don't care wait state Normal/abnormal end identification Don't care Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 7.23 Oscillation Stabilization Time, Boot Program Transfer Time, and Power Supply Fall Sequence 7.8.10 Notes On Memory Programming (1) When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. (2) When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Rev.3.00 Jan. 10, 2007 page 167 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.9 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and programmer mode are summarized below. (1) Use the specified voltages and timing for programming and erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Renesas Technology microcomputer device type with 128-kbyte onchip flash memory. Do not select the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Incorrect use will result in damaging the device. (2) Powering on and off Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. (3) FWE application/disconnection FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: (a) Apply FWE when the VCC voltage has stabilized within its rated voltage range. (b) In boot mode, apply and disconnect FWE during a reset. (c) In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. (d) Do not apply FWE if program runaway has occurred. (e) Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 and FLMCR2 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. (4) Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Rev.3.00 Jan. 10, 2007 page 168 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) (5) Use the recommended algorithm when programming and erasing fash memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. (6) Do not set or clear the SWE bit during program execution in flash memory Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). (7) Do not use interrupts while flash memory is being programmed or erased All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. (8) Do not perform additional aprogramming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 32-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. (9) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (10)Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Rev.3.00 Jan. 10, 2007 page 169 of 1038 REJ09B0328-0300 Section 7 ROM (H8S/2194 Group) 7.10 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 7.21 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 7.21 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 7.21 have no effect. Table 7.21 Registers Present in F-ZTAT Version but Absent in Mask ROM Version Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 Address H'FFF8 H'FFF9 H'FFFA H'FFFB Rev.3.00 Jan. 10, 2007 page 170 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Section 8 ROM (H8S/2194C Group) 8.1 Overview The H8S/2194C has 256 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2194B has 192 kbytes, the H8S/2194A has 160 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. The flash memory versions of the H8S/2194C can be erased and programmed on-board as well as with a general-purpose PROM programmer. 8.1.1 Block Diagram Figure 8.1 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'03FFFE H'03FFFF Figure 8.1 ROM Block Diagram (H8S/2194C) Rev.3.00 Jan. 10, 2007 page 171 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.2 8.2.1 Overview of Flash Memory Features The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing all blocks, the individual blocks must be erased sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-kbyte, and 32kbyte blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and MCU's bit rates. * Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Rev.3.00 Jan. 10, 2007 page 172 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.2.2 Block Diagram Internal address bus Internal data bus (16 bits) STCR FLMCR1 * FLMCR2 * EBR1 EBR2 * * Bus interface/controller Operating mode FWE pin Mode pin Module bus Flash memory (256 kbytes) Legend: STCR FLMCR1 FLMCR2 EBR1 EBR2 : Serial/timer control register : Flash memory control register 1 : Flash memory control register 2 : Erase block register 1 : Erase block register 2 Note: * These registers are exclusively used for the flash memory. If you try to read these addresses with the mask ROM version, values read becomes uncertain. Data write is also disabled with the above version. Figure 8.2 Block Diagram of Flash Memory Rev.3.00 Jan. 10, 2007 page 173 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.2.3 Flash Memory Operating Modes (1) Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 8.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. =0 M 1, D0 = FWE Reset state FWE = 1, MD0 = 0, P12 = P13 = P14 = 1 User mode FWE = 0 or SWE = 0 User program mode RES =0 * RES = 0 RES = 0 FWE = 1 SWE = 1 RE S = 0 Programmer mode Boot mode On-board program mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, P12 = P13 = 1, P14 = 0 Figure 8.3 Flash Memory Mode Transitions Rev.3.00 Jan. 10, 2007 page 174 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (2) On-Board Programming Modes (a) Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the LSI (originally incorporated in the chip) is started and the programing control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program This LSI Boot program Flash memory RAM SCI This LSI Boot program Flash memory New application program SCI RAM Boot program area Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program This LSI Boot program Flash memory RAM Boot program area Flash memory preprograming erase Programming control program New application program SCI This LSI Boot program Flash memory RAM Boot program area Programming control program SCI Program execution state Figure 8.4 Boot Mode Rev.3.00 Jan. 10, 2007 page 175 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (b) User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/erase control program from the flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. 3. Flash memory initialization The programming/erase control program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. New application program Program execution state Figure 8.5 User Program Mode (Example) Rev.3.00 Jan. 10, 2007 page 176 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (3) Differences between Boot Mode and User Program Mode Table 8.1 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Note: * Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify Program/program-verify To be provided by the user, in accordance with the recommended algorithm. (4) Block Configuration The flash memory is divided into six 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'000000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 16 kbytes 256 kbytes 8 kbytes 8 kbytes 32 kbytes 32 kbytes 32 kbytes 32 kbytes 32 kbytes 32 kbytes Address H'03FFFF 256-kbyte version Figure 8.6 Flash Memory Block Configuration Rev.3.00 Jan. 10, 2007 page 177 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 8.2. Table 8.2 Pin Name Reset Flash write enable Mode 0 Port 12 Port 13 Port 14 Transmit data Receive data Flash Memory Pins Abbreviation RES FWE MD0 P12 P13 P14 SO1 SI1 I/O Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI operating mode Sets this LSI operating mode when MD0 = 0 Sets this LSI operating mode when MD0 = 0 Sets this LSI operating mode when MD0 = 0 Serial transmit data output Serial receive data input 8.2.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 8.3. In order to access these registers, the FLSHE bit in STCR must be set to 1. Table 8.3 Flash Memory Registers Abbreviation FLMCR1* 4 FLMCR2* 4 4 EBR1* 4 EBR2* Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Serial/timer control register R/W R/W* 1 R/W* 1 1 R/W* 1 R/W* Initial Value H'00* 3 H'00* 2 3 H'00* 3 H'00* Address* H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFEE 5 STCR R/W H'00 Notes: 1. When the FWE bit in FLMCR1 is not set at 1, writes are disabled. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 4. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 5. Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 178 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.3 8.3.1 Flash Memory Register Descriptions Flash Memory Control Register 1 (FLMCR1) Bit : 7 FWE --* R 6 SWE 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W Initial value : R/W : Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE to 1 while FWE is 1 and then setting the EV1 bit or PV1 bit. Program mode for addresses H'00000 to H'1FFFF is entered by setting SWE to 1 while FWE is 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting SWE to 1 while FWE is 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), or when a low level is input to the FWE pin. When a high level is input to the FWE pin, its initial value is H'80 and when a low level is input, its initial value is H'00. Writes to the SWE, ESU1, PSU1, EV1, and PV1 bits in FLMCR1 are enabled only when FWE = 1 and SWE = 1; writes to the E1 bit only when FWE = 1, SWE = 1, and ESU1 = 1; and writes to the P1 bit only when FWE = 1, SWE = 1, and PSU1 = 1. Bit 7Flash Write Enable (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Rev.3.00 Jan. 10, 2007 page 179 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Bit 6Software Write Enable (SWE): Enables or disables flash memory programming. SWE should be set before setting bits 5 to 0, bits 5 to 0 in FLMCR2, bits 5 to 0 in EBR1 and bits 7 to 0 in EBR2. Bit 6 SWE 0 1 Description Writes are disabled Writes are enabled [Setting condition] Setting is available when FWE = 1 is selected (Initial value) Bit 5Erase-Setup Bit 1 (ESU1): Prepares erase-mode transition for addresses H'00000 to H'1FFFF. Set ESU1 to 1 before setting the E1 bit to 1. Do not set the SWE, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 0 1 Description Erase-setup cleared Erase-setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 4Program-Setup Bit 1 (PSU1): Prepares erase-mode transition for addresses H'00000 to H'1FFFF. Set PSU1 to 1 before setting the P1 bit to 1. Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 0 1 Description Program-setup cleared Program-setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Rev.3.00 Jan. 10, 2007 page 180 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Bit 3Erase-Verify (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected (Initial value) Bit 2Program-Verify (PV1) Selects program-verify mode transition or clearing. Do not set the SWE, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected (Initial value) Bit 1Erase (E1): Selects erase mode transition or clearing. Do not set the SWE, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 E1 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and ESU = 1 are selected (Initial value) Rev.3.00 Jan. 10, 2007 page 181 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Bit 0Program (P1): Selects program mode transition or clearing. Do not set the SWE, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 P1 0 1 Description Program mode cleared Transition to program mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and PSU = 1 are selected (Initial value) Rev.3.00 Jan. 10, 2007 page 182 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.3.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 FLER 0 R 6 -- 0 -- 5 ESU2 0 R/W 4 PSU2 0 R/W 3 EV2 0 R/W 2 PV2 0 R/W 1 E2 0 R/W 0 P2 0 R/W Initial value : R/W : FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'20000 to H'3FFFF is entered by setting SWE in FLMCR1 to 1 while FWE in FLMCR1 is 1 and then setting the EV2 bit or PV2 bit. Program mode for addresses H'20000 to H'3FFFF is entered by setting SWE in FLMCR1 to 1 while FWE in FLMCR1 is 1, then setting the PSU2 bit, and finally setting the P2 bit. Erase mode for addresses H'20000 to H'3FFFF is entered by setting SWE in FLMCR1 to 1 while FWE in FLMCR1 is 1, then setting the ESU2 bit, and finally setting the E2 bit. FLMCR2 is initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. However, FLER is initialized only by a reset. Writes to the ESU2, PSU2, EV2, and PV2 bits in FLMCR2 are enabled only when FWE in FLMCR1 = 1 and SWE in FLMCR1 = 1; writes to the E2 bit only when FWE in FLMCR1 = 1, SWE in FLMCR1 = 1, and ESU2 = 1; and writes to the P2 bit only when FWE in FLMCR1 = 1, SWE in FLMCR1 = 1, and PSU2 = 1. Bit 7Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 8.6.3, Error Protection (Initial value) Bit 6Reserved: This bit cannot be modified and is always read as 0. Rev.3.00 Jan. 10, 2007 page 183 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Bit 5Erase-Setup Bit 2 (ESU2): Prepares erase-mode transition for addresses H'20000 to H'3FFFF. Set ESU2 to 1 before setting the E2 bit to 1. Do not set the PSU2, EV2, PV2, E2, or P2 bit at the same time. Bit 5 ESU2 0 1 Description Erase-setup cleared Erase-setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 4Program-Setup Bit 2 (PSU2): Prepares erase-mode transition for addresses H'20000 to H'3FFFF. Set PSU2 to 1 before setting the P2 bit to 1. Do not set the ESU2, EV2, PV2, E2, or P2 bit at the same time. Bit 4 PSU2 0 1 Description Program-setup cleared Program-setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 3Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing for addresses H'20000 to H'3FFFF. Do not set the ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3 EV2 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Rev.3.00 Jan. 10, 2007 page 184 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Bit 2Program-Verify 2 (PV2): Selects program-verify mode transition or clearing for addresses H'20000 to H'3FFFF. Do not set the ESU2, PSU2, EV2, E2, or P2 bit at the same time. Bit 2 PV2 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 1Erase 2 (E2): Selects erase mode transition or clearing for addresses H'20000 to H'3FFFF. Do not set the ESU2, PSU2, EV2, PV2, or P2 bit at the same time. Bit 1 E2 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU2 = 1 (Initial value) Bit 0Program 2 (P2) Selects program-mode transition or clearing for addresses H'20000 to H'3FFFF. Do not set the ESU2, PSU2, EV2, PV2, or E2 bit at the same time. Bit 0 P2 0 1 Description Program-mode cleared Transition to program-mode [Setting condition] When FWE = 1, SWE = 1, and PSU2 = 1 (Initial value) Rev.3.00 Jan. 10, 2007 page 185 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.3.3 Erase Block Registers 1 (EBR1) Bit : EBR1 : 7 -- 0 -- 6 -- 0 -- 5 EB13 0 R/W 4 EB12 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Initial value : R/W : EBR1 is a register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). The flash memory block configuration is shown in table 8.3. 8.3.4 Erase Block Registers 2 (EBR2) Bit : EBR2 : Initial value : R/W : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W EBR2 is a register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). The flash memory block configuration is shown in table 8.4. Rev.3.00 Jan. 10, 2007 page 186 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Table 8.4 Block (Size) Flash Memory Erase Blocks 128-kbyte Versions EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) EB10 (32 kbytes) EB11 (32 kbytes) EB12 (32 kbytes) EB13 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF H'020000 to H'027FFF H'028000 to H'02FFFF H'030000 to H'037FFF H'038000 to H'03FFFF 8.3.5 Bit Serial/Timer Control Register (STCR) : : : 7 -- 0 -- 6 IICX 0 R/W 5 IICRST 0 R/W 4 -- 0 -- 3 FLSHE 0 R/W 2 -- 0 -- 2 1 -- 0 -- 0 -- 0 -- Initial value R/W STCR is an 8-bit readable/writable register that controls register access, the I C bus interface 2 operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the I C bus interface serial clock frequency. For details on functions not related to on-chip flash memory, see section 25.2.7, Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset. Bits 6 and 5I C Control (IICX, IICRST): These bits control the operation of the I C bus 2 interface. For details, see section 25, I C Bus Interface (IIC). 2 2 Rev.3.00 Jan. 10, 2007 page 187 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Bit 3Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE 0 1 Description Flash memory control registers deselected Flash memory control registers selected (Initial value) Bits 7, 4 and 2 to 0Reserved 8.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 8.5. For a diagram of the transitions to the various flash memory modes, see figure 8.3. Table 8.5 Mode Mode Name Boot mode User program mode Setting On-Board Programming Modes Pin FWE 1 1* 1 MD0 0 1 P12 2 1* P13 2 1* P14 1* 2 Notes: 1. In user program mode, the FWE pin should not be constantly set to 1. Set FWE to 1 to make a transition to user program mode before performing a program/erase/verify operation. 2. Can be used as I/O ports after boot mode is initiated. Rev.3.00 Jan. 10, 2007 page 188 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the MCU's pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI1. In the MCU, the programming control program received via the SCI1 is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 8.7, and the boot program mode execution procedure in figure 8.8. This LSI Flash memory Host Write data reception Verify data transmission SI1 SCI1 SO1 On-chip RAM Figure 8.7 System Configuration in Boot Mode Rev.3.00 Jan. 10, 2007 page 189 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00) and transmits one H'55 data byte Upon receiving H'55, this LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte This LSI transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units This LSI transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, this LSI transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM Note : If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. n+1n n = N? Figure 8.8 Boot Mode Execution Procedure Rev.3.00 Jan. 10, 2007 page 190 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (1) Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 8.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the MCU's system clock frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation, the host's transfer bit rate should be set to (4800 or 9600) bps. Table 8.6 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU's bit rate is possible. The boot program should be executed within this system clock range. Table 8.6 System Clock Frequencies for which Automatic Adjustment of This LSI Bit Rate Is Possible System Clock Frequency for which Automatic Adjustment of This LSI Bit Rate is Possible 8 MHz to 10 MHz 4 MHz to 10 MHz Host Bit Rate 9600 bps 4800 bps Rev.3.00 Jan. 10, 2007 page 191 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (2) On-Chip RAM Area Divisions in Boot Mode In boot mode, the RAM area is divided into; the area for use by the boot program and the area to which programming control program is transferred by the SCI, as shown in figure 8.10. The boot program area cannot be used until a transition is made to the execution state in boot mode for the programming control program transferred to RAM. H'FFE7B0 Boot program area* (3 kbytes) H'FFF3AF Programming control program area (2944 bytes) H'FFFF2F H'FFFFAF Reserved area (128 bytes) Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program reamins stored in this area after a branch is made to the programming control program. Figure 8.10 RAM Areas in Boot Mode (3) Notes on Use of Boot Mode: (a) When reset is released in boot mode, it measures the low period of the input at the SCI1's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input. (b) In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. (c) Interrupts cannot be used while the flash memory is being programmed or erased. (d) The SI1 and SO1 pins should be pulled up on the board. Rev.3.00 Jan. 10, 2007 page 192 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (e) Before branching to the programming control program (RAM area H'FFF3B0), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. (f) Boot mode can be entered by making the pin settings shown in table 8.6 and executing a reset-start. 1 When the chip detects the boot mode setting at reset release* , it retains that state internally. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then 1 setting the FWE pin and mode pins, and executing reset release* . Boot mode can also be cleared by a WDT overflow reset. If the mode pin input levels are changed in boot mode, the boot mode state will be maintained in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin must not be driven low while the boot program is running or flash 2 memory is being programmed or erased* . Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For further information on FWE application and disconnection, see section 8.9, Flash Memory Programming and Erasing Precautions. 8.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. In this mode, the chip starts up in mode 1 and applies a high level to the FWE pin. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 8.11 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Rev.3.00 Jan. 10, 2007 page 193 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD0 = 1 Reset start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 8.9, Flash Memory Programming and Erasing Precautions. Figure 8.11 User Program Mode Execution Procedure (Preliminary) Rev.3.00 Jan. 10, 2007 page 194 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.5 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. For addresses H'00000 to H'1FFFF, transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in FLMCR1 and for addresses H'20000 to H'3FFFF, transitions to these modes can be made by setting the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU1, PSU1, EV1, PV1, E1, and P1 bits in FLMCR1, and the ESU2, PSU2, EV2, PV2, E2 and P2 bits in FLMCR2, is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Do not program addresses H'00000 to H'1FFFF and H'20000 to H'3FFFF at the same time. Operation is not guaranteed if both areas are programmed at the same time. Program Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) Follow the procedure shown in the program/program-verify flowchart in figure 8.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. Table 29.12 lists wait time (x, y, z, , , , , and ) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum write count (N). Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Rev.3.00 Jan. 10, 2007 page 195 of 1038 REJ09B0328-0300 8.5.1 Section 8 ROM (H8S/2194C Group) Set more than (y + z + + ) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. 8.5.2 Program-Verify Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the Pn bit in FLMCRn is cleared, then the PSUn bit in FLMCRn is cleared at least () s later). The watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to programverify mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 8.12) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least () s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Rev.3.00 Jan. 10, 2007 page 196 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) START Set SWE bit in FLMCR1 Wait (x) s Programming must be excuted in the erased state. Do not perform additional programming on addresses that have already been programmed. *5 *4 Store 32-byte program data in program data area and reprogram data area n=1 m=0 Write 32-byte data in RAM reprogram data area consecutively to flash memory Enable WDT Set PSU bit in FLMCR1 or FLMCR2 Wait (y) s Set P bit in FLMCR1 or FLMCR2 Wait (z) s Clear P bit in FLMCR1 or FLMCR2 Wait () s Clear PSU bit in FLMCR1 or FLMCR2 Wait () s Disable WDT Set PV bit in FLMCR1 or FLMCR2 Wait () s H'FF dummy write to verify address Wait () s Read verify data Increment address Program data = verify data? YES Reprogram data computation NO *1 *5 Start of programming *5 End of programming *5 nn+1 *5 *5 *5 *2 m=1 *3 *4 Transfer reprogram data to reprogram data area End of 32-byte data verification? NO RAM Program data storage area (32 bytes) YES Clear PV bit in FLMCR1 or FLMCR2 Wait () s m = 0? YES Clear SWE bit in FLMCR1 End of programming *5 NO *5 n N? Reprogram data storage area (32 bytes) NO YES Clear SWE bit in FLMCR1 Programming failure Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even in case of the bit which is already-programmed in the 32-byte programming loop, perform additional programming if the bit fails at the next verify. 4. An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten as programming progresses. 5. The values of x, y, z, , , , , , and N are listed in section 29.2.7, Flash Memory Characteristics. Program data 0 0 1 1 Verify data 0 1 0 1 Reprogram data 1 0 1 1 Comments Do not reprogram bits for which programming has been completed. Programming incomplete; reprogramming should be performed. -- Still in erased state; no action Figure 8.12 Program/Program-Verify Flowchart Rev.3.00 Jan. 10, 2007 page 197 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.5.3 Erase Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 8.13. Table 29.12 lists wait time (x, y, z, , , , , and ) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum clearing count (N). To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set more than (y + z + + ) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time during which the En bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 8.5.4 Erase-Verify Mode (n = 1 for Addresses H'00000 to H'1FFFF and n = 2 for Addresses H'20000 to H'3FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then the ESU bit in FLMCR2 is cleared at least () s later), the watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. Rev.3.00 Jan. 10, 2007 page 198 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) START *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 or FLMCR2 Wait (y) s Set E bit in FLMCR1 or FLMCR2 Wait (z) ms Clear E bit in FLMCR1 or FLMCR2 Wait () s Clear ESU bit in FLMCR1 or FLMCR2 Wait () s Disable WDT Set EV bit in FLMCR1 or FLMCR2 Wait () s Set block start address to verify address H'FF dummy write to verify address Wait () s Read verify data Increment address Verify data = all 1? YES NO Last address of block? YES Clear EV bit in FLMCR1 or FLMCR2 Wait () s Clear EV bit in FLMCR1 or FLMCR2 Wait () s NO *2 *4 *2 Start of erase *2 Halt erase *2 *2 *2 nn+1 *2 *3 *2 NO *5 End of erasing of all erase blocks? YES Clear SWE bit in FLMCR1 End of erasing n N? YES *2 *2 NO Clear SWE bit in FLMCR1 Erase failure Notes: 1. 2. 3. 4. 5. Preprogramming (setting erase block data to all 0) is not necessary. The values of x, y, z, , , , , , and N are listed in section 29.2.7, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. Set only one bit in EBR1 or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 8.13 Erase/Erase-Verify Flowchart (Single-Block Erase) Rev.3.00 Jan. 10, 2007 page 199 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 8.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 8.7.) Table 8.7 Hardware Protection Functions Item FWE pin protection Reset/standby protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered In a reset (including a WDT overflow reset) and in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), FLMCR1, FLMCR2 (excluding the FLER bit), EBR1, and EBR2 are initialized, and the program/eraseprotected state is entered In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC characteristics section Program Yes Erase Yes * Yes Yes * Rev.3.00 Jan. 10, 2007 page 200 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.6.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or setting the P2 or E2 bit in flash memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode. (See table 8.8.) Table 8.8 Software Protection Functions Item SWE bit protection Block specification protection Description * Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory) Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2) Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state Program Yes Erase Yes * Yes * Rev.3.00 Jan. 10, 2007 page 201 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, E1, P2 or E2 bit. However, PV1, EV1, PV2, or EV2 bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: (1) When flash memory is read during programming/erasing (including a vector read or instruction fetch) (2) Immediately after exception handling (excluding a reset) during programming/erasing (3) When a SLEEP instruction is executed during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 8.14 shows the flash memory state transition diagram. Rev.3.00 Jan. 10, 2007 page 202 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 Reset (hardware protection) RD VF PR ER FLER = 0 Error occurrence E SL rror EE occ P u ex ins rren ec tru ce uti ct on ion RE S =0 RES = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Power-down state* Power-down state* release Error protection mode (Power-down state)* RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF : Verify-read possible PR : Programming possible ER : Erasing possible RD: Memory read not possible VF : Verify-read not possible PR : Programming not possible ER : Erasing not possible Note: * Watch mode, standby mode, and subactive mode Figure 8.14 Flash Memory State Transitions Rev.3.00 Jan. 10, 2007 page 203 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.7 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the Pn or En bit is set in FLMCRn), and while the boot program is executing in boot 1 mode* , to give priority to the program or erase operation. There are three reasons for this: (1) Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. (2) In the interrupt exception handling sequence during programming or erasing, the vector would 2 not be read correctly* , possibly resulting in MCU runaway. (3) If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI input, must therefore be disabled inside and outside the MCU during FWE application. Interrupt is also disabled in the error-protection state while the Pn or En bit remains set in FLMCRn. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by the write control program is complete. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the Pn or En bit is set in FLMCRn), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the interrupt vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev.3.00 Jan. 10, 2007 page 204 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.8 8.8.1 Flash Memory Programmer Mode Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device type with 256-kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with these device types. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. 8.8.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer. The socket adapter product codes are listed in table 8.9. Figure 8.15 shows the memory map in programmer mode. Table 8.9 Part No. HD64F2194C Socket Adapter Product Codes Package 112-pin QFP Socket Adapter Product Code ME2194ESHF1H MCU mode H'000000 This LSI Programmmer mode H'00000 On-chip ROM area (256 kbytes) H'03FFFF H'3FFFF Figure 8.15 Memory Map in Programmer Mode Rev.3.00 Jan. 10, 2007 page 205 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.8.3 Programmer Mode Operation Table 8.10 shows how the different operating modes are set when using programmer mode, and table 8.11 lists the commands used in programmer mode. Details of each mode are given below. (1) Memory Read Mode Memory read mode supports byte reads. (2) Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. (3) Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. (4) Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO6 signal. In status read mode, error information is output if an error occurs. Table 8.10 Settings for Each Operating Mode in Programmer Mode Pin Names Mode Read Output disable Command write 1 Chip disable* FWE H or L H or L H or L* H or L 3 CE L L L H OE L H H X WE H H L X FO0 to FO7 Data output Hi-Z Data input Hi-Z FA0 to FA17 Ain X Ain* X 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin. Rev.3.00 Jan. 10, 2007 page 206 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Table 8.11 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode write write write write Address X X X X Data H'00 H'40 H'20 H'71 2nd Cycle Mode read write write write Address Data RA WA X X Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 8.8.4 Memory Read Mode (1) After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. (2) Command writes can be performed in memory read mode, just as in the command wait state. (3) Once memory read mode has been entered, consecutive reads can be performed. (4) After power-on, memory read mode is entered. Table 8.12 AC Characteristics in Memory Read Mode (1) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 Max 30 30 Unit s ns ns ns ns ns ns ns Rev.3.00 Jan. 10, 2007 page 207 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Command write ADDRESS Memory read mode ADDRESS STABLE CE OE WE DATA twep tceh tnxtc tces tf tr H'00 tdh tds DATA Note: Data is latched on the rising edge of WE. Figure 8.16 Memory Read Mode Timing Waveforms after Command Write Table 8.13 AC Characteristics when Entering Another Mode from Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 Max 30 30 Unit s ns ns ns ns ns ns ns Rev.3.00 Jan. 10, 2007 page 208 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) XX mode command write ADDRESS ADDRESS STABLE CE OE WE DATA DATA tnxtc tces tf twep tceh tr H'XX tdh tds Note: Do not enable WE and OE at the same time. Figure 8.17 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 8.14 AC Characteristics in Memory Read Mode (2) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min 5 Max 20 150 150 100 Unit s ns ns ns ns Rev.3.00 Jan. 10, 2007 page 209 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) ADDRESS ADDRESS STABLE ADDRESS STABLE CE OE WE tacc DATA DATA toh DATA toh tacc VIL VIL VIH Figure 8.18 Timing Waveforms for CE/OE Enable State Read ADDRESS ADDRESS STABLE ADDRESS STABLE tacc CE OE WE DATA tce toe tdf DATA toh tce toe VIH tdf DATA toh tacc Figure 8.19 Timing Waveforms for CE/OE Clocked Read Rev.3.00 Jan. 10, 2007 page 210 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.8.5 Auto-Program Mode (a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. (b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. (c) The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. (d) Memory address transfer is performed in the second cycle (figure 8.20). Do not perform transfer after the third cycle. (e) Do not perform a command write during a programming operation. (f) Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. (g) Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-program operation end identification pin). (h) The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. Rev.3.00 Jan. 10, 2007 page 211 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Table 8.15 AC Characteristics in Auto-Program (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf tpns tpnh Min 20 0 0 50 50 70 1 0 60 1 100 100 Max 150 3000 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns FWE ADDRESS CE OE WE FO7 tpns ADDRESS STABLE tceh tnxtc twep tces tf tds tdh tr tas tah tpnh tnxtc Data transfer 1 byte to 128 bytes twsts tspa twrite(1 to 3,000 ms) Programming operation end identification signal FO6 Programming normal end identification signal Programming wait DATA H'40 DATA DATA FO0 to 5 = 0 Figure 8.20 Auto-Program Mode Timing Waveforms Rev.3.00 Jan. 10, 2007 page 212 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.8.6 Auto-Erase Mode (a) Auto-erase mode supports only entire memory erasing. (b) Do not perform a command write during auto-erasing. (c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin). (d) The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. Table 8.16 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf tens tenh Min 20 0 0 50 50 70 1 100 100 100 Max 150 40000 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Rev.3.00 Jan. 10, 2007 page 213 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) FWE tens ADDRESS tenh CE OE WE FO7 FO6 tces tceh tspa tnxtc twep tests terase (100 to 40000 ms) Erase end identification signal Erase normal end identification signal CLin DLin H'20 FO0 to 5 = 0 tnxtc tf tds tr tdh FO5 to FO0 H'20 Figure 8.21 Auto-Erase Mode Timing Waveforms 8.8.7 Status Read Mode (1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. (2) The return code is retained until a command write for other than status read mode is performed. Rev.3.00 Jan. 10, 2007 page 214 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Table 8.17 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 Max 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns ADDRESS CE tce OE WE tces tf tds twep tceh tr tdh DATA H'71 tnxtc tces tf tds H'71 twep tceh tr tdh DATA tnxtc toe tdf tnxtc Note: FO2 and FO3 are undefined. Figure 8.22 Status Read Mode Timing Waveforms Rev.3.00 Jan. 10, 2007 page 215 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) Table 8.18 Status Read Mode Return Commands Pin Name Attribute FO7 FO6 FO5 Programming error FO4 FO3 FO2 FO1 FO0 Normal end Command identifica- error tion 0 Erase error Effective Programming or erase address error count exceeded 0 0 Initial value 0 0 0 0 0 Indica-tions Normal end: Command 0 error: 1 Abnormal end: 1 Program- Erase error: ming error: 1 1 Otherwise: 0 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address error: 1 Otherwise: 0 Otherwise: 0 Note: FO2 and FO3 are undefined. 8.8.8 Status Polling (1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. (2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 8.19 Status Polling Output Truth Table Pin Names FO7 FO6 FO0 to FO5 Internal Operation in Progress Abnormal End 0 0 0 1 0 0 0 1 0 Normal End 1 1 0 Rev.3.00 Jan. 10, 2007 page 216 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.8.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 8.20 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 10 10 0 Max Unit ms ms ms VCC RES FWE tosc1 tbmv Memory read mode Command wait state tdwn Auto-program mode Auto-erase mode Command Don't care wait state Normal/abnormal end identification Don't care Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 8.23 Oscillation Stabilization Time, Boot Program Transfer Time, and Power Supply Fall Sequence 8.8.10 Notes On Memory Programming (1) When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. (2) When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Rev.3.00 Jan. 10, 2007 page 217 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.9 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and programmer mode are summarized below. (1) Use the specified voltages and timing for programming and erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Renesas Technology microcomputer device type with 256-kbyte onchip flash memory. Do not select the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Incorrect use will result in damaging the device. (2) Powering on and off Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. (3) FWE application/disconnection FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: (a) Apply FWE when the VCC voltage has stabilized within its rated voltage range. (b) In boot mode, apply and disconnect FWE during a reset. (c) In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. (d) Do not apply FWE if program runaway has occurred. (e) Disconnect FWE only when the SWE, ESU1, ESU2, PSU1, PSU2, EV1, EV2, PV1, PV2, P1, P2, E1, and E2 bits in FLMCR1 and FLMCR2 are cleared. Make sure that the SWE, ESU1, ESU2, PSU1, PSU2, EV1, EV2, PV1, PV2, P1, P2, E1, and E2 bits are not set by mistake when applying or disconnecting FWE. (4) Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Rev.3.00 Jan. 10, 2007 page 218 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) (5) Use the recommended algorithm when programming and erasing flash memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the Pn or En bit in FLMCR1 and FLMCR2, the watchdog timer should be set beforehand as a precaution against program runaway, etc. (6) Do not set or clear the SWE bit during program execution in flash memory Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). (7) Do not use interrupts while flash memory is being programmed or erased All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. (8) Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 32-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. (9) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (10)Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Rev.3.00 Jan. 10, 2007 page 219 of 1038 REJ09B0328-0300 Section 8 ROM (H8S/2194C Group) 8.10 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 8.21 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 8.21 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 8.21 have no effect. Table 8.21 Registers Present in F-ZTAT Version but Absent in Mask ROM Version Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 Address H'FFF8 H'FFF9 H'FFFA H'FFFB Rev.3.00 Jan. 10, 2007 page 220 of 1038 REJ09B0328-0300 Section 9 RAM Section 9 RAM 9.1 Overview The H8S/2194C, H8S/2194B, and H8S/2194A have 6 kbytes, and the H8S/2194, H8S/2193, H8S/2192, and H8S/2191 have 3 kbytes, of on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. 9.1.1 Block Diagram Figure 9.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFF3B0 H'FFF3B2 H'FFF3B4 H'FFF3B1 H'FFF3B3 H'FFF3B5 H'FFFFAE H'FFFFAF Figure 9.1 Block Diagram of RAM (H8S/2194) Rev.3.00 Jan. 10, 2007 page 221 of 1038 REJ09B0328-0300 Section 9 RAM Rev.3.00 Jan. 10, 2007 page 222 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator Section 10 Clock Pulse Generator 10.1 Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit. 10.1.1 Block Diagram Figure 10.1 shows a block diagram of the clock pulse generator. /16, /32, /64 w/2, w/4, w/8 or SUB Bus master clock To CPU Clock selection circuit OSC1 OSC2 System clock oscillator Duty adjustment circuit Mediumspeed clock divider SUB X1 X2 Subclock oscillator Subclock division circuit Timer A count clock Internal clock To supporting modules SUB (w/2, w/4, w/8) Figure 10.1 Block Diagram of Clock Pulse Generator 10.1.2 Register Configuration The clock pulse generator is controlled by SBYCR and LPWRCR. Table 10.1 shows the register configuration. Table 10.1 CPG Registers Name Standby control register Low-power control register Note: * Abbreviation SBYCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FFEA H'FFEB Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 223 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.2 10.2.1 Register Descriptions Standby Control Register (SBYCR) Bit : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 -- 0 -- 2 -- 0 -- 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby Control Register (SBYCR). SBYCR is initialized to H'00 by a reset. Bits 1 and 0System Clock Select 1 and 0 (SCK1, SCK0): These bits select the bus master clock for high-speed mode and medium-speed mode. Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 Description Bus master is in high-speed mode Medium-speed clock is /16 Medium-speed clock is /32 Medium-speed clock is /64 (Initial value) Rev.3.00 Jan. 10, 2007 page 224 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.2.2 Low-Power Control Register (LPWRCR) Bit : 7 DTON 0 R/W 6 LSON 0 R/W 5 NESEL 0 R/W 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 SA1 0 R/W 0 SA0 0 R/W Initial value : R/W : LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, LowPower Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset. Bits 1 and 0Subactive Mode Clock Select (SA1, SA0): Selects CPU clock for subactive mode. In subactive mode, writes are disabled. Bit 1 SA1 0 Bit 0 SA0 0 1 1 * Legend: * Don't care Description CPU operating clock is w/8 CPU operating clock is w/4 CPU operating clock is w/2 (Initial value) Rev.3.00 Jan. 10, 2007 page 225 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 10.3.1 Connecting a Crystal Resonator (1) Circuit Configuration A crystal resonator can be connected as shown in the example in figure 10.2. An AT-cut parallel-resonance crystal should be used. CL1 OSC1 Rf OSC2 CL2 Rf = 1M 20% CL1 = CL2 = 10 to 22 pF Figure 10.2 Connection of Crystal Resonator (Example) (2) Crystal Resonator Figure 10.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 10.2 and the same frequency as the system clock (). CL L OSC1 Rs OSC2 AT-cut parallel-resonance type C0 Figure 10.3 Crystal Resonator Equivalent Circuit Table 10.2 Crystal Resonator Parameters Frequency (MHz) RSmax () COmax (pF) 8 80 7 10 60 7 Rev.3.00 Jan. 10, 2007 page 226 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator (3) Note on Board Design When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 10.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Avoid CL2 Rf OSC2 CL1 Signal A Signal B This chip OSC1 Figure 10.4 Example of Incorrect Board Design Rev.3.00 Jan. 10, 2007 page 227 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.3.2 External Clock Input (1) Circuit Configuration An external clock signal can be input as shown in the examples in figure 10.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. OSC1 OSC2 Open External clock input (a) OSC2 pin left open OSC1 OSC2 External clock input (b) Completely clock input at OSC2 pin Figure 10.5 External Clock Input (Examples) (2) External Clock The external clock signal should have the same frequency as the system clock (). Table 10.3 and figure 10.6 show the input conditions for the external clock. Table 10.3 External Clock Input Conditions VCC = 4.0 to 5.5 V Item Symbol Min 40 40 Max 10 10 Unit ns ns ns ns Test Conditions Figure 10.6 External clock input low pulse width tCPL External clock input high pulse width tCPH External clock rise time External clock fall time tCPr tCPf Rev.3.00 Jan. 10, 2007 page 228 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator tCPH tCPL OSC1 tCPr tCPf Figure 10.6 External Clock Input Timing Table 10.4 shows the external clock output settling delay time, and figure 10.7 shows the external clock output settling delay timing. The oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the OSC1 pin. When the prescribed clock signal is input at the OSC1 pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT period, the reset signal should be driven low to maintain the reset state. Table 10.4 External Clock Output Settling Delay Time (Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V) Item External clock output settling delay time Note: * Symbol tDEXT* Min 500 Max Unit s Notes Figure 10.7 tDEXT includes 20 tCYC of RES pulse width (tRESW). Rev.3.00 Jan. 10, 2007 page 229 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator VCC 4.0 V OSC1 (Internal) RES tDEXT* Note: * tDEXT includes 20 tcyc of RES pulse width (tRESW). Figure 10.7 External Clock Output Settling Delay Timing 10.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (). 10.5 Medium-Speed Clock Divider The medium-speed divider divides the system clock to generate /16, /32, and /64 clocks. 10.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock () or one of the medium-speed clocks (/16, /32 or /64) to be supplied to the bus master (CPU), according to the settings of bits SCK2 to SCK0 in SBYCR. Rev.3.00 Jan. 10, 2007 page 230 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.7 10.7.1 Subclock Oscillator Circuit Connecting 32.768 kHz Crystal Resonator When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in figure 10.8. For precautions on connecting, see section 10.3.1 (3), Note on Board Design. The subclock input conditions are shown in figure 10.10. C1 X1 X2 C2 C1 = C2 = 15 pF (Typ) Figure 10.8 Connecting a 32.768 kHz Crystal Resonator (Example) Figure 10.9 shows a crystal resonator equivalent circuit. CS Ls X1 Rs X2 C0 = 1.5 pF (Typ) RS = 14 k (Typ) fW = 32.768 kHz C0 Note: Values shown are the reference values. Figure 10.9 32.768 kHz Crystal Resonator Equivalent Circuit Rev.3.00 Jan. 10, 2007 page 231 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.7.2 External Clock Input (1) Circuit Configuration When external clock input connect to the X1 pin, and X2 pin should remain open as connection example of figure 10.10. External clock input X1 X2 Open Figure 10.10 Connection Example when Inputting External Clock 10.7.3 When Subclock Is Not Needed Connect X1 pin to VCC, and X2 pin should remain open as shown in figure 10.11. VCC X1 X2 Open Figure 10.11 Terminal When Subclock Is Not Needed Rev.3.00 Jan. 10, 2007 page 232 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator 10.8 Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a clock obtained by dividing the clock. The sampling frequency is set with the NESEL bit in LPWRCR. For details, see section 4.2.2, Low-Power Control Register (LPWRCR). The clock is not sampled in subactive mode, subsleep mode, or watch mode. 10.9 Notes on the Resonator Resonator characteristics are closely related to the user board design. Perform appropriate assessment of resonator connection, mask version and F-ZTAT, by referring to the connection example given in this section. The resonator circuit rate differs depending on the free capacity of the resonator and the execution circuit, so consult with the resonator manufacturer before determination. Make sure the voltage applied to the resonator pin does not exceed the maximum rated voltage. Rev.3.00 Jan. 10, 2007 page 233 of 1038 REJ09B0328-0300 Section 10 Clock Pulse Generator Rev.3.00 Jan. 10, 2007 page 234 of 1038 REJ09B0328-0300 Section 11 I/O Port Section 11 I/O Port 11.1 11.1.1 Overview Port Functions This LSI has seven 8-bit I/O ports (including one CMOS high-current port), one 4-bit I/O port, and one 8-bit input port. Table 11.1 shows the functions of each port. Each I/O part a port control register (PCR) that controls an input and output and a port data register (PDR) for storing output data. The input and output can be controlled in a unit of bit. The pin whose peripheral function is used both as an alternative function can set the pin function in a unit of bit by a port mode register (PMR). 11.1.2 Port Input * Reading a Port When a general port of PCR = 0 (input) is read, the pin level is read. When a general port of PCR = 1 (output) is read, the value of the corresponding PDR bit is read. When the pins (excluding AN7 to AN0 and RP7 to RP0 pins) set to the peripheral function are read, the results are as given in items (1) and (2) according to the PCR value. * Processing Input Pins The general input port or general I/O port is gated by read signals. Unused pins can be left open if they are not read. However, if an open pin is read, a feedthrough current may apply during the read period according to an intermediate level. The read period is about one-state. Relevant ports: P0, P1, P2, P3, P4, P5, P6, P7, P8 When an alternative pin is set to an alternative function other than the general I/O, always set the pin level to a high or low level. If the pin is left open, a feedthrough current applies according to an intermediate level, which adversely affects reliability, causes malfunctions, and in the worst case may damage the pin. Because the PMR is not initialized in low power consumption mode, pay attention to the pin input level after the mode has been shifted to the low power consumption mode. Relevant pins: IC, IRQ0 to IRQ5, SCK1, SCK2, SI1, SI2, CS, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, ADTRG, EXCAP, EXTTRG Rev.3.00 Jan. 10, 2007 page 235 of 1038 REJ09B0328-0300 Section 11 I/O Port Table 11.1 Port Functions Port Port 0 Port 1 Description P07 to P00 input-only ports P17 to P10 I/O ports (Built-in MOS pull-up transistors) Pins P07/AN7 to P00/AN0 P17/TMOW P16/IC P15/IRQ5 to P10/IRQ0 P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 P37/TMO P36/BUZZ P35/PWM3 to P32/PWM0 P31/STRB P30/CS P47 P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/PWM14 P53/TRIG P52/TMBI P51 P50/ADTRG P67/RP7 to P60/RP0 P77/PPG7 to P70/PPG0 P87 to P84 P83/SV2 P82/SV1 P81/EXCAP P80/EXTTRG Alternative Functions Analog data input channels 7 to 0 Function Switching Register PMR0 Prescalar unit frequency division clock PMR1 output Prescalar unit input capture input External interrupt request input SCI2 clock I/O SCI2 transmit data output SCI2 receive data input I2C bus interface clock I/O I2C bus interface data I/O SCI1 clock I/O SCI1 transmit data output SCI1 receive data input Timer J timer output Timer J buzzer output 8-bit PWM output SCI2 strobe output SCI2 chip select input None Timer X output compare B output Timer X output compare A output Timer X input capture D input Timer X input capture C input Timer X input capture B input Timer X input capture A input 14-bit PWM output Realtime output port trigger input Timer B event input None A/D conversion start external trigger input Realtime output port PPG output None Servo monitor output Capstan external synchronous signal input External trigger signal input PMR2 Port 2 P27 to P20 I/O ports (Built-in MOS pull-up transistors) ICCR SMR SCR PMR3 Port 3 P37 to P30 I/O ports (Built-in MOS pull-up transistors) Port 4 P47 to P40 I/O ports TOCR Port 5 P53 to P50 I/O ports PMR4 PMR5 ADTSR PMR6 PMR7 PMR8 Port 6 Port 7 Port 8 P67 to P60 I/O ports P77 to P70 I/O ports P87 to P80 I/O ports (High-current ports) Rev.3.00 Jan. 10, 2007 page 236 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.1.3 MOS Pull-Up Transistors The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the pin function is set to an input by PCR1 to PCR3. If the pin function is set to an output, the MOS pullup transistor is turned off. Figure 11.1 shows the circuit configuration of a pin with a MOS pull-up transistor. When the pin whose peripheral function is used both as an alternative function is set to the alternative output function, the MOS pull-up transistor is turned off. When the pin is set to the alternative input function, the MOS pull-up transistor is controlled according to the PUR setting regardless of PCR. LPWRM PUR VCC VCC PCR PDR VSS Input data LPWRM : Low power consumption mode signal (The MOS pull-up transistor is turned off in reset, standby, and watch modes.) PUR : MOS pull-up select register PCR : Port control register PDR : Port data register Figure 11.1 Circuit Configuration of Pin with MOS Pull-Up Transistor Rev.3.00 Jan. 10, 2007 page 237 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.2 11.2.1 Port 0 Overview Port 0 is an 8-bit input-only port. Table 11.2 shows the port 0 configuration. Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input channels (AN7 to AN0). It is switched by port mode register 0 (PMR0). Table 11.2 Port 0 Configuration Port Port 0 Function P07 (standard input port) P06 (standard input port) P05 (standard input port) P04 (standard input port) P03 (standard input port) P02 (standard input port) P01 (standard input port) P00 (standard input port) Alternative Function AN7 (analog input channel) AN6 (analog input channel) AN5 (analog input channel) AN4 (analog input channel) AN3 (analog input channel) AN2 (analog input channel) AN1 (analog input channel) AN0 (analog input channel) 11.2.2 Register Configuration Table 11.3 shows the port 0 register configuration. Table 11.3 Port 0 Register Configuration Name Port mode register 0 Port data register 0 Note: * Abbrev. PMR0 PDR0 R/W R/W R Size Byte Byte Initial Value Address* H'00 H'FFCD H'FFC0 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 238 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 0 (PMR0) Bit : Initial value : R/W : 7 PMR07 0 R/W 6 PMR06 0 R/W 5 PMR05 0 R/W 4 PMR04 0 R/W 3 PMR03 0 R/W 2 PMR02 0 R/W 1 PMR01 0 R/W 0 PMR00 0 R/W Port mode register 0 (PMR0) controls switching of each pin function of port 0. The switching is specified in a unit of bit. PMR0 is an 8-bit read/write enable register. When reset, PMR0 is initialized to H'00. Bits 7 to 0P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): PMR07 to PMR00 sets whether the P0n/ANn pin is used as a P0n input pin or an ANn pin for the analog input channel of an A/D converter. Bit n PMR0n 0 1 Description The P0n/ANn pin functions as a P0n input pin The P0n/ANn pin functions as an ANn input pin (Initial value) Note: n = 7 to 0 (2) Port Data Register 0 (PDR0) Bit : Initial value : R/W : 7 PDR07 -- R 6 PDR06 -- R 5 PDR05 -- R 4 PDR04 -- R 3 PDR03 -- R 2 PDR02 -- R 1 PDR01 -- R 0 PDR00 -- R Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0 (general input port), the pin state is read if PDR0 is read. When the corresponding bit of PMR0 is 1 (analog input channel), 1 is read if PDR0 is read. PDR0 is an 8-bit read-only register. When PDR0 is reset, its values become undefined. Rev.3.00 Jan. 10, 2007 page 239 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.2.3 Pin Functions This section describes the pin functions of port 0 and their selection methods. (1) P07/AN7 to P00/AN0 P07/AN7 to P00/AN0 are switched according to the PMR0n bit of PMR0 as shown below. PMR0n 0 1 Note: n = 7 to 0 Pin Function P0n input pin ANn input pin 11.2.4 Pin States Table 11.4 shows the pin 0 states in each operation mode. Table 11.4 Port 0 Pin States Pins P07/AN7 to P00/AN0 Reset Highimpedance Active Highimpedance Sleep Highimpedance Standby Highimpedance Watch Highimpedance Subactive Subsleep HighHighimpedance impedance Rev.3.00 Jan. 10, 2007 page 240 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.3 11.3.1 Port 1 Overview Port 1 is an 8-bit I/O port. Table 11.5 shows the port 1 configuration. Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division clock output (TMOW), input capture input (IC), or external interrupt request inputs (IRQ5 to IRQ0). It is switched by port mode register 1 (PMR1) and port control register 1 (PCR1). Port 1 can select the functions of MOS pull-up transistors. Table 11.5 Port 1 Configuration Port Port 1 Function P17 (standard I/O port) P16 (standard I/O port) P15 (standard I/O port) P14 (standard I/O port) P13 (standard I/O port) P12 (standard I/O port) P11 (standard I/O port) P10 (standard I/O port) Alternative Function TMOW (frequency division clock output) IC (input capture input) IRQ5 (external interrupt request input) IRQ4 (external interrupt request input) IRQ3 (external interrupt request input) IRQ2 (external interrupt request input) IRQ1 (external interrupt request input) IRQ0 (external interrupt request input) 11.3.2 Register Configuration Table 11.6 shows the port 1 register configuration. Table 11.6 Port 1 Register Configuration Name Port mode register 1 Port control register 1 Port data register 1 Abbrev. PMR1 PCR1 PDR1 R/W R/W W R/W R/W Size Byte Byte Byte Byte Initial Value Address* H'00 H'00 H'00 H'00 H'FFCE H'FFD1 H'FFC1 H'FFE1 MOS pull-up select register PUR1 1 Note: * Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 241 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 1 (PMR1) Bit : Initial value : R/W : 7 PMR17 0 R/W 6 PMR16 0 R/W 5 PMR15 0 R/W 4 PMR14 0 R/W 3 PMR13 0 R/W 2 PMR12 0 R/W 1 PMR11 0 R/W 0 PMR10 0 R/W Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00. Note the following items when the pin functions are switched by PMR1. (1) If port 1 is set to an IC input pin and IRQ5 to IRQ0 by PMR1, the pin level needs be set to the high or low level regardless of the active mode and low power consumption mode. The pin level must not be set to an intermediate level. (2) When the pin functions of P16/IC and P15/IRQ5 to P10/IRQ0 are switched by PMR1, they are incorrectly recognized as edge detection according to the state of a pin signal and a detection signal may be generated. To prevent this, perform the operation in the following procedure. (a) Before switching the pin functions, inhibit an interrupt enable flag from being interrupted. (b) After having switched the pin functions, clear the relevant interrupt request flag to 0 by a single instruction. (Program Example) : MOV.B ROL,@IENR Interrupt disabled MOV.B R1L,@PMR1 Pin function change NOP BCLR m @IRQR Optional instruction Applicable interrupt clear MOV.B R1L,@IENR Interrupt enabled : Bit 7P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used as a P17 I/O pin or a TMOW pin for the frequency division clock output. Bit 7 PMR17 0 1 Description The P17/TMOW pin functions as a P17 I/O pin The P17/TMOW pin functions as a TMOW output pin (Initial value) Rev.3.00 Jan. 10, 2007 page 242 of 1038 REJ09B0328-0300 Section 11 I/O Port Bit 6P16/IC Pin Switching (PMR16): PMR16 sets whether the P16/IC pin as a P16 I/O pin or an IC pin for the input capture input of the prescalar unit. The IC pin has a built-in noise cancel circuit. See section 22, Prescalar Unit. Bit 6 PMR16 0 1 Description The P16/IC pin functions as a P16 I/O pin The P16/IC pin functions as an IC input pin (Initial value) Bits 5 to 0P15/IRQ5 to P10/IRQ0 Pin Switching (PMR15 to PMR10): PMR15 to PMR10 set whether the P1n/IRQn pin is used as a P1n I/O pin or an IRQn pin for the external interrupt request input. Bit n PMR1n 0 1 Description The P1n/IRQn pin functions as a P1n I/O pin The P1n/IRQn pin functions as an IRQn input pin (Initial value) Note: n = 5 to 0 (2) Port Control Register 1 (PCR1) Bit : Initial value : R/W : 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W Port control register 1 (PCR1) controls the I/Os of pins P17 to P10 of port 1 in a unit of bit. When PCR1 is set to 1, the corresponding P17 to P10 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of PCR1 and PDR1 become valid. PCR1 is an 8-bit write-only register. When PCR1 is read, 1 is read. When reset, PCR1 is initialized to H'00. Bit n PCR1n 0 1 Description The P1n pin functions as an input pin The P1n pin functions as an output pin (Initial value) Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 243 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) Port Data Register 1 (PDR1) Bit : Initial value : R/W : 7 PDR17 0 R/W 6 PDR16 0 R/W 5 PDR15 0 R/W 4 PDR14 0 R/W 3 PDR13 0 R/W 2 PDR12 0 R/W 1 PDR11 0 R/W 0 PDR10 0 R/W Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1 (output), the PDR1 values are directly read if port 1 is read. Accordingly, the pin states are not affected. When PCR1 is 0 (input), the pin states are read if port 1 is read. PDR1 is an 8-bit read/ write enable register. When reset, PDR1 is initialized to H'00. (4) MOS Pull-Up Select Register 1 (PUR1) Bit : Initial value : R/W : 7 PUR17 0 R/W 6 PUR16 0 R/W 5 PUR15 0 R/W 4 PUR14 0 R/W 3 PUR13 0 R/W 2 PUR12 0 R/W 1 PUR11 0 R/W 0 PUR10 0 R/W MOS pull-up selector register 1 (PUR1) controls the on and off of the MOS pull-up transistor of port 1. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. When the corresponding bit of PCR1 is set to 1 (output), the corresponding bit of PUR1 becomes invalid and the MOS pull-up transistor is turned off. PUR1 is an 8-bit read/ write enable register. When reset, PUR1 is initialized to H'00. Bit n PUR1n 0 1 Note: Description The P1n pin has no MOS pull-up transistor The P1n pin has a MOS pull-up pin n = 7 to 0 (Initial value) Rev.3.00 Jan. 10, 2007 page 244 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.3.3 Pin Functions This section describes the port 1 pin functions and their selection methods. (1) P17/TMOW P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and the PCR17 bit in PCR1. PMR17 0 PCR17 0 1 1 * Pin Function P17 input pin P17 output pin TMOW output pin (2) P16/IC P16/IC is switched as shown below according to the PMR16 bit in PMR1, the NC on/off bit in prescalar unit control/status register (PCSR), and the PCR16 bit in PCR1. PMR16 0 PCR16 0 1 1 * 0 1 NC on/off * Pin Function P16 input pin P16 output pin IC input pin Noise cancel invalid Noise cancel valid (3) P15/IRQ5 to P10/IRQ0 P15/IRQ15 to P10/IRQ0 are switched as shown below according to the PMR1n bit in PMR1 and the PCR1n bit in PCR1. PMR1n 0 PCR1n 0 1 1 * Pin Function P1n input pin P1n output pin IRQn input pin Legend: * Don't care. Notes: 1. n = 5 to 0 2. The IRQ5 to IRQ0 input pins can select the leading or falling edge as an edge sense (the IRQ0 pin can select both edges). See section 6.2.4, IRQ Edge Select Register (IEGR). 3. IRQ1 or IRQ2 can be used as a timer J event input and IRQ3 can be used as a timer R input capture input. For details, see section 14, Timer J or section 16, Timer R. Rev.3.00 Jan. 10, 2007 page 245 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.3.4 Pin States Table 11.7 shows the port 1 pin states in each operation mode. Table 11.7 Port 1 Pin States Pins Reset Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Subsleep Operation Holding P17/TMOW Highimpedance P16/IC P15/IRQ5 to P10/IRQ0 Note: If the IC input pin and IRQ5 to IRQ0 input pins are set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev.3.00 Jan. 10, 2007 page 246 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.4 11.4.1 Port 2 Overview Port 2 is an 8-bit I/O port. Table 11.8 shows the port 2 configuration. Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O 2 (SCK1, SCK2), receive data input (SI1, SI2), send data output (SO1, SO2), I C bus interface clock I/O (SCL), or data I/O (SCL). It is switched by port mode register 2 (PRM2), serial mode register 2 (SMR), serial control register 2 (SCR), I C bus control register (ICCR), and port control register (PCR2). Port 2 can select the MOS pull-up function. Table 11.8 Port 2 Configuration Port Port 2 Function P27 (standard I/O port) P26 (standard I/O port) P25 (standard I/O port) P24 (standard I/O port) P23 (standard I/O port) P22 (standard I/O port) P21 (standard I/O port) P20 (standard I/O port) Alternative Function SCK2 (SCI2 clock I/O) SO2 (SCI2 transmit data output) SI2 (SCI2 receive data input) SCL (I C bus interface clock I/O) SDA (I C bus interface data I/O) SCK1 (SCI1 clock I/O) SO1 (SCI1 transmit data output) SI1 (SCI1 receive data input) 2 2 11.4.2 Register Configuration Table 11.9 shows the port 2 register configuration. Table 11.9 Port 2 Register Configuration Name Port mode register 2 Port control register 2 Port data register 2 Abbrev. PMR2 PCR2 PDR2 R/W R/W W R/W R/W Size Byte Byte Byte Byte Initial Value Address* H'1E H'00 H'00 H'00 H'FFCF H'FFD2 H'FFC2 H'FFE2 MOS pull-up select register PUR2 2 Note: * Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 247 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 2 (PMR2) Bit : Initial value : R/W : 7 PMR27 0 R/W 6 PMR26 0 R/W 5 PMR25 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PMR20 0 R/W Port mode register 2 (PMR2) controls switching of each pin function of port 2. The switching is specified in a unit of bit. The switching of the P22/SCK1, P21/SO1, and P20/SI1 pin functions is controlled by SMR and SCR. See section 23, Serial Communication Interface 1 (SCI1). PMR2 is an 8-bit read/write enable register. When reset, PMR2 is initialized to H'1E. If the SCK1, SCK2, SI1, and SI2 input pins are set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level Bit 7P27/SCK2 Pin Switching (PMR27): PMR27 sets whether the P27/SCK2 pin is used as a P27 I/O pin or an SKC2 pin for the SCI2 clock I/O. Bit 7 PMR27 0 1 Description The P27/SCK2 pin functions as a P27 I/O pin The P27/SCK2 pin functions as an SCK2 I/O pin (Initial value) Bit 6P26/SO2 Pin Switching (PMR26): PMR26 sets whether the P26/SO2 pin as a P26 I/O pin or an SO2 pin for the SCI2 send data output. Bit 6 PMR26 0 1 Description The P26/SO2 pin functions as a P26 I/O pin The P26/SO2 pin functions as an SO2 output pin (Initial value) Rev.3.00 Jan. 10, 2007 page 248 of 1038 REJ09B0328-0300 Section 11 I/O Port Bit 5P25/SI2 Pin Switching (PMR25): PMR26 sets whether the P25/SI2 pin as a P25 I/O pin or an SI2 pin for the SCI2 receive data input. Bit 5 PMR25 0 1 Description The P25/SI2 pin functions as a P25 I/O pin The P25/SI2 pin functions as an SI2 input pin (Initial value) Bits 4 to 1Reserved: When the bits are read, 1 is always read. The write operation is invalid. Bit 0P26/SO2 Pin PMOS Control (PMR20): PMR20 controls the PMOS ON and OFF of the P26/SO2 pin output buffer. Bit 0 PMR20 0 1 Description The P26/SO2 pin functions as CMOS output The P26/SO2 pin functions as NMOS open drain output (Initial value) (2) Port Control Register 2 (PCR2) Bit : Initial value : R/W : 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W Port control register 2 (PCR2) controls the I/Os of pins P27 to P20 of port 2 in a unit of bit. When PCR2 is set to 1, the corresponding P27 to P20 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of PCR2 and PDR2 are valid. PCR2 is an 8-bit write-only register. When PCR2 is read, 1 is read. When reset, PCR2 is initialized to H'00. Bit n PCR2n 0 1 Note: Description The P2n pin functions as an input pin The P2n pin functions as an output pin n = 7 to 0 (Initial value) Rev.3.00 Jan. 10, 2007 page 249 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) Port Data Register 2 (PDR2) Bit : Initial value : R/W : 7 PDR27 0 R/W 6 PDR26 0 R/W 5 PDR25 0 R/W 4 PDR24 0 R/W 3 PDR23 0 R/W 2 PDR22 0 R/W 1 PDR21 0 R/W 0 PDR20 0 R/W Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1 (output), the PDR2 values are directly read if port 2 is read. Accordingly, the pin states are not affected. When PCR2 is 0 (input), the pin states are read if port 2 is read. PDR2 is an 8-bit read/write enable register. When reset, PDR2 is initialized to H'00. (4) MOS Pull-Up Select Register 2 (PUR2) Bit : Initial value : R/W : 7 PUR27 0 R/W 6 PUR26 0 R/W 5 PUR25 0 R/W 4 PUR24 0 R/W 3 PUR23 0 R/W 2 PUR22 0 R/W 1 PUR21 0 R/W 0 PUR20 0 R/W MOS pull-up selector register 2 (PUR2) controls the ON and OFF of the MOS pull-up transistor of port 2. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. If the corresponding bit of PCR2 is set to 1 (output), the corresponding bit of PUR2 becomes invalid and the MOS pull-up transistor is turned off. PUR2 is an 8-bit read/write enable register. When reset, PUR2 is initialized to H'00. Bit n PMR2n 0 1 Note: Description The P2n pin has no MOS pull-up transistor The P2n pin has a MOS pull-up transistor n = 7 to 0 (Initial value) Rev.3.00 Jan. 10, 2007 page 250 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.4.3 Pin Functions This section describes the port 2 pin functions and their selection methods. (1) P27/SCK2 P27/SCK2 is switched as shown below according to the PMR27 bit in PMR2, the PCR27 bit in PCR2, and the SCK2 to SCK0 bits in serial control register 2 (SCR2). PMR27 0 PCR27 0 1 1 * Other than 111 111 Legend: * Don't care. CKS2 to CKS0 * Pin Function P27 input pin P27 output pin SCK2 output pin SCK2 input pin (2) P26/SO2 P26/SO2 is switched as shown below according to the PMR26 bit in PMR2 and the PCR26 bit in PCR2. PMR26 0 PCR26 0 1 1 * Legend: * Don't care. Pin Function P26 input pin P26 output pin SO2 output pin (3) P25/SI2 P25/SI2 is switched as shown below according to the PMR25 bit in PMR2 and the PCR25 bit in PCR2. PMR25 0 PCR25 0 1 1 * Legend: * Don't care. Pin Function P25 input pin P25 output pin SI2 input pin Rev.3.00 Jan. 10, 2007 page 251 of 1038 REJ09B0328-0300 Section 11 I/O Port (4) P24/SCL P24/SCL2 is switched as shown below according to the ICE bit in the I C bus control register and the PCR24 bit in PCR2. ICE 0 PCR24 0 1 1 * Legend: * Don't care. Pin Function P24 input pin P24 output pin SCL I/O pin 2 (5) P23/SDA P23/SDA is switched as shown below according to the ICE bit in the I C bus control register and the PCR23 bit in PCR2. ICE 0 PCR23 0 1 1 * Legend: * Don't care. Pin Function P23 input pin P23 output pin SDA I/O pin 2 (6) P22/SCK1 P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/A bit in SMR, and the CKE1 and CKE0 bits in SCR. CKE1 0 C/A 0 CKE0 0 PCR22 0 1 1 1 1 * Legend: * Don't care. * SCK1 input pin * Pin Function P22 input pin P22 output pin SCK1 output pin Rev.3.00 Jan. 10, 2007 page 252 of 1038 REJ09B0328-0300 Section 11 I/O Port (7) P21/SO1 P21/SO1 is switched as shown below according to the PCR21 bit in PCR2 and the TE bit in SCR. TE 0 PCR21 0 1 1 * Legend: * Don't care. Pin Function P21 input pin P21 output pin SO1 output pin (8) P20/SI1 P20/SI1 is switched as shown below according to the PCR20 bit in PCR2 and the RE bit in SCR. RE 0 PCR20 0 1 1 * Legend: * Don't care. Pin Function P20 input pin P20 output pin SI1 input pin 11.4.4 Pin States Table 11.10 shows the port 2 pin states in each operation mode. Table 11.10 Port 2 Pin States Pins P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 Reset Highimpedance Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Operation Subsleep Holding Note: If the SCK1, SCK2, SI1, and SI2 input pins are set, the pin level needs be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev.3.00 Jan. 10, 2007 page 253 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.5 11.5.1 Port 3 Overview Port 3 is an 8-bit I/O port. Table 11.11 shows the port 3 configuration. Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer output (TMO), buzzer output (BUZZ), 8-bit PWN outputs (PWN3 to PWN0), SCI2 strobe output (STRB), or chip select input (CS). It is switched by port mode register 3 (PMR3) and port control register 3 (PCR3). Port 3 can select the MOS pull-up function. Table 11.11 Port 3 Configuration Port Port 3 Function P37 (standard I/O port) P36 (standard I/O port) P35 (standard I/O port) P34 (standard I/O port) P33 (standard I/O port) P32 (standard I/O port) P31 (standard I/O port) P30 (standard I/O port) Alternative Function TMO (timer J timer output) BUZZ (timer J buzzer output) PWM3 (8-bit PWM output) PWM2 (8-bit PWM output) PWM1 (8-bit PWM output) PWM0 (8-bit PWM output) STRB (SCI2 strobe output) CS (SCI2 chip select input) 11.5.2 Register Configuration Table 11.12 shows the port 3 register configuration. Table 11.12 Port 3 Register Configuration Name Port mode register 3 Port control register 3 Port data register 3 Abbrev. PMR3 PCR3 PDR3 R/W R/W W R/W R/W Size Byte Byte Byte Byte Initial Value Address* H'00 H'00 H'00 H'00 H'FFD0 H'FFD3 H'FFC3 H'FFE3 MOS pull-up select register PUR3 3 Note: * Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 254 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 3 (PMR3) Bit : Initial value : R/W : 7 PMR37 0 R/W 6 PMR36 0 R/W 5 PMR35 0 R/W 4 PMR34 0 R/W 3 PMR33 0 R/W 2 PMR32 0 R/W 1 PMR31 0 R/W 0 PMR30 0 R/W Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is specified in a unit of bit. PMR3 is an 8-bit read/write enable register. When reset, PMR3 is initialized to H'00. If the CS input pin is set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Bit 7P37/TMO Pin Switching (PMR37): PMR37 sets whether the P37/TMO pin is used as a P37 I/O pin or a TMO pin for the timer J output timer. Bit 7 PMR37 0 1 Description The P37/TMO pin functions as a P37 I/O pin The P37/TMO pin functions as a TMO output pin (Initial value) Note: If the TMO pin is used for remote control sending, a careless timer output pulse may be output when the remote control mode is set after the output has been switched to the TMO output. Perform the switching and setting in the following order. [1] Set the remote control mode. [2] Set the TMJ-1 and 2 counter data of the timer J. [3] Switch the P37/TMO pin to the TMO output pin. [4] Set the ST bit to 1. Bit 6P36/BUZZ Pin Switching (PMR36): PMR36 sets whether the P36/BUZZ pin as a P36 I/O pin or an BUZZ pin for the timer J buzzer output. For the selection of the BUZZ output, see section14.2.2, Timer J Control Register (TMJC). Bit 6 PMR36 0 1 Description The P36/BUZZ pin functions as a P36 I/O pin The P36/BUZZ pin functions as a BUZZ output pin (Initial value) Rev.3.00 Jan. 10, 2007 page 255 of 1038 REJ09B0328-0300 Section 11 I/O Port Bits 5 to 2P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): PMR35 to PMR32 set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM output. Bit n PMR3n 0 1 Note: Description The P3n/PWMm pin functions as a P3n I/O pin The P3n/PWMm pin functions as a PWMm output pin n = 5 to 2, m = 3 to 0 (Initial value) Bit 1P31/STRB Pin Switching (PMR31): PMR31 sets whether the P31/STRB pin is used as a P31 I/O pin or an STRB pin for the SCI2 strobe output. Bit 1 PMR31 0 1 Description The P31/STRB pin functions as a P31 I/O pin The P31/STRB pin functions as an STRB output pin (Initial value) Bit 0P30/CS Pin Switching (PMR30): PMR30 sets whether the P30/CS pin is used as a P30 I/O pin or a CS pin for the SCI2 chip select input. Bit 0 PMR30 0 1 Description The P30/CS pin functions as a P30 I/O pin The P30/CS pin functions as a CS input pin (Initial value) Rev.3.00 Jan. 10, 2007 page 256 of 1038 REJ09B0328-0300 Section 11 I/O Port (2) Port Control Register 3 (PCR3) Bit : Initial value : R/W : 7 PCR37 0 W 6 PCR36 0 W 5 PCR35 0 W 4 PCR34 0 W 3 PCR33 0 W 2 PCR32 0 W 1 PCR31 0 W 0 PCR30 0 W Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit. When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR3, settings of PCR3 and PDR3 become valid. PCR3 is an 8-bit write-only register. When PCR3 is read, 1 is read. When reset, PCR3 is initialized to H'00. Bit n PCR3n 0 1 Note: Description The P3n pin functions as an input pin The P3n pin functions as an output pin n = 7 to 0 (Initial value) (3) Port Data Register 3 (PDR3) Bit : Initial value : R/W : 7 PDR37 0 R/W 6 PDR36 0 R/W 5 PDR35 0 R/W 4 PDR34 0 R/W 3 PDR33 0 R/W 2 PDR32 0 R/W 1 PDR31 0 R/W 0 PDR30 0 R/W Port data register 3 (PDR3) stores the data for the pins P37 to P30 of port 3. When PCR3 is 1 (output), the PDR3 values are directly read if port 3 is read. Accordingly, the pin states are not affected. When PCR3 is 0 (input), the pin states are read if port 3 is read. PDR3 is an 8-bit read/write enable register. When reset, PDR3 is initialized to H'00. Rev.3.00 Jan. 10, 2007 page 257 of 1038 REJ09B0328-0300 Section 11 I/O Port (4) MOS Pull-Up Select Register 3 (PUR3) Bit : Initial value : R/W : 7 PUR37 0 R/W 6 PUR36 0 R/W 5 PUR35 0 R/W 4 PUR34 0 R/W 3 PUR33 0 R/W 2 PUR32 0 R/W 1 PUR31 0 R/W 0 PUR30 0 R/W MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If the corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid and the MOS pull-up transistor is turned off. PUR3 is an 8-bit read/write enable register. When reset, PUR3 is initialized to H'00. Bit n PCR3n 0 1 Note: Description The P3n pin has no MOS pull-up transistor The P3n pin has a MOS pull-up transistor n = 7 to 0 (Initial value) 11.5.3 Pin Functions This section describes the port 3 pin functions and their selection methods. (1) P37/TMO P37/TMO is switched as shown below according to the PMR37 bit in PMR3 and the PCR37 bit in PCR3. PMR37 0 PCR37 0 1 1 * Legend: * Don't care. Pin Function P37 input pin P37 output pin TMO output pin Rev.3.00 Jan. 10, 2007 page 258 of 1038 REJ09B0328-0300 Section 11 I/O Port (2) P36/BUZZ P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the PCR36 bit in PCR3. PMR36 0 PCR36 0 1 1 * Legend: * Don't care. Pin Function P36 input pin P36 output pin BUZZ output pin (3) P35/PWM3 to P32/PWM0 P35/PWM3 to P32/PWM0 are switched as shown below according to the PMR3n bit in PMR3 and the PCR3n bit in PCR3. PMR3n 0 PCR3n 0 1 1 * Pin Function P3n input pin P3n output pin PWMm output pin Legend: * Don't care. Note: n = 5 to 2, m = 3 to 0 (4) P31/STRB P31/STRB is switched as shown below according to the PMR31 bit in PMR3 and the PCR31 bit in PCR3. PMR31 0 PCR31 0 1 1 * Legend: * Don't care. Pin Function P31 input pin P31 output pin STRB output pin Rev.3.00 Jan. 10, 2007 page 259 of 1038 REJ09B0328-0300 Section 11 I/O Port (5) P30/CS P30/CS is switched as shown below according to the PMR30 bit in PMR3 and the PCR30 bit in PCR3. PMR30 0 PCR30 0 1 1 * Legend: * Don't care. Pin Function P30 input pin P30 output pin CS input pin 11.5.4 Pin States Table 11.13 shows the port 3 pin states in each operation mode. Table 11.13 Port 3 Pin States Pins Reset Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Subsleep Operation Holding HighP37/TMO impedance P36/BUZZ P35/PWM3 to P32/PWM0 P31/STRB P30/CS Note: If the CS input pin is set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev.3.00 Jan. 10, 2007 page 260 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.6 11.6.1 Port 4 Overview Port 4 is an 8-bit I/O port. Table 11.14 shows the port 4 configuration. Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output (PWM14). It is switched by port mode register 4 (PRM4), timer output compare control register (TOCR), and port control register 4 (PCR4). Table 11.14 Port 4 Configuration Port Port 4 Function P47 (standard I/O port) P46 (standard I/O port) P45 (standard I/O port) P44 (standard I/O port) P43 (standard I/O port) P42 (standard I/O port) P41 (standard I/O port) P40 (standard I/O port) Alternative Function None FTOB (timer X1 output compare output) FTOA (timer X1 output compare output) FTID (timer X1 input capture input) FTIC (timer X1 input capture input) FTIB (timer X1 input capture input) FTIA (timer X1 input capture input) PWM14 (14-bit PWM output) 11.6.2 Register Configuration Table 11.15 shows the port 4 register configuration. Table 11.15 Port 4 Register Configuration Name Port mode register 4 Port control register 4 Port data register 4 Note: * Abbrev. PMR4 PCR4 PDR4 R/W R/W W R/W Size Byte Byte Byte Initial Value Address* H'FE H'00 H'00 H'FFDB H'FFD4 H'FFC4 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 261 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 4 (PMR4) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PMR40 0 R/W Port mode register 4 (PMR4) controls switching of the P40/PWM14 pin function. The switchings of the P46/FTOB and P45/FTOA functions are controlled by TOCR. See section 17, Timer X1. The FTIA, FTIB, FTIC, and FTID inputs always function. PMR4 is an 8-bit read/write enable register. When reset, PMR4 is initialized to H'FE. Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level (excluding reset, standby, and watch modes). Because the FTIA, FTIB, FTIC, and FTID inputs always function, each input uses the input edge to the alternative general I/O pins P44, P43, P42, and P41 as input signals. Bits 7 to 1Reserved: When the bits are read, 1 is always read. The write operation is invalid. Bit 0P40/PWM14 Pin Switching (PMR40): PMR40 sets whether the P40/PWM pin is used as a P40 I/O pin or a PWM14 pin for the 14-bit PWM square wave output. Bit 0 PMR40 0 1 Description The P40/PWM14 pin functions as a P40 I/O pin The P40/PWM14 pin functions as a PWM14 output pin (Initial value) Rev.3.00 Jan. 10, 2007 page 262 of 1038 REJ09B0328-0300 Section 11 I/O Port (2) Port Control Register 4 (PCR4) Bit : Initial value : R/W : 7 PCR47 0 W 6 PCR46 0 W 5 PCR45 0 W 4 PCR44 0 W 3 PCR43 0 W 2 PCR42 0 W 1 PCR41 0 W 0 PCR40 0 W Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit. When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR4, settings of PCR4 and PDR4 become valid. PCR4 is an 8-bit write-only register. When PCR4 is read, 1 is read. When reset, PCR4 is initialized to H'00. Bit n PCR4n 0 1 Note: Description The P4n pin functions as an input pin The P4n pin functions as an output pin n = 7 to 0 (Initial value) (3) Port Data Register 4 (PDR4) Bit : Initial value : R/W : 7 PDR47 0 R/W 6 PDR46 0 R/W 5 PDR45 0 R/W 4 PDR44 0 R/W 3 PDR43 0 R/W 2 PDR42 0 R/W 1 PDR41 0 R/W 0 PDR40 0 R/W Port data register 4 (PDR4) stores the data for the pins P47 to P40 of port 4. When PCR4 is 1 (output), the PDR4 values are directly read if port 3 is read. Accordingly, the pin states are not affected. When PCR4 is 0 (input), the pin states are read if port 4 is read. PDR4 is an 8-bit read/write enable register. When reset, PDR4 is initialized to H'00. 11.6.3 Pin Functions This section describes the port 4 pin functions and their selection methods. (1) P47/FTCI P47/FTCI is switched as shown below according to the PCR47 bit in PCR4. PCR47 0 1 Pin Function P47 input pin P47 output pin Rev.3.00 Jan. 10, 2007 page 263 of 1038 REJ09B0328-0300 Section 11 I/O Port (2) P46/FTOB P46/FTOB is switched as shown below according to the PCR46 bit in PCR4 and the OEB bit in TOCR. OEB 0 PCR46 0 1 1 * Legend: * Don't care. Pin Function P46 input pin P46 output pin FTOB output pin (3) P45/FTOA P45/FTOA is switched as shown below according to the PCR45 bit in PCR4 and the OEA bit in TOCR. OEA 0 PCR45 0 1 1 * Legend: * Don't care. Pin Function P45 input pin P45 output pin FTOA output pin (4) P44/FTID P44/FTID is switched as shown below according to the PCR44 bit in PCR4. PCR44 0 1 Pin Function P44 input pin P44 output pin FTID input pin (5) P43/FTIC P43/FTIC is switched as shown below according to the PCR43 bit in PCR4. PCR43 0 1 Pin Function P43 input pin P43 output pin FTIC input pin Rev.3.00 Jan. 10, 2007 page 264 of 1038 REJ09B0328-0300 Section 11 I/O Port (6) P42/FTIB P42/FTIB is switched as shown below according to the PCR42 bit in PCR4. PCR42 0 1 Pin Function P42 input pin P42 output pin FTIB input pin (7) P41/FTIA P41/FTIA is switched as shown below according to the PCR41 bit in PCR4. PCR41 0 1 Pin Function P41 input pin P41 output pin FTIA input pin (8) P40/PWM14 P40/PWM14 is switched as shown below according to the PMR40 bit in PMR4 and the PCR40 bit in PCR4. PMR40 0 PCR40 0 1 1 * Legend: * Don't care. Pin Function P40 input pin P40 output pin PWM14 input pin Rev.3.00 Jan. 10, 2007 page 265 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.6.4 Pin States Table 11.16 shows the port 4 pin states in each operation mode. Table 11.16 Port 4 Pin States Pins Reset Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Subsleep Operation Holding HighP47 impedance P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/PWM14 Note: Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level (excluding reset, standby, and watch modes). Rev.3.00 Jan. 10, 2007 page 266 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.7 11.7.1 Port 5 Overview Port 5 is a 4-bit I/O port. Table 11.17 shows the port 5 configuration. Port 5 consists of pins that are used both as standard I/O ports (P53 to P50) and realtime output port trigger input (TRIG), timer B event input (TMBI), or A/D conversion start external trigger input (ADTRG). It is switched by port mode register 5 (PMR5), A/D trigger select register (ADTSR), and port control register 5 (PCR5). Table 11.17 Port 5 Configuration Port Port 5 Function P53 (standard I/O port) P52 (standard I/O port) P51 (standard I/O port) P50 (standard I/O port) Alternative Function TRIG (realtime output port trigger input) TMBI (timer B event input) None ADTRG (A/D conversion start external trigger input) 11.7.2 Register Configuration Table 11.18 shows the port 5 register configuration. Table 11.18 Port 5 Register Configuration Name Port mode register 5 Port control register 5 Port data register 5 Note: * Abbrev. PMR5 PCR5 PDR5 R/W R/W W R/W Size Byte Byte Byte Initial Value H'F1 H'F0 H'F0 Address* H'FFDC H'FFD5 H'FFC5 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 267 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 5 (PMR5) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PMR53 0 R/W 2 PMR52 0 R/W 1 PMR51 0 R/W 0 -- 1 -- Port mode register 5 (PMR5) controls switching of each pin function of port 5 and specifies the edge sense of the timer B event input (TMBI). The switching of the P50/ADTRG pin function is controlled by ADTSR. See section 26, A/D Converter. PMR5 is an 8-bit read/write enable register. When reset, PMR5 is initialized to H'F1. If the TRIG, TMBI, and ADTRG pin pins are set, the alternative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Bits 7 to 4Reserved: When the bits are read, 1 is always read. The write operation is invalid. Bit 3P53/TRIG Pin Switching (PMR53): PMR53 sets whether the P53/TRIG pin is used as a P53 I/O pin or a TRIG pin for the realtime output port trigger input. Bit 3 PMR53 0 1 Description The P53/TRIG pin functions as a P53 I/O pin The P53/TRIG pin functions as a TRIG input pin (Initial value) Bit 2P52/TMBI Pin Switching (PMR52): PMR52 sets whether the P52/TMBI pin is used as a P52 I/O pin or a TMBI pin for the timer B event input. Bit 2 PMR52 0 1 Description The P52/TMBI pin functions as a P52 I/O pin The P52/TMBI pin functions as a TMBI input pin (Initial value) Rev.3.00 Jan. 10, 2007 page 268 of 1038 REJ09B0328-0300 Section 11 I/O Port Bit 1Timer B event Input Edge Select (PMR51): PMR51 selects the input edge sense of the TMBI pin. Bit 1 PMR51 0 1 Description The timer B event input detects the falling edge The timer B event input detects the rising edge (Initial value) Bit 0Reserved When the bit is read, 1 is always read. The write operation is invalid. (2) Port Control Register 5 (PCR5) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W Port control register 5 (PCR5) controls the I/Os of pins P53 to P50 of port 5 in a unit of bit. When PCR5 is set to 1, the corresponding P53 to P50 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O, settings of PCR5 and PDR5 are valid. PCR5 is an 8-bit write-only register. When PCR5 is read, 1 is read. When reset, PCR5 is initialized to H'F0. Bits 7 to 4 are reserved bits. Bit n PCR5n 0 1 Note: Description The P5n pin functions as an input pin The P5n pin functions as an output pin n = 3 to 0 (Initial value) Rev.3.00 Jan. 10, 2007 page 269 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) Port Data Register 5 (PDR5) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PDR53 0 R/W 2 PDR52 0 R/W 1 PDR51 0 R/W 0 PDR50 0 R/W Port data register 5 (PDR5) stores the data for the pins P53 to P50 of port 5. When PCR5 is 1 (output), the PDR5 values are directly read if port 5 is read. Accordingly, the pin states are not affected. When PCR5 is 0 (input), the pin states are read if port 5 is read. PDR5 is an 8-bit read/write enable register. When reset, PDR5 is initialized to H'F0. Bits 7 to 4 are reserved bits. 11.7.3 Pin Functions This section describes the port 5 pin functions and their selection methods. (1) P53/TRIG P53/TRIG is switched as shown below according to the PMR53 bit in PMR5 and the PCR53 bit in PCR5. PMR53 0 PCR53 0 1 1 * Legend: * Don't care. Pin Function P53 input pin P53 output pin TRIG input pin (2) P52/TMBI P52/TMBI is switched as shown below according to the PMR52 bit in PMR5 and the PCR52 bit in PCR5. PMR52 0 PCR52 0 1 1 * Legend: * Don't care. Pin Function P52 input pin P52 output pin TMBI input pin Rev.3.00 Jan. 10, 2007 page 270 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) P51 P51 is switched as shown below according to the PCR51 bit in PCR5. PCR51 0 1 Pin Function P51 input pin P51 output pin (4) P50/ADTRG P50/ADTRG is switched as shown below according to the PCR50 bit in PCR5 and the TRGS1 and TRG0 bits in ADTSR. TRGS1, TRGS0 Other than 11 11 PCR31 0 1 * Pin Function P50 input pin P50 output pin ADTRG input pin Legend: * Don't care. 11.7.4 Pin States Table 11.19 shows the port 5 pin states in each operation mode. Table 11.19 Port 3 Pin States Pins Reset Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Subsleep Operation Holding HighP53/TRIG impedance P52/TMBI P51 P50/ADRTG Note: If the TRIG, TMBI, and ADTRG input pins are set, the alternative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev.3.00 Jan. 10, 2007 page 271 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.8 11.8.1 Port 6 Overview Port 6 is an 8-bit I/O port. Table 11.20 shows the port 6 configuration. Port 6 consists of pins that are used both as standard I/O ports (P67 to P60) and realtime output ports (RP7 to RP0). It is switched by port mode register 6 (PMR6) and port control register 6 (PCR6). The realtime output function can instantaneously switch the output data by an external or internal trigger input. Table 11.20 Port 6 Configuration Port Port 6 Function P67 (standard I/O port) P66 (standard I/O port) P65 (standard I/O port) P64 (standard I/O port) P63 (standard I/O port) P62 (standard I/O port) P61 (standard I/O port) P60 (standard I/O port) Alternative Function RP7 (realtime output port pin) RP6 (realtime output port pin) RP5 (realtime output port pin) RP4 (realtime output port pin) RP3 (realtime output port pin) RP2 (realtime output port pin) RP1 (realtime output port pin) RP0 (realtime output port pin) Rev.3.00 Jan. 10, 2007 page 272 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.8.2 Register Configuration Table 11.21 shows the port 6 register configuration. Table 11.21 Port 6 Register Configuration Name Port mode register 6 Port control register 6 Port data register 6 Realtime output trigger select register Realtime output trigger edge select register Abbrev. PMR6 PCR6 PDR6 RTPSR RTPEGR R/W R/W W R/W R/W R/W Size Byte Byte Byte Byte Byte Byte Byte Initial Value Address* H'00 H'00 H'00 H'00 H'FC H'00 H'00 H'FFDD H'FFD6 H'FFC6 H'FFE5 H'FFE4 Port control register slave 6 PCRS6 Port data register slave 6 Note: * PDRS6 Lower 16 bits of the address. (1) Port Mode Register 6 (PMR6) Bit : Initial value : R/W : 7 PMR67 0 R/W 6 PMR66 0 R/W 5 PMR65 0 R/W 4 PMR64 0 R/W 3 PMR63 0 R/W 2 PMR62 0 R/W 1 PMR61 0 R/W 0 PMR60 0 R/W Port mode register 6 (PMR6) controls switching of each pin function of port 6. The switching is specified in units of bits. PMR6 is an 8-bit read/write enable register. When reset, PMR6 is initialized to H'00. Bits 7 to 0P67/RP7 to P60/RP0 Pin Switching (PMR67 to PMR60): PMR67 to PMR60 set whether the P6n/RPn pin is used as a P6n I/O pin or an RPn pin for the realtime output port. Bit n PMR6n 0 1 Note: Description The P6n/RPn pin functions as a P6n I/O pin The P6n/RPn pin functions as an RPn output pin n = 7 to 0 (Initial value) Rev.3.00 Jan. 10, 2007 page 273 of 1038 REJ09B0328-0300 Section 11 I/O Port (2) Port Control Register 6 (PCR6) Bit : Initial value : R/W : 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output in a unit of bit together with PMR6. When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to 1, and they become general input pins if it is set to 0. When PMR6 = 1, PCR6 controls the corresponding RP7 to RP0 realtime output pins. For details, see section 11.8.4, Operation. PCR6 is an 8-bit write-only register. When PCR6 is read, 1 is read. When reset, PCR6 is initialized to H'00. PMR6 Bit n PMR6n 0 PCR6 Bit n PCR6n 0 1 1 * Legend: * Don't care. Note: n = 7 to 0 Description The P6n/RPn pin functions as a P6n general I/O input pin (Initial value) The P6n/RPn pin functions as a P6n general output pin The P6n/RPn pin functions as an RPn realtime output pin (3) Port Data Register 6 (PDR6) Bit : Initial value : R/W : 7 PDR67 0 R/W 6 PDR66 0 R/W 5 PDR65 0 R/W 4 PDR64 0 R/W 3 PDR63 0 R/W 2 PDR62 0 R/W 1 PDR61 0 R/W 0 PDR60 0 R/W Port data register 6 (PDR6) stores the data for the pins P67 to P60 of port 6. For PMR6 = 0, when PCR6 is 1 (output), the PDR6 values are directly read if port 6 is read. Accordingly, the pin states are not affected. When PCR6 is 0 (input), the pin states are read if port 6 is read. For PMR6 = 1, port 6 becomes a realtime output pin. For details, see section 11.8.4, Operation. PDR6 is an 8-bit read/write enable register. When reset, PDR6 is initialized to H'00. Rev.3.00 Jan. 10, 2007 page 274 of 1038 REJ09B0328-0300 Section 11 I/O Port (4) Realtime Output Trigger Select Register (RTPSR) Bit : Initial value : R/W : 7 RTPSR7 0 R/W 6 RTPSR6 0 R/W 5 RTPSR5 0 R/W 4 RTPSR4 0 R/W 3 RTPSR3 0 R/W 2 RTPSR2 0 R/W 1 RTPSR1 0 R/W 0 RTPSR0 0 R/W The realtime output trigger select register (RTPSR) sets whether the external trigger (TRIG pin input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of bit. For the internal trigger HSW, see section 28.4, HSW (Head-Switch) Timing Generator. RTPSR is an 8-bit read/write enable register. When reset, RTPSR is initialized to H'00. Bit n RTPSRn 0 1 Note: Description Selects the external trigger (TRIG pin input) as a trigger input Selects the internal trigger (HSW) a trigger input n = 7 to 0 (Initial value) (5) Real Time Output Trigger Edge Select Register (RTPEGR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 0 RTPEGR1 RTPEGR0 0 R/W 0 R/W The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external or internal trigger input for the realtime output. RTPEGR is an 8-bit read/write enable register. When reset, RTPEGR is initialized to H'FC. Bits 7 to 2Reserved: When the bits are read, 1 is always read. The write operation is invalid. Bits 1 and 0Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0): RTPEGR1 and RTPEGR0 select the edge sense of the external or internal trigger input for the realtime output. Bit 1 RTPEGR1 0 Bit 0 RTPEGR0 0 1 1 0 1 Description Inhibits a trigger input Selects the rising edge of a trigger input Selects the falling edge of a trigger input Selects both the leading and falling edges of a trigger input (Initial value) Rev.3.00 Jan. 10, 2007 page 275 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.8.3 Pin Functions This section describes the port 6 pin functions and their selection methods. (1) P67/RP7 to P60/RP0 P67/RP7 to P60/RP0 are switched as shown below according to the PMR6n bit in PMR6 and the PCR6n bit in PCR6. PMR6n 0 PCR6n 0 1 1 0 1 Pin Function P6n input pin P6n output pin RPn output pin Output Value PDR6n High-impedance* PDRS6n* Value When PDR6n was read P6n pin PDR6n Notes: n = 7 to 0 * When PMR6n = 1 (realtime output pin), indicates the state after the PCR6n setup value has been transferred to PCRS6n by a trigger input. Rev.3.00 Jan. 10, 2007 page 276 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.8.4 Operation Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6 functions as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The operation per port 6 function is shown below. (See figure 11.2.) Internal trigger HSW External trigger TRIG Selection circuit RTPEGR write CK RTPEGR RTPSR write CK RTPSR RMR6 write Internal data bus CK RMR6 RDR6 write CK CK RDR6 RDR6 read Selection circuit RCR6 write CK RDRS6 P6/RP CK RCR6 RCRS6 Legend: PMR6 PCR6 PDR6 : Port mode register 6 : Port control register 6 : Port data register 6 RTPSR : Realtime output trigger select register RTPEGR : Realtime output trigger edge select register HSW TRIG : Internal trigger signal : External trigger pin PCRS6 : Port control register slave 6 PDRS6 : Port data register slave 6 Figure 11.2 Port 6 Function Block Diagram Rev.3.00 Jan. 10, 2007 page 277 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Operation of the realtime output port (PMR6 = 1) When PMR6 is 1, it operates as a realtime output port. When a trigger is input, PMR6 transfers the PDR6 data to PDRS6 and the PCR6 data to PCRS6, respectively. In this case, when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin. When PCRS6 is 0, the RP pin of the corresponding bit is output to the high-impedance state. In other words, the pin output state (High or Low) or high-impedance state can instantaneously be switched by a trigger input. Adversely, when PDR6 is read, the PDR6 values are read regardless of the PCR6 and PCRS6 values. (2) Operation of the general I/O port (PMR6 = 0) When PMR6 is 0, it operates as a general I/O port. When data is written to PDR6, the same data is also written to PDRS6. Accordingly, because both PDR6 and PDRS6 and both PCR6 and PCRS6 can be handled as one register, respectively, they can be used in the same way as a normal general I/O port. In other words, if PCR6 is 1, the PDR6 data of the corresponding bit is output to the P6 pin. If PCR6 is 0, the P6 pin of the corresponding bit becomes an input. Adversely, assuming that PDR6 is read, the PDR6 values are read when PCR6 is 1 and the pin values are read when PCR6 is 0. 11.8.5 Pin States Table 11.22 shows the port 6 pin states in each operation mode. Table 11.22 Port 6 Pin States Pins P67/RP7 to P60/RP0 Reset Highimpedance Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Operation Subsleep Holding Rev.3.00 Jan. 10, 2007 page 278 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.9 11.9.1 Port 7 Overview Port 7 is an 8-bit I/O port. Table 11.23 shows the port 7 configuration. Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0). It is switched by port mode register 7 (PMR7) and port control register 7 (PCR7). For the programmable generator (PPG), see section 28.4, HSW (Head-Switch) Timing Generator. Table 11.23 Port 7 Configuration Port Port 7 Function P77 (standard I/O port) P76 (standard I/O port) P75 (standard I/O port) P74 (standard I/O port) P73 (standard I/O port) P72 (standard I/O port) P71 (standard I/O port) P70 (standard I/O port) Alternative Function PPG7 (HSW timing output) PPG6 (HSW timing output) PPG5 (HSW timing output) PPG4 (HSW timing output) PPG3 (HSW timing output) PPG2 (HSW timing output) PPG1 (HSW timing output) PPG0 (HSW timing output) 11.9.2 Register Configuration Table 11.24 shows the port 7 register configuration. Table 11.24 Port 7 Register Configuration Name Port mode register 7 Port control register 7 Port control register 7 Note: * Abbrev. PMR7 PCR7 PDR7 R/W R/W W R/W Size Byte Byte Byte Initial Value H'00 H'00 H'00 Address* H'FFDE H'FFD7 H'FFC7 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 279 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 7 (PMR7) Bit : Initial value : R/W : 7 PMR77 0 R/W 6 PMR76 0 R/W 5 PMR75 0 R/W 4 PMR74 0 R/W 3 PMR73 0 R/W 2 PMR72 0 R/W 1 PMR71 0 R/W 0 PMR70 0 R/W Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is specified in a unit of bit. PMR7 is an 8-bit read/write enable register. When reset, PMR7 is initialized to H'00. Bits 7 to 0: P77/PPG7 to P70/PPG0 Pin Switching (PMR77 to PMR70) PMR77 to PMR70 set whether the P7n/PPGn pin is used as a P7n I/O pin or a PPGn pin for the HSW timing generation circuit output. Bit n PMR7n 0 1 Note: Description The P7n/PPGn pin functions as a P7n I/O pin The P7n/PPGn pin functions as a PPGn output pin n = 7 to 0 (Initial value) (2) Port Control Register 7 (PCR7) Bit : Initial value : R/W : 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 PCR72 0 W 1 PCR71 0 W 0 PCR70 0 W Port control register 7 (PCR7) controls the I/Os of pins P77 to P70 of port 7 in a unit of bit. When PCR7 is set to 1, the corresponding P77 to P70 pins become output pins, and when it is set to 0, they become input pins. When the corresponding pin is set to the general I/O by PMR7, settings of PCR7 and PDR7 become valid. PCR7 is an 8-bit write-only register. When PCR7 is read, 1 is read. When reset, PCR7 is initialized to H'00. Bit n PCR7n 0 1 Note: Description The P7n pin functions as an input pin The P7n pin functions as an output pin n = 7 to 0 (Initial value) Rev.3.00 Jan. 10, 2007 page 280 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) Port Data Register 7 (PDR7) Bit : Initial value : R/W : 7 PDR77 0 R/W 6 PDR76 0 R/W 5 PDR75 0 R/W 4 PDR74 0 R/W 3 PDR73 0 R/W 2 PDR72 0 R/W 1 PDR71 0 R/W 0 PDR70 0 R/W Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7. When PCR7 is 1 (output), the PDR7 values are directly read if port 7 is read. Accordingly, the pin states are not affected. When PCR7 is 0 (input), the pin states are read if port 7 is read. PDR7 is an 8-bit read/write enable register. When reset, PDR7 is initialized to H'00. 11.9.3 Pin Functions This section describes the port 7 pin functions and their selection methods. (1) P77/PPG7 to P70/PPG0 P77/PPG7 to P70/PPG0 are switched as shown below according to the PMR7n bit in PMR7 and the PCR7n bit in PCR7. PMR7n 0 PCR7n 0 1 1 * Legend: * Don't care. Note: n = 7 to 0 Pin Function P7n input pin P7n output pin PPGn input pin 11.9.4 Pin States Table 11.25 shows the port 7 pin states in each operation mode. Table 11.25 Port 7 Pin States Pins Reset Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Operation Subsleep Holding P77/PPG7 to HighP70/PPG0 impedance Rev.3.00 Jan. 10, 2007 page 281 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.10 Port 8 11.10.1 Overview Port 8 is an 8-bit I/O port. Table 11.26 shows the port 8 configuration. Port 8 is a CMOS high-current I/O port. The sink current is 20 mA max. (VOL = 1.5 V) and up to four pins can simultaneously be set on. Port 8 consists of pins that are used both as high-current I/O ports (P87 to P80) and servo monitor output (SV1, SV2), capstan external synchronous signal input (EXCAP), or external trigger signal input (EXTTRG). It is switched by port mode register 8 (PMR8) and port control register 8 (PCR8). Table 11.26 Port 8 Configuration Port Port 8 Function P87 (high-current I/O port) P86 (high-current I/O port) P85 (high-current I/O port) P84 (high-current I/O port) P83 (high-current I/O port) P82 (high-current I/O port) P81 (high-current I/O port) P80 (high-current I/O port) Alternative Function None None None None SV2 (servo monitor output) SV1 (servo monitor output) EXCAP (capstan external synchronous signal input) EXTTRG (external trigger signal input) 11.10.2 Register Configuration Table 11.27 shows the port 8 register configuration. Table 11.27 Port 8 Register Configuration Name Port mode register 8 Port control register 8 Port data register 8 Note: * Abbrev. PMR8 PCR8 PDR8 R/W R/W W R/W Size Byte Byte Byte Initial Value H'F0 H'00 H'00 Address* H'FFDF H'FFD8 H'FFC8 The address indicates the low-order 16 bits. Rev.3.00 Jan. 10, 2007 page 282 of 1038 REJ09B0328-0300 Section 11 I/O Port (1) Port Mode Register 8 (PMR8) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PMR83 0 R/W 2 PMR82 0 R/W 1 PMR81 0 R/W 0 PMR80 0 R/W Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is specified in a unit of bit. PMR8 is an 8-bit read/write enable register. When reset, PMR8 is initialized to H'F0. If the EXCAP and EXTTRG input pins are set, the pin level need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Bits 7 to 4Reserved: When the bits are read, 1 is always read. The write operation is valid. Bit 3P83/SV2 Pin Switching (PMR83): PMR83 sets whether the P83/SV2 pin is used as a P83 I/O pin or an SV2 pin for the servo monitor output. For the selection of the SV2 output, see section 28, Servo Circuits. Bit 3 PMR83 0 1 Description The P83/SV2 pin functions as a P83 I/O pin The P83/SV2 pin functions as an SV2 output pin (Initial value) Bit 2P82/SV1 Pin Switching (PMR82): PMR82 sets whether the P82/SV1 pin is used as a P82 I/O pin or an SV1 pin for the servo monitor output. For the selection of the SV1 output, see section 28, Servo Circuits. Bit 2 PMR82 0 1 Description The P82/SV1 pin functions as a P82 I/O pin The P82/SV1 pin functions as an SV1 output pin (Initial value) Rev.3.00 Jan. 10, 2007 page 283 of 1038 REJ09B0328-0300 Section 11 I/O Port Bit 1P81/EXCAP Pin Switching (PMR81): PMR81 sets whether the P81/EXCAP pin is used as a P81 I/O pin or an EXCAP pin for the capstan external synchronous signal input. Bit 1 PMR81 0 1 Description The P81/EXCAP pin functions as a P81 I/O pin The P81/EXCAP pin functions as an EXCAP input pin (Initial value) Bit 0P80/EXTTRG Pin Switching (PMR80): PMR80 sets whether the P80/EXTTRG pin is used as a P80 I/O pin or an EXTTRG pin for the external trigger signal input. Bit 0 PMR80 0 1 Description The P80/EXTTRG pin functions as a P80 I/O pin The P80/EXTTRG pin functions as an EXTTRG input pin (Initial value) (2) Port Control Register 8 (PCR8) Bit : Initial value : R/W : 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W Port control register 8 (PCR8) controls the I/Os of pins P87 to P80 of port 8 in a unit of bit. When PCR8 is set to 1, the corresponding P87 to P80 pins become output pins, and when it is set to 0, they become input pins. When the corresponding pin is set to a general I/O, settings of PCR8 and PDR8 become valid. PCR8 is an 8-bit write-only register. When PCR8 is read, 1 is read. When reset, PCR8 is initialized to H'00. Bit n PCR8n 0 1 Description The P8n pin functions as an input pin The P8n pin functions as an output pin (Initial value) Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 284 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) Port Data Register 8 (PDR8) Bit : Initial value : R/W : 7 PDR87 0 R/W 6 PDR86 0 R/W 5 PDR85 0 R/W 4 PDR84 0 R/W 3 PDR83 0 R/W 2 PDR82 0 R/W 1 PDR81 0 R/W 0 PDR80 0 R/W Port data register 8 (PDR8) stores the data for the pins P87 to P80 of port 8. When PCR8 is 1 (output), the PDR8 values are directly read if port 8 is read. Accordingly, the pin states are not affected. When PCR8 is 0 (input), the pin states are read if port 8 is read. PDR8 is an 8-bit read/write enable register. When reset, PDR8 is initialized to H'00. 11.10.3 Pin Functions This section describes the port 8 pin functions and their selection methods. (1) P87 to P84 P87 to P84 are switched as shown below according to the PCR8n bit in PCR8. PCR8n 0 1 Pin Function P8n input pin P8n output pin Legend: * Don't care. Note: n = 7 to 4 (2) P83/SV2 P83/SV2 is switched as shown below according to the PMR83 bit in PMR8 and the PCR83 bit in PCR8. PMR83 0 PCR83 0 1 1 * Legend: * Don't care. Pin Function P83 input pin P83n output pin SV2 output pin Rev.3.00 Jan. 10, 2007 page 285 of 1038 REJ09B0328-0300 Section 11 I/O Port (3) P82/SV1 P82/SV1 is switched as shown below according to the PMR82 bit in PRM8 and the PCR82 bit in PCR8. PMR82 0 PCR82 0 1 1 * Legend: * Don't care. Pin Function P82 input pin P82 output pin SV1 output pin (4) P81/EXCAP P81/EXCAP is switched as shown below according to the PMR81 bit in PRM8 and the PCR81 bit in PCR8. PMR81 0 PCR81 0 1 1 * Legend: * Don't care. Pin Function P81 input pin P81 output pin EXCAP input pin (5) P80/EXTTRG P80/EXTTRG is switched as shown below according to the PMR80 bit in PRM8 and the PCR80 bit in PCR8. PMR80 0 PCR80 0 1 1 * Legend: * Don't care. Pin Function P80 input pin P80 output pin EXTTRG input pin Rev.3.00 Jan. 10, 2007 page 286 of 1038 REJ09B0328-0300 Section 11 I/O Port 11.10.4 Pin States Table 11.28 shows the port 8 pin states in each operation mode. Table 11.28 Port 8 Pin States Pins Reset Active Operation Sleep Holding Standby Highimpedance Watch Highimpedance Subactive Operation Subsleep Holding P87 to P84 Highimpedance P83/SV2 P83/SV1 P81/EXCAP P80/EXTTRG Note: If the EXCAP and EXTTRG input pins are set, the pin level need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev.3.00 Jan. 10, 2007 page 287 of 1038 REJ09B0328-0300 Section 11 I/O Port Rev.3.00 Jan. 10, 2007 page 288 of 1038 REJ09B0328-0300 Section 12 Timer A Section 12 Timer A 12.1 Overview The Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768-kHz crystal oscillator. 12.1.1 Features Features of the Timer A are as follows: * Choices of eight different types of internal clocks (/16384, /8192, /4096, /1024, /512, /256, /64, and /16) are available for your selection. * Four different overflowing cycles (1 s, 0.5 s, 0.25 s, and 0.03125 s) are selectable as a clock timer. (When using a 32.768-kHz crystal oscillator.) * Requests for interrupt will be output when the counter overflows. Rev.3.00 Jan. 10, 2007 page 289 of 1038 REJ09B0328-0300 Section 12 Timer A 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the Timer A. w/128 TCA /128 * /256 * Overflowing of the interval timer /16384, /8192, /4096, /1024, /512, /256, /64, /16 System clock Prescaler S (PSS) Prescaler unit /64 * /8 * Interrupting circuit Interrupt requests Legend: TMA : Timer mode register A TCA : Timer counter A Note: * Selectable only when the prescaler W output (w/128) is working as the input clock to the TCA. Figure 12.1 Block Diagram of the Timer A 12.1.3 Register Configuration Table 12.1 shows the register configuration of the Timer A. Table 12.1 Register Configuration Name Timer mode register A Timer counter A Note: * Abbrev. TMA TCA R/W R/W R Size Byte Byte Initial Value H'30 H'00 Address* H'FFBA H'FFBB Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 290 of 1038 REJ09B0328-0300 Internal data bus 32-kHz w Crystal oscillator 1/4 Prescaler W (PSW) TMA Section 12 Timer A 12.2 12.2.1 Descriptions of Respective Registers Timer Mode Register A (TMA) Bit : 7 TMAOV 6 TMAIE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W Initial value : R/W : 0 R/(W)* Note: * Only 0 can be written to clear the flag. The timer mode register A (TMA) works to control the interrupts of the Timer A and to select the input clock. TMA is an 8-bit read/write register. When reset, the TMA will be initialized to H'30. Bit 7Timer A Overflow Flag (TMAOV): This is a status flag indicating the fact that the TCA is overflowing (H'FF H'00). Bit 7 TMAOV 0 Description [Clearing condition] (Initial value) When 0 is written to the TMAOV flag after reading the TMAOV flag under the status where TMAOV = 1 1 [Setting condition] When the TCA overflows Bit 6Enabling Interrupt of the Timer A (TMAIE): This bit works to permit/prohibit occurrence of interrupt of the Timer A (TMAI) when the TCA overflows and when the TMAOV of the TMA is set to 1. Bit 6 TMAIE 0 1 Description Prohibits occurrence of interrupt of the Timer A (TMAI) Permits occurrence of interrupt of the Timer A (TMAI) (Initial value) Bits 5 and 4Reserved: When they are read, 1 will always be readout. Writes are disabled. Rev.3.00 Jan. 10, 2007 page 291 of 1038 REJ09B0328-0300 Section 12 Timer A Bit 3Selection of the Clock Source and Prescaler (TMA3): This bit works to select the PSS or PSW as the clock source for the Timer A. Bit 3 TMA3 0 1 Description Selects the PSS as the clock source for the Timer A Selects the PSW as the clock source for the Timer A (Initial value) Bits 2 to 0Clock Selection (TMA2 to TMA0): These bits work to select the clock to input to the TCA. In combination with the TMA3 bit, the choices are as follows: Bit 3 TMA3 0 Bit 2 TMA2 0 Bit 1 TMA1 0 Bit 0 TMA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Note: = f osc 0 1 Prescaler Division Ratio (Interval Timer) Operation or Overflow Cycle (Time Base) Mode PSS, /16384 (Initial value) PSS, /8192 PSS, /4096 PSS, /1024 PSS, /512 PSS, /256 PSS, /64 PSS, /16 1s 0.5 s 0.25 s 0.03125 s Works to clear the PSW and TCA to H'00 Clock time base mode Interval timer mode Rev.3.00 Jan. 10, 2007 page 292 of 1038 REJ09B0328-0300 Section 12 Timer A 12.2.2 Timer Counter A (TCA) Bit : 7 TCA7 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R Initial value : R/W : 0 R The timer counter A (TCA) is an 8-bit up-counter which counts up on inputs from the internal clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA When the TCA overflows, the TMAOV bit of the TMA is set to 1. The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11. The TCA is always readable. When reset, the TCA will be initialized into H'00. 12.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit : Initial value : R/W : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR will be initialized into H'FFFF. Bit 7Module Stop (MSTP15): This bit works to designate the module stop mode for the Timer A. MSTPCRH Bit 7 MSTP15 0 1 Description Cancels the module stop mode of the Timer A Sets the module stop mode of the Timer A (Initial value) Rev.3.00 Jan. 10, 2007 page 293 of 1038 REJ09B0328-0300 Section 12 Timer A 12.3 Operation The Timer A is an 8-bit timer for use as an interval timer and as a clock time base connecting to a 32.768 kHz crystal oscillator. 12.3.1 Operation as the Interval Timer When the TMA3 bit of the TMA is cleared to 0, the Timer A works as an 8-bit interval timer. When resetince the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues counting up as the interval counter without interrupts right after resetting. As the operation clock for the Timer A, selection can be made from eight different types of internal clocks being output from the PSS by the TMA2 to TMA0 bits of the TMA. When the clock signal is input after the reading of the TCA reaches H'FF, the Timer A overflows and the TMAOV bit of the TMA will be set to 1. At this time, when the TMAIE bit of the TMA is 1, interrupt occurs. When overflowing occurs, the reading of the TCA returns to H'00 before resuming counting up. Consequently, it works as the interval timer to produce overflow outputs periodically at every 256 input clocks. 12.3.2 Operation of the Timer for Clocks When the TMA3 bit of the TMA is set to 1, the Timer A works as a time base for the clock. As the overflow cycles for the Timer A, selection can be made from four different types by counting the clock being output from the PSW by the TMA1 bit and TMA0 bit of the TMA. 12.3.3 Initializing the Counts When the TMA3 and TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to come to a stop. At this state, writing 10 to the TMA3 bit and TMA2 bit makes the Timer A to start counting from H'00 under the time base mode for clocks. After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the TMA3 bit and TMA2 bit work to make the Timer A to start counting from H'00 under the interval timer mode. However, since the PSS is not cleared, the period to the first count is not constant. Rev.3.00 Jan. 10, 2007 page 294 of 1038 REJ09B0328-0300 Section 13 Timer B Section 13 Timer B 13.1 Overview The Timer B is an 8-bit up-counter. The Timer B is equipped with two different types of functions namely, the interval function and the auto reloading function. 13.1.1 Features * Selection from choices of seven different types of internal clocks (/16384, /4096, /1024, /512, /128, /32, and /8) or selection of external clock are possible. * When the counter overflows, an interrupt request will be issued. 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the Timer B. TMB Clock sources /16384 /1024 /512 /128 /32 /8 Re-loading TCB Overflowing TMBI TLB Interrupting circuit Legend: TMB : Timer mode register B TCB : Timer counter B TLB : Timer re-loading register B TMBI : Event input terminal of the Timer B Timer B Interrupt requests Figure 13.1 Block diagram of the Timer B Rev.3.00 Jan. 10, 2007 page 295 of 1038 REJ09B0328-0300 Internal data bus /4096 Section 13 Timer B 13.1.3 Pin Configuration Table 13.1 shows the pin configuration of the Timer B. Table 13.1 Pin Configuration Name Event inputs to the Timer B Abbrev. TMBI I/O Input Function Event input pin for inputs to the TCB 13.1.4 Register Configuration Table 13.2 shows the register configuration of the Timer B. The TCB and TLB are being allocated to the same address. Reading or writing determines the accessing register. Table 13.2 Register Configuration Name Timer mode register B Timer counter B Timer load register B Port mode register 5 Note: * Abbrev. TMB TCB TLB PMR5 R/W R/W R W R/W Size Byte Byte Byte Byte Initial Value Address* H'18 H'00 H'00 H'F1 H'D110 H'D111 H'D111 H'FFDC Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 296 of 1038 REJ09B0328-0300 Section 13 Timer B 13.2 13.2.1 Descriptions of Respective Registers Timer Mode Register B (TMB) Bit : 7 TMB17 6 TMBIF 0 R/(W)* 5 TMBIE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMB12 0 R/W 1 TMB11 0 R/W 0 TMB10 0 R/W Initial value : R/W : 0 R/W Note: * Only 0 can be written to clear the flag. The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto reloading function and to select the input clock. When reset, the TMB is initialized to H'18. Bit 7Selecting the Auto Reloading Function (TMB17): This bit works to select the auto reloading function of the Timer B. Bit 7 TMB17 0 1 Description Selects the interval function Selects the auto reloading function (Initial value) Bit 6Interrupt Requesting Flag for the Timer B (TMBIF): This is an interrupt requesting flag for the Timer B. It indicates the fact that the TCB is overflowing. Bit 6 TMBIF 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When the TCB overflows (Initial value) Rev.3.00 Jan. 10, 2007 page 297 of 1038 REJ09B0328-0300 Section 13 Timer B Bit 5Enabling Interrupt of the Timer B (TMBIE): This bit works to permit/prohibit occurrence of interrupt of the Timer B when the TCB overflows and when the TMBIF is set to 1. Bit 5 TMBIE 0 1 Description Prohibits occurrence of interrupt of the Timer B Permits occurrence of interrupt of the Timer B (Initial value) Bits 4 and 3Reserved: When they are read, 1 will always be readout. Writes are disabled. Bits 2 to 0Clock Selection (TMB12 to TMB10): These bits work to select the clock to input to the TCB. Selection of the rising edge or the falling edge is workable with the external event inputs. Bit 2 TMB12 0 0 0 0 1 1 1 1 Note: * Bit 1 TMB11 0 0 1 1 0 0 1 1 Bit 0 TMB10 0 1 0 1 0 1 0 1 Descriptions Internal clock: Counts at /16384 Internal clock: Counts at /4096 Internal clock: Counts at /1024 Internal clock: Counts at /512 Internal clock: Counts at /128 Internal clock: Counts at /32 Internal clock: Counts at /8 Counts at the rising edge and the falling edge of external event inputs (TMBI)* (Initial value) The edge selection for the external event inputs is made by setting the PMR51 of the port mode register 5 (PMR5). See section 13.2.4, Port Mode Register 5 (PMR5). Rev.3.00 Jan. 10, 2007 page 298 of 1038 REJ09B0328-0300 Section 13 Timer B 13.2.2 Timer Counter B (TCB) Bit : 7 TCB17 6 TCB16 0 R 5 TCB15 0 R 4 TCB14 0 R 3 TCB13 0 R 2 TCB12 0 R 1 TCB11 0 R 0 TCB10 0 R Initial value : R/W : 0 R The TCB is an 8-bit readable register which works to count up by the internal clock inputs and external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB. When the TCB overflows (H'FF H'00 or H'FF TLB setting), a interrupt request of the Timer B will be issued. When reset, the TCB is initialized to H'00. 13.2.3 Timer Load Register B (TLB) Bit : 7 TLB17 Initial value : R/W : 0 W 6 TLB16 0 W 5 TLB15 0 W 4 TLB14 0 W 3 TLB13 0 W 2 TLB12 0 W 1 TLB11 0 W 0 TLB10 0 W The TLB is an 8-bit write only register which works to set the reloading value of the TCB. When the reloading value is set to the TLB, the value will be simultaneously loaded to the TCB and the TCB starts counting up from the set value. Also, during an auto reloading operation, when the TCB overflows, the value of the TLB will be loaded to the TCB. Consequently, the overflowing cycle can be set within the range of 1 to 256 input clocks. When reset, the TLB is initialized to H'00. 13.2.4 Port Mode Register 5 (PMR5) Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PMR53 0 R/W 2 PMR52 0 R/W 1 PMR51 0 R/W 0 -- 1 -- The port mode register 5 (PMR5) works to changeover the pin functions of the port 5 and to designate the edge sense of the event inputs of the Timer B (TMBI). The PMR5 is an 8-bit read/write register. When reset, the PMR5 will be initialized to H'F1. See section 11.7, Port 5 for other information than bit 1. Rev.3.00 Jan. 10, 2007 page 299 of 1038 REJ09B0328-0300 Section 13 Timer B Bit 1Selecting the Edges of the Event Inputs to the Timer B (PMR51): This bit works to select the input edge sense of the TMBI pins. Bit 1 PMR51 0 1 Description Detects the falling edge of the event inputs to the Timer B Detects the rising edge of the event inputs to the Timer B (Initial value) 13.2.5 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module stop mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 6Module Stop (MSTP14): This bit works to designate the module stop mode for the Timer B. MSTPCRH Bit 6 MSTP14 0 1 Description Cancels the module stop mode of the Timer B Sets the module stop mode of the Timer B (Initial value) Rev.3.00 Jan. 10, 2007 page 300 of 1038 REJ09B0328-0300 Section 13 Timer B 13.3 13.3.1 Operation Operation as the Interval Timer When the TMB17 bit of the TMB is set to 0, the Timer B works as an 8-bit interval timer. When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, the Timer B continues counting up as the interval timer without interrupts right after resetting. As the clock source for the Timer B, selection can be made from seven different types of internal clocks being output from the prescaler unit by the TMB12 to TMB10 bits of the TMB or an external clock through the TMBI input pin can be chosen instead. When the clock signal is input after the reading of the TCB reaches H'FF, the Timer B overflows and the TMBIF bit of the TMB will be set to 1. At this time, when the TMBIE bit of the TMB is 1, interrupt occurs. When overflowing occurs, the reading of the TCB returns to H'00 before resuming counting up. When a value is set to the TLB while the interval timer is in operation, the value which has been set to the TLB will be loaded to the TCB simultaneously. 13.3.2 Operation as the Auto Reload Timer When the TMB17 of the TMB is set to 1, the Timer B works as an 8-bit auto reload timer. When a reload value is set in the TLB, the value is loaded onto the TCB at the same time, and the TCB starts counting up from the value. When the clock signal is input after the reading of the TCB reaches H'FF, the Timer B overflows and the TLB value is loaded onto the TCB, then the TCB continues counting up from the loaded value. Accordingly, overflow interval can be set within the range of 1 to 256 clocks depending on the TLB value. Clock source and interrupts in the auto reload operation are the same as those in the interval operation. When the TLB value is re-set while the auto reload timer is in operation, the value which has been set to the TLB will be loaded onto the TCB simultaneously. 13.3.3 Event Counter The Timer B works as an event counter using the TMBI pin as the event input pin. When the TMB12 to TMB10 are set to 111, the external event will be selected as the clock source and the TCB counts up at the leading edge or the trailing edge of the TMBI pin inputs. Rev.3.00 Jan. 10, 2007 page 301 of 1038 REJ09B0328-0300 Section 13 Timer B Rev.3.00 Jan. 10, 2007 page 302 of 1038 REJ09B0328-0300 Section 14 Timer J Section 14 Timer J 14.1 Overview The Timer J consists of twin 8-bit counters. It carries seven different operation modes such as reloading and event counting. 14.1.1 Features The Timer J consists of twin 8-bit reloading timers and it is usable under the various functions as follows: * Twin 8-bit reloading timers (Among the two, one is capable to make timer outputs) * Twin 8-bit event counters (Capable to make reloading) * 8-bit event counter (Capable to make reloading) + 8-bit reload timer * 16-bit event counter (Capable to make 16-bit reloading) * 16-bit reload timer (Capable to make 16-bit reloading) * Remote controlled transmissions * "Take up/Supply reel pulse" dividing (8 bit x 2 units) 14.1.2 Block Diagram Figure 14.1 is a block diagram of the Timer J. The Timer J consists of two reload timers namely, TMJ-1 and TMJ-2. Rev.3.00 Jan. 10, 2007 page 303 of 1038 REJ09B0328-0300 TMJ-1 Interrupting circuit TMJ-2 Interrupting circuit /4096 /8192 Toggle Interrupt request by the TMJ2 BUSS Output Control Section 14 Timer J Interrupt request by the TMJ1 PB/REC-CTL DVCTL TCA7 Monitor Output Control BUZZ TMO TMJ-1 TCJ Downcounter (8 bit) Underflow Down-counter (8 bit) flow Reloading TMO Rev.3.00 Jan. 10, 2007 page 304 of 1038 REJ09B0328-0300 Clock sources IRQ2 /1024 (only for the H8S/2194C Group) /2048 TMJ-2 /16384 TCK Under- Toggle TGL Clock sources IRQ1 /4 /256 /512 REMOout Reloading register TLJ Reloading Edge detection * T/R 8/16 Reloading register (Burst/space PS21, 20 width register TLK Internal data bus BUZZ TMO : Buzzer output : TMJ-1 timer output PS11,10 : TMJ-1 input clock selection PS21,20 : TMJ-2 input clock selection ST 8/16 T/R : Starting the remote controlled operation : 8-bit/16-bit operation changeover : Timer output/Remote controller output changeover ST Synchronization PS11,10 Figure 14.1 Block Diagram of the Timer J REMOout : TMJ-2 toggle output (Remote controller transmission data) TGL : TMJ-2 toggle plug Legend: TCJ : Timer counter J TLJ : Timer load register J TCK : Timer counter K TLK : Timer load register K Note: * At the Low level under the timer mode. Section 14 Timer J 14.1.3 Pin Configuration Table 14.1 shows the pin configuration of the Timer J. Table 14.1 Pin Configuration Name Event input pin Event input pin Abbrev. IRQ1 IRQ2 I/O Input Input Function Event inputs to the TMJ-1 Event inputs to the TMJ-2 14.1.4 Register Configuration Table 14.2 shows the register configuration of the Timer J. The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively. Reading or writing determines the accessing register. Table 14.2 Register Configuration Name Timer mode register J Timer J control register Timer J status register Timer counter J Timer counter K Timer load register J Timer load register K Abbrev. TMJ TMJC TMJS TCJ TCK TLJ TLK R/W R/W R/W 1 R/(W)* Size Byte Byte Byte Byte Byte Byte Byte Initial Value H'00 H'09 H'3F H'FF H'FF H'FF H'FF 2 Address* H'D13A H'D13B H'D13C H'D139 H'D138 H'D139 H'D138 R R W W Notes: 1. Only 0 can be written to clear the flag. 2. Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 305 of 1038 REJ09B0328-0300 Section 14 Timer J 14.2 14.2.1 Descriptions of Respective Registers Timer Mode Register J (TMJ) Bit : 7 PS11 6 PS10 0 R/W 5 ST 0 R/W 4 8/16 0 R/W 3 PS21 0 R/W 2 PS20 0 R/W 1 TGL 0 R 0 T/R 0 R/W Initial value : R/W : 0 R/W The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and to set the operation mode. The TMJ is an 8-bit register and Bit-1 is for read only and all the remaining bits are applicable to read/write. When reset, the TMJ is initialized to H'00. Under all other modes than the remote controlling mode, writing into the TMJ works to initialize the counters (TCJ and TCK) to H'FF. Bits 7 and 6Selecting the Inputting Clock to the TMJ-1 (PS11 and PS10): These bits work to select the clock to input to the TMJ-1. Selection of the rising edge or the falling edge is workable for counting by use of an external clock. Bit 7 PS11 0 Bit 6 PS10 0 1 1 0 1 Note: * Description Counting by the PSS, /512 Counting by the PSS, /256 Counting by the PSS, /4 Counting at the rising edge or the falling edge of the external clock inputs (IRQ1)* (Initial value) The edge selection for the external clock inputs is made by setting the edge select register (IEGR). See section 6.2.4, IRQ Edge Select Registers (IEGR) for more information. When using an external clock under the remote controlling mode, set the opposite edge with the IRQ1 and the IRQ2 when using an external clock under the remote controlling mode. (When IRQ1 falling, select IRQ2 rising and when IRQ1 rising, select IRQ2 falling.) Rev.3.00 Jan. 10, 2007 page 306 of 1038 REJ09B0328-0300 Section 14 Timer J Bit 5Starting the Remote Controlled Operation (ST): This bit works to start the remote controlled operations. When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions. When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be valid under the remote controlling mode, namely, when the Bit 0 (T/R bit) is 1 and the Bit 4 (8/16-bit) is 0. Under other modes than the remote controlling mode, it will be fixed to 0. When a shift to the low power consumption mode is made during remote controlled operation, the ST bit will be cleared to 0. When resuming operation after returning to the active mode, write 1. Bit 5 ST 0 1 Description Works to stop clock signal supply to the TMJ-1 under the remote controlling mode (Initial value) Works to supply clock signal to the TMJ-1 under the remote controlling mode Bit 4Switching Over Between 8-bit/16-bit Operations (8/16): This bit works to choose if using the Timer J as two units of 8-bit timer/counter or if using it as a single unit of 16-bit timer/counter. Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be valid. Bit 4 8/16 0 1 Description Makes the TMJ-1 and TMJ-2 operate separately Makes the TMJ-1 and TMJ-2 operate altogether as 16-bit timer/counter (Initial value) Rev.3.00 Jan. 10, 2007 page 307 of 1038 REJ09B0328-0300 Section 14 Timer J Bits 3 and 2Selecting the Inputting Clock to the TMJ-2 (PS21 and PS20): This bit works to select the clock to input to the TMJ-2. Selection of the leading edge or the trailing edge is workable for counting by use of an external clock. TMJC: Bit 0 Bit 3 3 PS22* Bit 2 PS20 0 1 Description Counting by the PSS, /16384 Counting by the PSS, /2048 Counting at underflowing of the TMJ-1 Counting at the leading edge or the trailing edge of 1 the external clock inputs (IRQ2)* Counting by the PSS, /1024 (available only the H8S/2194C Group) (Initial value) PS21 0 1 1 0 1 0 *2 *2 Notes: 1. The edge selection for the external clock inputs is made by setting the edge select register (IEGR). See section 6.2.4, IRQ Edge Select Registers (IEGR) for more information. 2. Don't care. 3. Available only in the H8S/2194C Group. Bit 1TMJ-2 Toggle Flag (TGL): This flag indicates the toggled status of the underflowing with the TMJ-2. Reading only is workable. It will be cleared to 0 under the low power consumption mode. Bit 1 TGL 0 1 Description The toggle output of the TMJ-2 is 0 The toggle output of the TMJ-2 is 0 (Initial value) Bit 0Switching Over between Timer Output/Remote Controlling Output (T/R): This bit works to select if using the timer outputs from the TMJ-1 as the output signal through the TMO pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the output signal through the TMO pin. Bit 0 T/R 0 1 Description Timer outputs from the TMJ-1 Toggle outputs from the TMJ-2 (remote controlled transmission data) (Initial value) Rev.3.00 Jan. 10, 2007 page 308 of 1038 REJ09B0328-0300 Section 14 Timer J Selecting the Operation Mode: The operation mode of the Timer J is determined by the Bit 4 (8/16) and Bit 0 (T/R) of the TMJ. TMJ Bit 4 8/16 0 Bit 0 T/R 0 1 1 * Legend: * Don't care. Description 8-bit timer x 2 Remote controlling mode 16-bit timer (Initial value) When writing is made into the TMJ under the timer mode, the counters (TCJ and TCK) will be initialized (H'FF). Consequently, writing into the reloading registers (TLJ an TLK) should be conducted after finishing settings with the TMJ. Under the remote controlling mode, although the TLJ and the TLK will not be initialized even when writing is made into the TMJ, follow the sequence listed below when starting a remote controlling operation. (1) Make setting to the remote controlling mode with the TMJ. (2) Write the data into the TLJ and TLK. (3) Start the remote controlled operation by use of the TMJ. (ST bit = 1) Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be valid. 14.2.2 Timer J Control Register (TMJC) Bit : 7 BUZZ1 Initial value : R/W : 0 R/W 6 BUZZ0 0 R/W 5 MON1 0 R/W 4 MON0 0 R/W 3 -- 1 -- 2 TMJ2IE 0 R/W 1 TMJ1IE 0 R/W 0 (PS22)* 1 (R/W)* Note: * Bit 0 is readable/writable only in the H8S/2194C Group. The timer J control register works to select the buzzer output frequency and to control permission/prohibition of interrupts. The TMJC is an 8-bit read/write register. When reset, the TMJC is initialized to H'09. Bits 7 and 6Selecting the Buzzer Output (BUZZ1 or BUZZ0): This bit works to select if using the buzzer outputs as the output signal through the BUZZ pin or if using the monitor signals as the output signal through the BUZZ pin. Rev.3.00 Jan. 10, 2007 page 309 of 1038 REJ09B0328-0300 Section 14 Timer J When setting is made to the monitor signals, choose the monitor signal using the MON1 bit and MON0 bit. Bit 7 BUZZ1 0 Bit 6 BUZZ0 0 1 1 0 1 Description /4096 /8192 Works to output monitor signals Works to output BUZZ signals from the Timer J Frequency when = 10 MHz (Initial value) 2.44 kHz 1.22 kHz Bits 5 and 4Selecting the Monitor Signals (MON1 or MON0): These bits work to select the type of signals being output through the BUZZ pin for monitoring purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 1 and 0. When PB-CTL or REC-CTL is chosen, signal duties will be output as they are. In case of DVCTL signals, signals from the CTL dividing circuit will be toggled before being output. Signal waveforms divided by the CTL dividing circuit into "n-divisions" will further be divided into halves. (Namely, "2n" divisions, 50% duty waveform). In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty) When the prescaler is being used with the Timer A, 1 Hz outputs are available. Bit 5 MON1 0 Bit 4 MON0 0 1 1 * Legend: * Don't care. Description PB or REC-CTL DVCTL Outputs TCA7 (Initial value) Bit 3Reserved: When this is read, 1 will always be readout. Writes are disabled. Bit 2Enabling Interrupt of the TMJ2I (TMJ2IE): This bit works to permit/prohibit occurrence of TMJ2I interrupt of the TMJS in 1-set of the TMJ2I. Bit 2 TMJ2IE 0 1 Description Prohibits occurrence of TMJ2I interrupt Permits occurrence of TMJ2I interrupt (Initial value) Rev.3.00 Jan. 10, 2007 page 310 of 1038 REJ09B0328-0300 Section 14 Timer J Bit 1Enabling Interrupt of the TMJ1I (TMJ1IE): This bit works to permit/prohibit occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I. Bit 1 TMJ1IE 0 1 Description Prohibits occurrence of TMJ1I interrupt Permits occurrence of TMJ1I interrupt (Initial value) Bit 0Reserved (for H8S/2194 Group): When this is read, 1 will always be readout. Writes are disabled. Bit 0Selecting the Input clock for TMJ-2 (PS22) (for H8S/2194C Group): This bit, together with bits 3 and 2 (PS21, PS20) in TMJ, selects the input clock for TMJ-2. For details, see section 14.2.1, Timer Mode Register J (TMJ). 14.2.3 Timer J Status Register (TMJS) Bit : 7 TMJ2I Initial value : 0 R/(W)* 6 TMJ1I 0 R/(W)* 5 -- 1 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- -- R/W : Note: * Only 0 can be written to clear the flag. The timer J status register (TMJS) works to indicate issuance of the interrupt request of the Timer J. The TMJS is an 8-bit read/write register. When reset, the TMJS is initialized to H'3F. Bit 7TMJ2I Interrupt Requesting Flag (TMJ2I): This is the TMJ2I interrupt requesting flag. This flag is set when the TMJ-2 underflows. Bit 7 TMJ2I 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When the TMJ-2 underflows (Initial value) Rev.3.00 Jan. 10, 2007 page 311 of 1038 REJ09B0328-0300 Section 14 Timer J Bit 6TMJ1I Interrupt Requesting Flag (TMJ1I): This is the TMJ1I interrupt requesting flag. This flag is set out when the TMJ-1 underflows. TMJ1I interrupt requests will also be made under a 16-bit operation. Bit 6 TMJ1I 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When the TMJ-1 underflows (Initial value) Bits 5 to 0Reserved: When they are read, 1 will always be readout. Writes are disabled. 14.2.4 Timer Counter J (TCJ) Bit : 7 TDR17 Initial value : R/W : 1 R 6 TDR16 1 R 5 TDR15 1 R 4 TDR14 1 R 3 TDR13 1 R 2 TDR12 1 R 1 TDR11 1 R 0 TDR10 1 R The time counter J (TCJ) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and PS10 bits of the TMJ. TCJ values can be readout always. Nonetheless, when the 8-/16-bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), reading is possible under the word command only. At this time, the TCK of the TMJ-2 can be read by the upper 8 bits and the TCJ can be read by the lower 8 bits. When the TCJ underflows (H'00 Reloading value), regardless of the operation mode setting of the 8-/16-bit, the TMJ1I bit of the TMJS will be set to 1. The TCJ and TLJ are being allocated to the same address. When reset, the TCJ is initialized to H'FF. Rev.3.00 Jan. 10, 2007 page 312 of 1038 REJ09B0328-0300 Section 14 Timer J 14.2.5 Timer Counter K (TCK) Bit : 7 TDR27 6 TDR26 1 R 5 TDR25 1 R 4 TDR24 1 R 3 TDR23 1 R 2 TDR22 1 R 1 TDR21 1 R 0 TDR20 1 R Initial value : R/W : 1 R The time counter K (TCK) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS21 and PS20 bits of the TMJ. TCK values can be readout always. Nonetheless, when the 8-/16-bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), reading is possible under the word command only. At this time, the TCK can be read by the upper 8 bits and the TCJ of the TMJ-1 can be read by the lower 8 bits. When the TCK underflows (H'00 Reloading value), the TMJ2I bit of the TMJS will be set to 1. The TCK and TLK are being allocated to the same address. When reset, the TCK is initialized to H'FF. 14.2.6 Timer Load Register J (TLJ) Bit : 7 TLR17 Initial value : R/W : 1 W 6 TLR16 1 W 5 TLR15 1 W 4 TLR14 1 W 3 TLR13 1 W 2 TLR12 1 W 1 TLR11 1 W 0 TLR10 1 W The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading value of the TCJ. When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and the TCJ starts counting down from the set value. Also, during an auto reloading operation, when the TCJ underflows, the value of the TLJ will be loaded to the TCJ. Consequently, the underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the 8-/16-bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), writing is possible under the word command only. At this time, the upper 8 bits can be written into the TLK of the TMJ-2 and the lower 8 bits can be written into the TLJ. The TLJ and TCJ are being allocated to the same address. When reset, the TLJ is initialized to H'FF. Rev.3.00 Jan. 10, 2007 page 313 of 1038 REJ09B0328-0300 Section 14 Timer J 14.2.7 Timer Load Register K (TLK) Bit : 7 TLR27 6 TLR26 1 W 5 TLR25 1 W 4 TLR24 1 W 3 TLR23 1 W 2 TLR22 1 W 1 TLR21 1 W 0 TLR20 1 W Initial value : R/W : 1 W The timer load register K (TLK) is an 8-bit write only register which works to set the reloading value of the TCK. When the reloading value is set to the TLK, the value will be simultaneously loaded to the TCK and the TCK starts counting down from the set value. Also, during an auto reloading operation, when the TCK underflows, the value of the TLK will be loaded to the TCK. Consequently, the underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the 8-/16-bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), writing is possible under the word command only. At this time, the upper 8 bits can be written into the TLK and the lower 8 bits can be written into the TLJ of the TMJ-1. The TLK and TCK are being allocated to the same address. When reset, the TLK is initialized to H'FF. 14.2.8 Module Stop Control Register (MSTPCR) MSTPCRH Bit : Initial value : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP13 bit is set to 1, the Timer J stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 5Module Stop (MSTP13): This bit works to designate the module stop mode for the Timer J. MSTPCRH Bit 5 MSTP13 0 1 Description Cancels the module stop mode of the Timer J Sets the module stop mode of the Timer J (Initial value) Rev.3.00 Jan. 10, 2007 page 314 of 1038 REJ09B0328-0300 Section 14 Timer J 14.3 14.3.1 Operation 8-Bit Reload Timer (TMJ-1) The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through the IRQ1 pin are being used. By selecting the edge signals through the IRQ1 pin, it can also be used as an event counter. While it is working as an event counter, its reloading function is workable simultaneously. When data are written into the reloading register TLJ, these data will be written into the counter TCJ simultaneously. Also, when the counter TCJ underflows, the data of the reloading register TLJ will be reloaded to the counter TCJ. When the counter underflows, TMJ1I interrupt requests will be issued. The underflow will be toggled and, by a appropriate selection of the dividing clock, buzzer outputs will be issued or carrier frequencies for remote controlling transmissions can be acquired. The TMJ-1 and TMJ-2, in combination, can be used as a 16-bit reload timer. Nonetheless, when they are being used, in combination, as a 16-bit timer, word command only is valid and the TCK works as the down counter for the upper 8 bits and the TCJ works as the down counter for the lower 8 bits, means a reloading register of total 16 bits. When data are written into a 16-bit reloading register, the same data will be written into the 16-bit counter. Also, when the 16-bit counter underflows, the data of the 16-bit reloading register will be reloaded into the counter. Even when they are making a 16-bit operation, the TMJ1I interrupt requests of the TMJ-1 and BUZZ outputs are effective. In case these functions are not necessary, make them invalid by programming. The TMJ-1 and TMJ-2, in combination, can be used for remote controlled data transmission. Regarding the remote controlled data transmission, see section 14.3.3, Remote Controlled Data Transmission. 14.3.2 8-Bit Reload Timer (TMJ-2) The TMJ-2 is an 8-bit down-counting reload timer. As the clock source, dividing clock, edge signals through the IRQ2 pin or the underflow signals from the TMJ-1 are being used. By selecting the edge signals through the IRQ2 pin, it can also be used as an event counter. While it is working as an event counter, its reloading function is workable simultaneously. When data are written into the reloading register TLK, these data will be written into the counter TCK simultaneously. Also, when the counter TCK underflows, the data of the reloading register TLK will be made to the data counter TCK. When the counter underflows, TMJ2I interrupt requests will be issued. The TMJ-2 and TMJ-1, in combination, can be used as a 16-bit reload timer. For more information Rev.3.00 Jan. 10, 2007 page 315 of 1038 REJ09B0328-0300 Section 14 Timer J on the 16-bit reload timer, see section 14.3.1, 8-bit Reload Timer (TMJ-1). The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission. Regarding the remote controlled data transmission, see section 14.3.3, Remote Controlled Data Transmission. 14.3.3 Remote Controlled Data Transmission The Timer J is capable of making remote controlled data transmission. The carrier frequencies for the remote controlled data transmission can be generated by the TMJ-1 and the burst width duration and the space width duration can be setup by the TMJ-2. The data having been written into the reloading register TMJ-1 and into the burst/space duration register (TLK) of the TMJ-2 will be loaded to the counter at the same time as the remote controlled data transmission starts. (Remote controlled data transmission starting bit (ST) 1) While remote controlled data transmission is being made, the contents of the burst/space duration register will be loaded to the counter only while reloading is being made by underflow signals. Even when a writing is made to the burst/space duration register while remote controlled data transmission is being made, reloading operation will not be made until an underflow signal is issued. The TMJ-2 issues TMJ2I interrupt requests by the underflow signals. The TMJ-1 performs normal reloading operation (including the TMJ1I interrupt requests). Figure 14.2 shows the output waveform for the remote controlled data transmission function. When a shift to the low power consumption mode is effected while remote controlled data transmission is being made, the ST bit will be cleared to 0. When resuming the remote controlled data transmission after returning to the active mode, write 1. Rev.3.00 Jan. 10, 2007 page 316 of 1038 REJ09B0328-0300 Section 14 Timer J TMJ-1 can generate the carrier frequencies Remote controlled data transmission outputs Burst width TMJ-2 toggle output =1 Setting the remote controlled mode Setting the burst width ST bit 1 Setting the space width Underflow Space width TMJ-2 toggle output =0 Setting the burst width Burst width TMJ-2 toggle output = 1 Setting the space width Underflow Underflow Figure 14.2 Remote Controlled Data Transmission Output Waveform Rev.3.00 Jan. 10, 2007 page 317 of 1038 REJ09B0328-0300 Section 14 Timer J Figure 14.3 Timer Output Timing Rev.3.00 Jan. 10, 2007 page 318 of 1038 REJ09B0328-0300 Remote controlled data transmission output REMOout TMO (BUZZ) TMJ-1 TMJ-2 TMO UDF UDF Section 14 Timer J When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote controlled data transmission starts. Consequently, when the TLK is updated during the period after setting the ST bit to 1 until the next cycle of the inputting clock comes, the initial burst width will be changed like shown in figure 14.4. Therefore, when making remote controlled data transmission, determine I/O of the TGL bit at the time of the first burst width control operation without fail. (Or, set the space width to the TLK after waiting for a cycle of the inputting clock.) After that, operations can be continued by interrupts. Similarly, pay attention to the control works when ending remote controlled data transmission. Exemple) 1) Set the burst width with the TLK. 2) ST bit 1 3) Execute the procedure 4) if the TGL flag = 1. 4) Set the space width with the TLK under the status where the TGL flag = 1. 5) Make TMJ-2 interrupt. 6) Set the burst width with the TLK. : n) After making TMJ-2 interrupt, make setting of the ST 0 under the status where the TGL flag = 0. Inputting clock to the TMJ-2 Interrupt Interrupt TGL flag Burst width according to (B) Space width according to (S) ST 0 Delay ST 1 TLK setting (Burst width) (B) Remote controlled data transmission starts here. Delay The period during which the space width settig can be made. (S) If an updating is made with the TLK during this period, the burst width will be changed. Stopping the remote controlled data transmission Figure 14.4 Controls of the Remote Controlled Data Transmission Rev.3.00 Jan. 10, 2007 page 319 of 1038 REJ09B0328-0300 Section 14 Timer J Rev.3.00 Jan. 10, 2007 page 320 of 1038 REJ09B0328-0300 Section 15 Timer L Section 15 Timer L 15.1 Overview The Timer L is an 8-bit up/down counter using the control pulses or the CFG division signals as the clock source. 15.1.1 Features Features of the Timer L are as follows: * Choices of two different types of internal clocks (/128 and /64), DVCFG2 (CFG division signal 2), PB and REC-CTL (control pulses) are available for your selection. In case the PB-CTL is not available, such as when reproducing un-recorded tapes, tape count can be made by the DVCFG2. -- Selection of the leading edge or the trailing edge is workable with the CTL pulse counting. * Interrupts occur when the counter overflows or underflows and at occurrences of compare match clear. * It is possible to switch over between the up-counting and down-counting functions with the counter. Rev.3.00 Jan. 10, 2007 page 321 of 1038 REJ09B0328-0300 Section 15 Timer L 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the Timer L. INTERNAL CLOCK /128 /64 LMR Read DVCFG2 PB and REC-CTL LTC OVF/UDF Reloading Match clear Comparator Interrupting circuit RCR Legend: DVCFG2 : Division signal 2 of the CFG PB and REC-CTL : Control pluses necessary when making reproduction and storage LMR : Timer L mode register LTC : Linear time counter RCR : Reload/compare match register OVF : Overflow UDF : Underflow Write Internal data bus Interrupt request Figure 15.1 Block Diagram of the Timer L Rev.3.00 Jan. 10, 2007 page 322 of 1038 REJ09B0328-0300 Section 15 Timer L 15.1.3 Register Configuration Table 15.1 shows the register configuration of the Timer L. The linear time counter (LTC) and the reload compare patch register (RCR) are being allocated to the same address. Reading or writing determines the accessing register. Table 15.1 Register Configuration Name Timer L mode register Linear time counter Reload/compare match register Note: * Abbrev. LMR LTC RCR R/W R/W R W Size Byte Byte Byte Initial Value Address* H'30 H'00 H'00 H'D112 H'D113 H'D113 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 323 of 1038 REJ09B0328-0300 Section 15 Timer L 15.2 15.2.1 Descriptions of Respective Registers Timer L Mode Register (LMR) Bit : 7 LMIF 6 LMIE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 LMR3 0 R/W 2 LMR2 0 R/W 1 LMR1 0 R/W 0 LMR0 0 R/W Initial value : 0 R/W : R /(W)* Note: * Only 0 can be written to clear the flag. The timer L mode register (LMR) is an 8-bit read/write register which works to control the interrupts, to select between up-counting and down-counting and to select the clock source. When reset, the LMR is initialized to H'30. Bit 7Timer L Interrupt Requesting Flag (LMIF): This is the Timer L interrupt requesting flag. It indicates occurrence of overflow or underflow of the LTC or occurrence of compare match clear. Bit 7 LMIF 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When the LTC overflows, underflows or when compare match clear has occurred (Initial value) Bit 6Enabling Interrupt of the Timer L (LMIE): This bit works to permit/prohibit occurrence of interrupt of the Timer L when the LTC overflows, underflows or when compare match clear has occurred. Bit 6 LMIE 0 1 Description Prohibits occurrence of interrupt of the Timer L Permits occurrence of interrupt of the Timer L (Initial value) Bits 5 and 4Reserved: When they are read, 1 will always be readout. Writes are disabled. Bit 3Up-Count/Down-Count Control (LMR3): This bit is for selection if the Timer L is to be controlled to the up-counting function or down-counting function. Rev.3.00 Jan. 10, 2007 page 324 of 1038 REJ09B0328-0300 Section 15 Timer L (1) When controlled to the up-counting function When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00 before starting counting up. When the LTC value and the RCR value match, the LTC will be cleared to H'00. Also, interrupt requests will be issued by the match signal. (Compare patch clear function) When H'00 is set to the RCR, the counter makes 8-bit interval timer operation to issue a interrupt request when overflowing occurs. (Interval timer function) (2) When controlled to the down-counting function When a value is set to the RCR, the set value is reloaded to the LTC and counting down starts from that value. When the LTC underflows, the value of the RCR will be reloaded to the LTC. Also, when the LTC underflows, a interrupt request will be issued. (Auto reload timer function) Bit 3 LMR3 0 1 Description Controlling to the up-counting function Controlling to the up-counting function (Initial value) Bits 2 to 0Clock Selection (LMR2 to LMR0): The bits LMR2 to LMR0 work to select the clock to input to the Timer L. Selection of the leading edge or the trailing edge is workable for counting by the PB and the REC-CTL. Bit 2 LMR2 0 Bit 1 LMR1 0 Bit 0 LMR0 0 1 1 1 0 1 Legend: * Don't care. * * * Description Counts at the rising edge of the PB and REC-CTL (Initial value) Counts at the falling edge of the PB and REC-CTL Counts the DVCFG2 Counts at /128 of the internal clock Counts at /64 of the internal clock Rev.3.00 Jan. 10, 2007 page 325 of 1038 REJ09B0328-0300 Section 15 Timer L 15.2.2 Linear Time Counter (LTC) Bit : 7 LTC7 6 LTC6 0 R 5 LTC5 0 R 4 LTC4 0 R 3 LTC3 0 R 2 LTC2 0 R 1 LTC1 0 R 0 LTC0 0 R Initial value : R/W : 0 R The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be selected by the LMR2 to LMR0 bits of the LMR. When reset, the LTC is initialized to H'00. 15.2.3 Reload/Compare Match Register (RCR) Bit : 7 RCR7 Initial value : R/W : 0 W 6 RCR6 0 W 5 RCR5 0 W 4 RCR4 0 W 3 RCR3 0 W 2 RCR2 0 W 1 RCR1 0 W 0 RCR0 0 W The reload/compare match register (RCR) is an 8-bit write only register. When the Timer L is being controlled to the up-counting function, when a compare match value is set to the RCR, the LTC will be cleared at the same time and the LTC will then start counting up from the initial value (H'00). While, when the Timer L is being controlled to the down-counting function, when a reloading value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC will then start counting up from said value. Also, when the LTC underflows, the value of the RCR will be reloaded to the LTC. When reset, the RCR is initialized to H'00. 15.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : Initial value : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP12 bit is set to 1, the Timer L stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Rev.3.00 Jan. 10, 2007 page 326 of 1038 REJ09B0328-0300 Section 15 Timer L Bit 4Module Stop (MSTP12): This bit works to designate the module stop mode for the Timer L. MSTPCRH Bit 4 MSTP12 0 1 Description Cancels the module stop mode of the Timer L Sets the module stop mode of the Timer L (Initial value) 15.3 Operation The Timer L is an 8-bit up/down counter. The inputting clock for the Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the choices of the internal clock (/128 and /64), DVCDG2, PB and REC-CTL. The Timer L is provided with three different types of operation modes, namely, the compare match clear mode when controlled to the up-counting function, the auto reloading mode when controlled to the down-counting function and the interval timer mode. Respective operation modes and operation methods will be explained below. 15.3.1 Compare Match Clear Operation When the LMR3 bit of the LMR is cleared to 0, the Timer L will be controlled to the up-counting function. When any other values than H'00 are written into the RCR, the LTC will be cleared to H'00 simultaneously before starting counting up. Figure 15.2 shows the clear timing of the LTC. When the LTC value and the RCR value match (compare match), the LTC readings will be cleared to H'00 to resume counting from H'00. Figure 15.3 indicated on the next page shows the compare match clear timing. Rev.3.00 Jan. 10, 2007 page 327 of 1038 REJ09B0328-0300 Section 15 Timer L 1 state Write signal RCR LTC N H'00 Figure 15.2 RCR Writing and LTC Clearing Timing Chart PB-CTL Count-up signal Compare match clear signal RCR N-1 N LTC Interrupt request N H'00 Figure 15.3 Compare Match Clearing Timing Chart (In Case the Rising Edge of the PB-CTL Is Selected) Rev.3.00 Jan. 10, 2007 page 328 of 1038 REJ09B0328-0300 Section 16 Timer R Section 16 Timer R 16.1 Overview The Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and slow tracking function in addition to the reloading function and event counter function. 16.1.1 Features The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units of reloading timers/counters and by combining three units of timers, it can be used for the following applications: * Applications making use of the functions of three units of reloading timers. * For identification of the VCR mode. * For reel controls. * For acceleration and braking of the capstan motor when being applied to intermittent movements. * Slow tracking mono-multi applications. 16.1.2 Block Diagram The Timer R consists of three units of reload timer counters, namely, two units of reload timer counters equipped with capturing function (TMRU-1 and TMRU-2) and a unit of reload timer counter (TMRU-3). Figure 16.1 is a block diagram of the Timer R. Rev.3.00 Jan. 10, 2007 page 329 of 1038 REJ09B0328-0300 Internal bus TMRL1 TMRL2 Reloading register (8 bits) Acceleration Acceleration/ braking Section 16 Timer R RLD AC/BR Reloading Available/ not available CPS PS11, 10 Clock selection (2 bits) RLD/ CAP Reloading register (8 bits) RLCK Reloading clock selection TMRI2 Interrupt request braking Clock sources /4 /256 /512 R Down-counter Under(8 bits) flow TMRU-1 *2 TMRCP1 Clock source /64 /128 /256 Down-counter (8 bits) UnderTMRU-2 flow Capture register (8 bits) Q S CFG mask F/F Interrupting circuit CAPF Res SLW Res Resetting Available/ Not available Rev.3.00 Jan. 10, 2007 page 330 of 1038 REJ09B0328-0300 TMRI1 Interrupt request Underflow TMRCP2 Capture register (8 bits) *1 RQ S LAT Latch clock selection PS21,20 Clock selection (2 bits) TMRU-3 Down-counter (8 bits) TMRL3 Reloading register (8 bits) TMRI3 Interrupt request CP/ SLM CLR2 CFG External signals IRQ3 Clock sources /1024 /2048 /4096 Figure 16.1 Block Diagram of the Timer R Internal bus DVCTL Clock selection (2 bits) PS31, 30 Notes: 1. When the DVCTL is being used as the clock source, reloading will be made when the counter underflows and when the dividing clock is being used as the clock source, reloading will be made by the DVCTL. 2. When the LAT bit = 0, the capture signal against the TMRU-1 will not be output. Section 16 Timer R 16.1.3 Pin Configuration Table 16.1 shows the pin configuration of the Timer R. Table 16.1 Pin Configuration Name Input capture inputting pin Abbrev. IRQ3 I/O Input Function Input capture inputting for the Timer R 16.1.4 Register Configuration Table 16.2 shows the register configuration of the Timer R. Table 16.2 Register Configuration Name Timer R mode register 1 Timer R mode register 2 Abbrev. TMRM1 TMRM2 R/W R/W R/W R/W R R W W W Size Byte Byte Byte Byte Byte Byte Byte Byte Initial Value H'00 H'00 H'03 H'FF H'FF H'FF H'FF H'FF Address H'D118 H'D119 H'D11F H'D11A H'D11B H'D11C H'D11D H'D11E Timer R control/status register TMRCS Timer R capture register 1 Timer R capture register 2 Timer R load register 1 Timer R load register 2 Timer R load register 3 TMRCP1 TMRCP2 TMRL1 TMRL2 TMRL3 Note: Memories of respective registers will be preserved even under the low power consumption mode. Nonetheless, the CAPF flag and SLW flag of the TMRM2 will be cleared to 0. Rev.3.00 Jan. 10, 2007 page 331 of 1038 REJ09B0328-0300 Section 16 Timer R 16.2 16.2.1 Descriptions of Respective Registers Timer R Mode Register 1 (TMRM1) Bit : 7 CLR2 6 AC/BR 0 R/W 5 RLD 0 R/W 4 RLCK 0 R/W 3 PS21 0 R/W 2 PS20 0 R/W 1 RLD/CAP 0 R/W 0 CPS 0 R/W Initial value : R/W : 0 R/W The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register. When reset, the TMRM1 is initialized to H'00. Bit 7Selecting Clearing/Not Clearing of TMRU-2 (CLR2): This bit is used for selecting if the TMRU-2 counter reading is to be cleared or not as it is captured. Bit 7 CLR2 0 1 Description TMRU-2 counter reading is not to be cleared as soon as it is captured. (Initial value) TMRU-2 counter reading is to be cleared as soon as it is captured Bit 6Selecting the Acceleration/Braking Processing (AC/BR): This bit works to control occurrences of interrupt requests to detect completion of acceleration or braking while the capstan motor is making intermittent revolutions. For more information, see section 16.3.6, Acceleration and Braking Processes of the Capstan Motor. Bit 6 AC/BR 0 1 Description Acceleration Braking (Initial value) Rev.3.00 Jan. 10, 2007 page 332 of 1038 REJ09B0328-0300 Section 16 Timer R Bit 5Selection if Using the TMRU-2 for Reloading or Not Doing So (RLD): This bit is used for selecting if the TMRU-2 reload function is to be turned on or not. Bit 5 RLD 0 1 Description Not using the TMRU-2 as the reload timer Using the TMRU-2 as the reload timer (Initial value) Bit 4Selection of the Reloading Timing for the TMRU-2 (RLCK): This bit works to select if the TMRU-2 is reloading by the CFG or by underflowing of the TMRU-2 counter. This choice is valid only when the bit 5 (RLD) is being set to 1. Bit 4 RLCK 0 1 Description Reloading at the rising edge of the CFG Reloading by underflowing of the TMRU-2 (Initial value) Bits 3 and 2: Selecting the Clock Source for the TMRU-2 (PS21 and PS20): These bits work to select the inputting clock to the TMRU-2. Bit 3 PS21 0 Bit 2 PS20 0 1 1 0 1 Description Counting by underflowing of the TMRU-1 Counting by the PSS, /256 Counting by the PSS, /128 Counting by the PSS, /64 (Initial value) Bit 1Selection of the Operation Mode of the TMRU-1 (RLD/CAP): This bit works to select if the operation mode of the TMRU-1 is reload timer mode or capture timer mode. Under the capture timer mode, reloading operation will not be made. Also, the counter reading will be cleared as soon as capture has been made. Bit 1 RLD/CAP 0 1 Description The TMRU-1 works as the reloading timer The TMRU-1 works as the capture timer (Initial value) Rev.3.00 Jan. 10, 2007 page 333 of 1038 REJ09B0328-0300 Section 16 Timer R Bit 0Selection of the Capture Signals of the TMRU-1 (CPS): In combination with the LAT bit (Bit 7) of the TMR2, this bit works to select the capture signals of the TMRU-1. This bit becomes valid when the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set to 1. Nonetheless, it will be invalid when the RLD/CAP bit (Bit 1) is being set to 0. Bit 0 CPS 0 1 Description Capture signals at the rising edge of the CFG Capture signals at the edge of the IRQ3 (Initial value) 16.2.2 Timer R Mode Register 2 (TMRM2) Bit : 7 LAT 6 PS11 0 R/W 5 PS10 0 R/W 4 PS31 0 R/W 3 PS30 0 R/W 2 CP/SLM 0 R/W 1 CAPF 0 R/(W)* 0 SLW 0 R/(W)* Initial value : R/W : Note: * 0 R/W The CAPF bit and the SLW bit, respectively, works to latch the interrupt causes and writing 0 only is valid. Consequently, when these bits are being set to 1, respective interrupt requests will not be issued. Therefore, it is necessary to check these bits during the course of the interrupt processing routine to have them cleared. Also, priority is given to the set and, when an interrupt cause occur while the a clearing command (BCLR, MOV, etc.) is being executed, the CAPF bit and the SLW bit will not be cleared respectively and it thus becomes necessary to pay attention to the clearing timing. The timer R mode register 2 (TMRM2) is an 8-bit read/write register which works to identify the operation mode and to control the slow tracking processing. When reset, the TMRM2 is initialized to H'00. Rev.3.00 Jan. 10, 2007 page 334 of 1038 REJ09B0328-0300 Section 16 Timer R Bit 7Selection of the Capture Signals of the TMRU-2 (LAT): In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture signals of the TMRU-2. TMRM2 Bit 7 LAT 0 1 TMRM1 Bit 0 CPS * 0 1 Legend: * Don't care. Description Captures when the TMRU-3 underflows Captures at the rising edge of the CFG Captures at the edge of the IRQ3 (Initial value) Bits 6 and 5Selecting the Clock Source for the TMRU-1 (PS11 and PS10): These bits work to select the inputting clock to the TMRU-1. Bit 6 PS11 0 Bit 5 PS10 0 1 1 0 1 Description Counting at the rising edge of the CFG Counting by the PSS, /4 Counting by the PSS, /256 Counting by the PSS, /512 (Initial value) Bits 4 and 3Selecting the Clock Source for the TMRU-3 (PS31 and PS30): These bits work to select the inputting clock to the TMRU-3. Bit 4 PS31 0 Bit 3 PS30 0 1 1 0 1 Description Counting at the rising edge of the DVCTL from the dividing circuit. (Initial value) Counting by the PSS, /4096 Counting by the PSS, /2048 Counting by the PSS, /1024 Rev.3.00 Jan. 10, 2007 page 335 of 1038 REJ09B0328-0300 Section 16 Timer R Bit 2Selection of Interrupt Causes (CP/SLM): This bit works to select the interrupt causes for the TMRI3. Bit 2 CP/SLM 0 1 Description Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value) Makes interrupt requests upon ending of the slow tracking mono-multi valid Bit 1Capture Signal Flag (CAPF): This is a flag being set out by the capture signal of the TMRU-2. Although both reading/writing are possible, 0 only is valid for writing. Also, priority is being given to the set and, when the "capture signal" and "writing 0" occur simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and it is necessary to be attentive about this fact. When the CP/SLM bit (Bit 2) is being set to 1, this CAPF bit should always be set to 0. The CAPF flag is cleared to 0 under the low power consumption mode. Bit 1 CAPF 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] At occurrences of the TMRU-2 capture signals while the CP/SLM bit is being set to 0 (Initial value) Bit 0Slow Tracking Mono-Multi Flag (SLW): This is a flag being set out when the slow tracking mono-multi processing ends. Although both reading/writing are possible, 0 only is valid for writing. Also, priority is being given to the set and, when "ending of the slow tracking mono-multi processing" and "writing 0" occur simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and it is necessary to be attentive about this fact. When the CP/SLM bit (Bit 2) is being set to 0, this SLW bit should always be set to 0. The SLW flag is cleared to 0 under the low power consumption mode. Bit 0 SLW 0 1 Description [Clearing condition] When 0 is written after reading 1 (Initial value) [Setting condition] When the slow tracking mono-multi processing ends while the CP/SLM bit is being set to 1 Rev.3.00 Jan. 10, 2007 page 336 of 1038 REJ09B0328-0300 Section 16 Timer R 16.2.3 Timer R Control/Status Register (TMRCS) Bit : 7 TMRI3E 6 TMRI2E 0 5 TMRI1E 0 4 TMRI3 0 R/(W)* 3 TMRI2 0 R/(W)* 2 TMRI1 0 R/(W)* 1 -- 1 -- 0 -- 1 -- Initial value : 0 R/W R/W R/W R/W : Note: * Only 0 can be written to clear the flag. The timer R control/status register (TMRCS) works to control the interrupts of the Timer R. The TMRCS is an 8-bit read/write register. When reset, the TMRCS is initialized to H'03. Bit 7Enabling the TMRI3 Interrupt (TMRI3E): This bit works to permit/prohibit occurrence of the TMRI3 interrupt when an interrupt cause being selected by the CP/SLM bit of the TMRM2 has occurred, such as occurrences of the TMRU-2 capture signals or when the slow tracking mono-multi processing ends, and the TMRI3 has been set to 1. Bit 7 TMRI3E 0 1 Description Prohibits occurrences of TMRI3 interrupts Permits occurrences of TMRI3 interrupts (Initial value) Bit 6Enabling the TMRI2 Interrupt (TMRI2E): This bit works to permit/prohibit occurrence of the TMRI2 interrupt when the TMRI2 has been set to 1 by issuance of the underflow signal of the TMRU-2 or by ending of the slow tracking mono-multi processing. Bit 6 TMRI2E 0 1 Description Prohibits occurrences of TMRI2 interrupts Permits occurrences of TMRI2 interrupts (Initial value) Rev.3.00 Jan. 10, 2007 page 337 of 1038 REJ09B0328-0300 Section 16 Timer R Bit 5Enabling the TMRI1 Interrupt (TMRI1E): This bit works to permit/prohibit occurrence of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of the TMRU-1. Bit 5 TMRI1E 0 1 Description Prohibits occurrences of TMRI1 interrupts Permits occurrences of TMRI1 interrupts (Initial value) Bit 4TMRI3 Interrupt Requesting Flag (TMRI3): This is the TMRI3 interrupt requesting flag. It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2, such as occurrences of the TMRU-2 capture signals or ending of the slow tracking mono-multi processing. Bit 4 TMRI3 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] At occurrence of the interrupt cause being selected by the CP/SLM bit of the TMRM2 (Initial value) Bit 3TMRI2 Interrupt Requesting Flag (TMRI2): This is the TMRI2 interrupt requesting flag. It indicates occurrences of the TMRU-2 underflow signals or ending of the acceleration/braking processing of the capstan motor. Bit 3 TMRI2 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] At occurrences of the TMRU-2 underflow signals or ending of the acceleration/ braking processing of the capstan motor (Initial value) Rev.3.00 Jan. 10, 2007 page 338 of 1038 REJ09B0328-0300 Section 16 Timer R Bit 2TMRI1 Interrupt Requesting Flag (TMRI1): This is the TMRI1 interrupt requesting flag. It indicates occurrences of the TMRU-1 underflow signals. Bit 2 TMRI1 0 1 Description [Clearing condition] When 0 is written after reading 1. [Setting condition] When the TMRU-1 underflows. (Initial value) Bits 1 and 0Reserved: When they are read, 1 will always be readout. Writes are disabled. 16.2.4 Timer R Capture Register 1 (TMRCP1) Bit : 7 6 5 4 3 2 1 0 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 Initial value : R/W : 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R The timer R capture register 1 (TMRCP1) works to store the capture data of the TMRU-1. During the course of the capturing operation, the TMRU-1 counter readings are captured by the TMRCP1 at the CFG edge or the IRQ3 edge. The capturing operation of the TMRU-1 is being performed using 16 bits, in combination with the capturing operation of the TMRU-2. The TMRCP1 is an 8-bit read only register. When reset, the TMRCS is initialized to H'FF. Notes: 1. When the TMRCP1 is readout while the capture signal is being received, the reading data become unstable. Pay attention to the timing for reading out. 2. When a shift to the low power consumption mode is made while the capturing operating is in progress, the counter reading becomes unstable. After returning to the active mode, always write "H'FF" into the TMRL1 to initialize the counter. Rev.3.00 Jan. 10, 2007 page 339 of 1038 REJ09B0328-0300 Section 16 Timer R 16.2.5 Timer R Capture Register 2 (TMRCP2) Bit : 7 6 5 4 3 2 1 0 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : R/W : 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter readings are captured by the TMRCP2. The TMRCP2 is an 8-bit read only register. When reset, the TMRCS will be initialized into H'FF. Notes: 1. When the TMRCP2 is readout while the capture signal is being received, the reading data become unstable. Pay attention to the timing for reading out. 2. When a shift to the low power consumption mode is made, the counter reading becomes unstable. After returning to the active mode, always write "H'FF" into the TMRL2 to initialize the counter. 16.2.6 Timer R Load Register 1 (TMRL1) Bit : 7 TMR17 Initial value : R/W : 1 W 6 TMR16 1 W 5 TMR15 1 W 4 TMR14 1 W 3 TMR13 1 W 2 TMR12 1 W 1 TMR11 1 W 0 TMR10 1 W The timer R load register 1 (TMRL1) is an 8-bit write only register which works to set the load value of the TMRU-1. When a load value is set to the TMRL1, the same value will be set to the TMRU-1 counter simultaneously and the counter starts counting down from the set value. Also, when the counter underflows during the course of the reload timer operation, the TMRL1 value will be set to the counter. When reset, the TMRL1 is initialized to H'FF. Rev.3.00 Jan. 10, 2007 page 340 of 1038 REJ09B0328-0300 Section 16 Timer R 16.2.7 Timer R Load Register 2 (TMRL2) Bit : 7 TMR27 6 TMR26 1 W 5 TMR25 1 W 4 TMR24 1 W 3 TMR23 1 W 2 TMR22 1 W 1 TMR21 1 W 0 TMR20 1 W Initial value : R/W : 1 W The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load value of the TMRU-2. When a load value is set to the TMRL2, the same value will be set to the TMRU-2 counter simultaneously and the counter starts counting down from the set value. Also, when the counter underflows or a CFG edge is detected during the course of the reload timer operation, the TMRL2 value will be set to the counter. When reset, the TMRL2 is initialized to H'FF. 16.2.8 Timer R Load Register 3 (TMRL3) Bit : 7 TMR37 Initial value : R/W : 1 W 6 TMR36 1 W 5 TMR35 1 W 4 TMR34 1 W 3 TMR33 1 W 2 TMR32 1 W 1 TMR31 1 W 0 TMR30 1 W The timer R load register 3 (TMRL3) is an 8-bit write only register which works to set the load value of the TMRU-3. When a load value is set to the TMRL3, the same value will be set to the TMRU-3 counter simultaneously and the counter starts counting down from the set value. Also, when the counter underflows or a DVCTL edge is detected, the TMRL2 value will be set to the counter. (Reloading will be made by the underflowing signals when the DVCTL signal is selected as the clock source, and reloading will be made by the DVCTL signals when the dividing clock is selected as the clock source.) When reset, the TMRL3 is initialized to H'FF. Rev.3.00 Jan. 10, 2007 page 341 of 1038 REJ09B0328-0300 Section 16 Timer R 16.2.9 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP11 bit is set to 1, the Timer R stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 3Module Stop (MSTP11): This bit works to designate the module stop mode for the Timer R. MSTPCRH Bit 3 MSTP11 0 1 Description Cancels the module stop mode of the Timer R Sets the module stop mode of the Timer R (Initial value) Rev.3.00 Jan. 10, 2007 page 342 of 1038 REJ09B0328-0300 Section 16 Timer R 16.3 16.3.1 Operation Reload Timer Counter Equipped with Capturing Function TMRU-1 The reload timer counter equipped with capturing function, TMRU-1, consists of an 8-bit downcounter, a reloading register and a capture register. The clock source can be selected from among the leading edge of the CFG signals and three types of dividing clocks. It is also selectable whether using it as a reload counter or as a capture counter. Even when the capturing function is selected, the counter readings can be updated by writing the values into the reloading register. When the counter underflows, the TMRI1 interrupt request will be issued. The initial values of the TMRU-1 counter, reloading register and capturing register are all H'FF. (1) Operation of the Reload Timer When a value is written into to the reloading register, the same value will be written into the counter simultaneously. Also, when the counter underflows, the reloading register value will be reloaded to the counter. The TMRU-1 is a dividing circuit for the CFG. In combination with the TMRU-2 and TMRU-3, it can also be used for the mode identification purpose. (2) Capturing Operation Capturing operation is carried out in combination with the TMRU-2 using the combined 16 bits. It can be so programmed that the counter may be cleared by the capture signal. The CFG edges or IRQ3 edges are used as the capture signals. It is possible to issue the TMRI3 interrupt request by the capture signal. In addition to the capturing function being worked out in combination with the TMRU-2, the TMRU-1 can be used as a 16-bit CFG counter. Selecting the IRQ3 as the capture signal, the CFG within the duration of the reel pulse being input into the IRQ3 pin can be counted by the TMRU-1. Rev.3.00 Jan. 10, 2007 page 343 of 1038 REJ09B0328-0300 Section 16 Timer R 16.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 The reload timer counter equipped with capturing function, TMRU-2, consists of an 8-bit downcounter, a reloading register and a capture register. The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three types of dividing clocks. Also, although the reloading function is workable during its capturing operation, equipping or not of the reloading function is selectable. Even when without-reloadingfunction is chosen, the counter reading can be updated by writing the values to the reloading register. When the counter underflows, the TMRI2 interrupt request will be issued. The initial values of the TMRU-2 counter, reloading register and capturing register are all H'FF. (1) Operation of the Reload Timer When a value is written into to the reloading register, the same value will be written into the counter, simultaneously. Also, when the counter underflows, the reloading register value will be reloaded to the counter. The TMRU-2 can make acceleration and braking work for the capstan motor using the reload timer operation. (2) Capturing Operation Using the capture signals, the counter reading can be latched into the capturing register. As the capture signal, you can choose from among edges of the CFG, edges of the IRQ3 or the underflow signals of the TMRU-3. It is possible to issue the TMRI3 interrupt request by the capture signal. The capturing function (stopping the reloading function) of the TMRU-2, in combination with the TMRU-1 and TMRU-3, can also be used for the mode identification purpose. 16.3.3 Reload Counter Timer TMRU-3 The reload counter timer TMRU-3 consists of an 8-bit down-counter and a reloading register. Its clock source can be selected from between the undedrflowing signal of the counter and the edges of the DVCTL signals. (When the DVCTL signal is selected as the clock source, reloading will be effected by the underflowing signals and when the dividing clock is selected as the clock source, reloading will be effected by the DVCTL signals.) The reloading signal works to reload the reloading register value into the counter. Also, when a value is written into to the reloading register, the same value will be written into the counter, simultaneously. The initial values of the counter and the reloading register are H'FF. The underflowing signals can be used as the capturing signal for the TMRU-2. The TMRU-3 can also be used as a dividing circuit for the DVCTL. Also, in combination with the TMRU-1 and TMRU-2 (capturing function), the TMRU-3 can be used for the mode identification Rev.3.00 Jan. 10, 2007 page 344 of 1038 REJ09B0328-0300 Section 16 Timer R purpose. Since the divided signals of the DVCTL are being used as the clock source, CTL signals (DVCTL) conforming to the double speed can be input when making searches. These DVCTL signals can also be used for phase controls of the capstan motor. Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the edges of the DVCTL to provide the slow tracking mono-multi function. 16.3.4 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used. The Timer R will become to the aforementioned status after a reset. Under the aforementioned status, the divided CFG should be written into the reloading register of the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU-3. When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing register value represents the number of the CFG within the DVCTL cycle. As aforementioned, the Timer R can work to count the number of the CFG corresponding to "n" times of DVCTL's or to identify the mode being searched. For exemplary settings for the register, see section 16.5.1, Mode Identification. 16.3.5 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the IRQ3 pin, reeling controls, etc. can be effected. For exemplary settings for the register, see section 16.5.2, Reeling Controls. 16.3.6 Acceleration and Braking Processes of the Capstan Motor When making intermittent movements such as those for slow reproductions or for still reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan motor. The acceleration and braking processes will function to check if the revolution of a capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2 (reloading function) should be used. When making accelerations: (1) Set the AC/BR bit of the TMRM1 to acceleration. (Set to 1). Also, use the rising edge of the CFG as the reloading signal. Rev.3.00 Jan. 10, 2007 page 345 of 1038 REJ09B0328-0300 Section 16 Timer R (2) Set the prescribed time on the CFG frequency to deem as the acceleration has been finished, into the reloading register. (3) The TMRU-2 will work to down-count the reloading data. (4) In case the acceleration has not been finished (in case the CFG signal is not input even when the prescribed time has elapsed = underflowing of down-counting has occurred), such underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be cleared by the CFG. (5) When the acceleration has been finished (when the CFG signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), an interrupt request will be issued because of the CFG. When making breaking: (1) Set the AC/BR bit of the TMRM1 to braking. (Clear to 0). Also, use the rising edge of the CFG as the reloading signal. (2) Set the prescribed time on the CFG frequency to deem as the braking has been finished, into the reloading register. (3) The TMRU-2 will work to down-count the reloading data. (4) In case the braking has not been finished (when the CFG signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), the reload timer movement will continue. (5) When the acceleration has been finished (when the CFG signal is not input even when the prescribed time has elapsed = underflowing of down-counting has occurred), interrupt request will be issued because of the underflowing signal. The acceleration and braking processes should be employed when making special reproductions, in combination with the slow tracking mono-multi function being outlined below. For exemplary settings for the register, see section 16.5.4, Acceleration and Braking Processes of the Capstan Motor. 16.3.7 Slow Tracking Mono-Multi Function When performing slow reproductions or still reproductions, the braking timing for the capstan motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi function works to measure the time from the rising edge of the DVCTL signal down to the desired point to issue the interrupt request. In actual programming, this interrupt should be used to activate the brake of the capstan motor. The TMRU-3 should be used to perform time measurements for the slow tracking mono-multi function. Also, the braking process can be made using the TMRU-2. Figure 16.2 below shows the exemplary time series movements when a slow reproduction is being Rev.3.00 Jan. 10, 2007 page 346 of 1038 REJ09B0328-0300 Section 16 Timer R performed. For exemplary settings for the register, see section 16.5.3, Slow Tracking Mono-Multi Function. Compensation for vertical vibrations (Supplementary V-pulse) HSW FG acceleration detection Accelerating the capstan motor Acceleration process Hi-Z DVCTL Interrupt Slow tracking moto-multi Slow tracking delay Reverse rotation Forward rotation Reloading FG stopping detection Braking the capstan motor Braking process Braking the drum motor Servo Compensation for horizontal vibrations Compensation for horizontal vibrations Frame feeds H.AmpSW C.Rotary In case of 4-head SP mode. In case of 2-head application, H.AmpSW and C.Rotary should be "Low". Legend: Hi-Z : High impedance state Figure 16.2 Exemplary Time Series Movements when a Slow Reproduction Is Being Performed Rev.3.00 Jan. 10, 2007 page 347 of 1038 REJ09B0328-0300 Section 16 Timer R 16.4 Interrupt Cause The interrupt causes for the Timer R are 3-causes of the TMRI3 bit through TMRI1 bit of the timer R control/status register (TMRCS). (a) Interrupts being caused by the underflowing of the TMRU-1 (TMRI1) These interrupts will constitute the timing for reloading with the TMRU-1. (b) Interrupts being caused by the underflowing of the TMRU-2 or by an end of the acceleration or braking process (TMRI2) When interrupts occur at the reload timing of the TMRU-2, clear the AC/BR (acceleration/braking) bit of the timer R mode register 1 (TMRM1) to 0. (c) Interrupts being caused by the capture signals of the TMRU-3 and by ending the slow tracking mono-multi process (TMRI3) Since these two interrupt causes are constituting the OR, it becomes necessary to determine which interrupt cause is occurring using the software. Respective interrupt causes are being set to the CAPF flag or the SLW flag of the timer R mode register 2 (TMRM2), have the software determine which. Since the CAPF flag and the SLW flag will not be cleared automatically, program the software to clear them. (Writing 0 only is valid for these flags.) Unless these flags are cleared, detection of the next cause becomes unworkable. Also, if the CP/SLM bit is changed leaving these flags un-cleared as they are, these flags will get cleared. Rev.3.00 Jan. 10, 2007 page 348 of 1038 REJ09B0328-0300 Section 16 Timer R 16.5 16.5.1 Exemplary Settings for Respective Functions Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used. The Timer R will become to the aforementioned status after a reset. Under the aforementioned status, the divided CFG should be written into the reloading register of the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU-3. When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing register value represents the number of the CFG within the DVCTL cycle. As aforementioned, the Timer R can work to count the number of the CFG corresponding to "n" times of DVCTL's or to identify the mode being searched. * Exemplary settings (1) Setting the timer R mode register 1 (TMRM1) CLR2 bit (Bit 7) = 1: Works to clear after making the TMRU-2 capture. RLD bit (Bit 5) = 0: Sets the TMRU-3 without reloading function. PS21 and PS20 (Bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to be used as the clock source for the TMRU-2. RLD/CAP bit (Bit 1) = 0: The TMRU-1 has been set to make the reload timer operation. (2) Setting the timer R mode register 2 (TMRM2) LAT bit (Bit 7) = 0: The underflowing signals of the TMRU-3 are to be used as the capture signal for the TMRU-2. PS11 and PS10 (Bits 6 and 5) = (0 and 0): The leading edge of the CFG signal is to be used as the clock source for the TMRU-1. PS31 and PS30 (Bits 4 and 3) = (0 and 0): The leading edge of the DVCTL signal is to be used as the clock source for the TMRU-3. CP/SLM bit (Bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request. (3) Setting the timer R load register 1 (TMRL1) Set the dividing value for the CFG. The set value should become (n - 1) when divided by "n". (4) Setting the timer R load register 3 (TMRL3) Set the dividing value for the DVCTL. The set value should become (n - 1) when divided by "n". Rev.3.00 Jan. 10, 2007 page 349 of 1038 REJ09B0328-0300 Section 16 Timer R 16.5.2 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the IRQ3 pin, reeling controls, etc. can be effected. * Exemplary settings (1) Setting P13/IRQ3 pin as the IRQ3 pin Set the PMR13 bit (Bit 3) of the port mode register 1 (PMR1) to 1. See section 22.2.3, Port Mode Register 1 (PMR1). (2) Setting the timer R mode register 1 (TMRM1) CLR2 bit (Bit 7) = 1: Works to clear after making the TMRU-2 capture. PS21 and PS20 (Bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to be used as the clock source for the TMRU-2. RLD/CAP bit (Bit 1) = 1: The TMRU-1 has been set to make the capturing operation. CPS bit (Bit 0) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the TMRU-1 and TMRU-2. (3) Setting the timer R mode register 2 (TMRM2) LAT bit (Bit 7) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the TMRU-1 and TMRU-2. PS11 and PS10 (Bits 6 and 5) = (0 and 0): The rising edge of the CFG signal is to be used as the clock source for the TMRU-1. CP/SLM bit (Bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request. 16.5.3 Slow Tracking Mono-Multi Function When performing slow reproductions or still reproductions, the braking timing for the capstan motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi function works to measure the time from the leading edge of the DVCTL signal down to the desired point to issue the interrupt request. In actual programming, this interrupt should be used to activate the brake of the capstan motor. The TMRU-3 should be used to perform time measurements for the slow tracking mono-multi function. Also, the braking process can be made using the TMRU-2. * Exemplary settings (1) Setting the timer R mode register 2 (TMRM2) PS31 and PS30 (Bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-3. Rev.3.00 Jan. 10, 2007 page 350 of 1038 REJ09B0328-0300 Section 16 Timer R CP/SLM bit (Bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3 interrupt request. (2) Setting the timer R load register 3 (TMRL3) Set the slow tracking delay value. When the delay count is "n", the set value should be (n - 1). Regarding the delaying duration, see figure 16.2 Exemplary time series movements when a slow reproduction is being performed. 16.5.4 Acceleration and Braking Processes of the Capstan Motor When making intermittent movements such as those for slow reproductions or for still reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan motor. The acceleration and braking processes will function to check if the revolution of a capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2 (reloading function) should be used. The acceleration and braking processes should be employed when making special reproductions, in combination with the slow tracking mono-multi function. * Exemplary settings for the acceleration process (1) Setting the timer R mode register 1 (TMRM1) AC/BR bit (Bit 6) = 1: Acceleration process RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer. RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG. PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-2. (2) Setting the timer R load register 2 (TMRL2) Set the count reading for the duration until the acceleration process finishes. When the count is "n", the set value should be (n - 1). Regarding the duration until the acceleration process finishes, see figure 16.2 Exemplary time series movements when a slow reproduction is being performed. * Exemplary settings for the braking process (1) Setting the timer R mode register 1 (TMRM1) AC/BR bit (Bit 6) = 0: Braking process RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer. RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG. PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-2. Rev.3.00 Jan. 10, 2007 page 351 of 1038 REJ09B0328-0300 Section 16 Timer R (2) Setting the timer R load register 2 (TMRL2) Set the count reading for the duration until the braking process finishes. When the count is "n", the set value should be (n - 1). Regarding the duration until the braking process finishes, see figure 16.2 Exemplary time series movements when a slow reproduction is being performed. Rev.3.00 Jan. 10, 2007 page 352 of 1038 REJ09B0328-0300 Section 17 Timer X1 Section 17 Timer X1 17.1 Overview The Timer X1 is capable of outputting two different types of independent waveforms using the free running counter (FRC) as the basic means and it is also applicable to measurements of the durations of input pulses and the cycles external clocks. 17.1.1 Features Listed below are the features of the Timer X1. * Choices of 4 different types of counter inputting clocks are available for your selection. You can select from among three different types of internal clocks (/4, /16, and /64) and the DVCFG. * Two independent output comparing functions Capable of outputting two different types of independent waveforms. * Four independent input capturing functions The rising edge or falling edge can be selected for use. The buffer operation can also be designated. * Counter clearing designation is workable. The counter readings can be cleared by compare match A. * Seven types of interrupt causes Comparing match x 2 causes, input capture x 4 causes, and overflow x 1 cause are available for use and they can make respective interrupt requests independently. 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the Timer X1. Rev.3.00 Jan. 10, 2007 page 353 of 1038 REJ09B0328-0300 Section 17 Timer X1 FTIA* (HSW) FTIB* (VD) FTIC* (DVCTL) FTID* (NHSW) ICRA Input capture control ICRB ICRC ICRD TCRX OCRB Comparison circuit FRC (DVCFG) /4 /16 /64 Output comparing output FTOA FTOB Comparison circuit OCRA TOCR TCSRX TIER Interrupt request x 7 Legend: TIER : Timer interrupt enabling register TCSRX : Timer control/status register X FRC : Free running counter OCRA : Output comparing register A OCRB : Output comparing register B TCRX : Timer control register X TOCR : Output comparing control register ICRA : Input capture register A ICRB : Input capture register B ICRC : Input capture register C ICRD : Input capture register D Note: * stands for the external terminal. ( ) stands for the internal signal. Figure 17.1 Block Diagram of the Timer X1 Rev.3.00 Jan. 10, 2007 page 354 of 1038 REJ09B0328-0300 Internal data bus Section 17 Timer X1 17.1.3 Pin Configuration Table 17.1 shows the pin configuration of the Timer X1. Table 17.1 Pin Configuration Name Output comparing A output-pin Output comparing B output-pin Input capture A input-pin Input capture B input-pin Input capture C input-pin Input capture D input-pin Abbrev. FTOA FTOB FTIA FTIB FTIC FTID I/O Output Output Input Input Input Input Function Output pin for the output comparing A Output pin for the output comparing B Input-pin for the input capture A Input-pin for the input capture B Input-pin for the input capture C Input-pin for the input capture D Rev.3.00 Jan. 10, 2007 page 355 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.1.4 Register Configuration Table 17.2 shows the register configuration of the Timer X1. Table 17.2 Register Configuration Name Timer interrupt enabling register Timer control/status register X Free running counter H Free running counter L Output comparing register AH Output comparing register AL Output comparing register BH Output comparing register BL Timer control register X Timer output comparing control register Input capture register AH Input capture register AL Input capture register BH Input capture register BL Input capture register CH Input capture register CL Input capture register DH Input capture register DL Abbrev. TIER TCSRX FRCH FRCL OCRAH OCRAL OCRBH OCRBL TCRX TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL R/W R/W R/ (W)* R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R 1 3 Initial Value Address* H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'D100 H'D101 H'D102 H'D103 H'D104* 2 H'D105* 2 H'D104* 2 H'D105* 2 H'D106 H'D107 H'D108 H'D109 H'D10A H'D10B H'D10C H'D10D H'D10E H'D10F Notes: 1. Only 0 can be written to clear the flag for Bits 7 to 1. Bit 0 is readable/writable. 2. The addresses of the OCRA and OCRB are the same. Changeover between them are to be made by use of the TOCR bit and OCRS bit. 3. Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 356 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.2 17.2.1 Descriptions of Respective Registers Free Running Counter (FRC) Free running counter H (FRCH) Free running counter L (FRCL) FRC Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRCH FRCL The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external clock. The inputting clock is to be selected from the CKS1 and CKS0 of the TCRX. By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A. When the FRC overflows (H'FFFF H'0000), the OVF of the TCSRX will be set to 1. At this time, when the OVIE of the TIER is being set to 1, an interrupt request will be issued to the CPU. Reading/writing can be made from and to the FRC through the CPU at 8-bit or 16-bit. The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. 17.2.2 Output Comparing Register A and B (OCRA and OCRB) Output comparing register AH and BH (OCRAH and OCRBH) Output comparing register AL and BL (OCRAL and OCRBL) OCRA, OCRB Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAH, OCRBH OCRAL, OCRBL The OCR consists of twin 8-bit read/write registers (OCRA and OCRB). The contents of the OCR are always being compared with the FRC and, when the value of these two match, the OCFA and OCRB of the TCSRX will be set to 1. At this time, if the OCIAE and OCIB of the TIER are being set to 1, an interrupt request will be issued to the CPU. Rev.3.00 Jan. 10, 2007 page 357 of 1038 REJ09B0328-0300 Section 17 Timer X1 When performing compare matching, if the OEA and OEB of the TOCR are being set to 1, the level value having been set to the OLVLA and OLVLB of the TOCR will be output through the FTOA and FTOB pins. After resetting, 0 will be output through the FTOA and FTOB pins until the first compare matching occurs. Reading/writing can be made from and to the OCR through the CPU at 8-bit or 16-bit. The OCR is cleared to H'FFFF when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. 17.2.3 Input Capture Register A Through D (ICRA Through ICRD) Input capture register AH to DH (ICRAH to ICRDH) Input capture register AL to DL (ICRAL to ICRDL) ICRA, ICRB, ICRC, ICRD Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL The ICR consists of four 16-bit read only registers (ICRA through ICRD). When the falling edge of the input capture input signal is detected, the value is transferred to the ICRA through ICRD. At this time, the ICFA through ICFD of the TCSRX are set to 1 simultaneously. At this time, if the IDIAE through IDIDE of the TCRX are all being set to 1, due interrupt request will be issued to the CPU. The edge of the input signal can be selected by setting the IEDGA through IEDGD of the TCRX. Also, the ICRC and ICRD can be used as the buffer register, respectively, of the ICRA and ICRB by setting the BUFEA and BUFEB of the TCRX to perform buffer operations. Figure 17.2 shows the connections necessary when using the ICRC as the buffer register of the ICRA. (BUFEA = 1) When the ICRC is used as the buffer of the ICRA, by setting IEDGA IEDGC, both of the rising and falling edges can be designated for use. In case of IEDGA = IEDGC, either one of the rising edge or the falling edge only is usable. Regarding selection of the input signal edge, see table 17.3. Note: Transference from the FRC to the ICR will be performed regardless of the value of the ICF. Rev.3.00 Jan. 10, 2007 page 358 of 1038 REJ09B0328-0300 Section 17 Timer X1 IEDGA BUFEA IEDGC FTIA Edge detection and capture signal generating circuit. ICRC ICRA FRC Figure 17.2 Buffer Operation (an Example) Table 17.3 Input Signal Edge Selection when Making Buffer Operation IEDGA 0 IEDGC 0 1 1 0 1 Captures at the rising edge of the input capture input A Selection of the Input Signal Edge Captures at the rising edge of the input capture input A (Initial value) Captures at both rising and falling edges of the input capture input A Reading can be made from the ICR through the CPU at 8-bit or 16-bit. For stable input capturing operation, maintain the pulse duration of the input capture input signals at 1.5 system clock () or more in case of single edge capturing and at 2.5 system clock () or more in case of both edge capturing. The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep mode, module stop mode, or subactive mode. Rev.3.00 Jan. 10, 2007 page 359 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.2.4 Timer Interrupt Enabling Register (TIER) Bit : 7 ICIAE 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 ICSA 0 R/W Initial value : R/W : 0 R/W The TIER is an 8-bit read/write register which works to control permission/prohibition of respective interrupt requests. The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Bit 7Enabling the Input Capture Interrupt A (ICIAE): This bit works to permit/prohibit interrupt requests (ICIA) by the ICFA when the ICFA of the TCSRX is being set to 1. Bit 7 ICIAE 0 1 Description Prohibits interrupt requests (ICIA) by the ICFA Permits interrupt requests (ICIA) by the ICFA (Initial value) Bit 6Enabling the Input Capture Interrupt B (ICIBE): This bit works to permit/prohibit interrupt requests (ICIB) by the ICFB when the ICFB of the TCSRX is being set to 1. Bit 6 ICIBE 0 1 Description Prohibits interrupt requests (ICIB) by the ICFB Permits interrupt requests (ICIB) by the ICFB (Initial value) Bit 5Enabling the Input Capture Interrupt C (ICICE): This bit works to permit/prohibit interrupt requests (ICIC) by the ICFC when the ICFC of the TCSRX is being set to 1. Bit 5 ICICE 0 1 Description Prohibits interrupt requests (ICIC) by the ICFC Permits interrupt requests (ICIC) by the ICFC (Initial value) Rev.3.00 Jan. 10, 2007 page 360 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 4Enabling the Input Capture Interrupt D (ICIDE): This bit works to permit/prohibit interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1. Bit 4 ICIDE 0 1 Description Prohibits interrupt requests (ICID) by the ICFD Permits interrupt requests (ICID) by the ICFD (Initial value) Bit 3Enabling the Output Comparing Interrupt A (OCIAE): This bit works to permit/prohibit interrupt requests (OCIA) by the OCFA when the OCFA of the TCSRX is being set to 1. Bit 3 OCIAE 0 1 Description Prohibits interrupt requests (OCIA) by the OCFA Permits interrupt requests (OCIA) by the OCFA (Initial value) Bit 2Enabling the Output Comparing Interrupt B (OCIBE): This bit works to permit/prohibit interrupt requests (OCIB) by the OCFB when the OCFB of the TCSRX is being set to 1. Bit 2 OCIBE 0 1 Description Prohibits interrupt requests (OCIB) by the OCFB Permits interrupt requests (OCIB) by the OCFB (Initial value) Bit 1Enabling the Timer Overflow Interrupt (OVIE): This bit works to permit/prohibit interrupt requests (FOVI) by the OVF when the OVF of the TCSRX is being set to 1. Bit 1 OVIE 0 1 Description Prohibits interrupt requests (FOVI) by the OVF Permits interrupt requests (FOVI) by the OVF (Initial value) Rev.3.00 Jan. 10, 2007 page 361 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 0Selecting the Input Capture A Signals (ICSA): This bit works to select the input capture A signals. Bit 0 ICSA 0 1 Description Selects the FTIA pin for inputting of the input capture A signals Selects the HSW for inputting of the input capture A signals (Initial value) 17.2.5 Timer Control/Status Register X (TCSRX) Bit : 7 ICFA 6 ICFB 0 5 ICFC 0 4 ICFD 0 3 OCFA 0 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W Initial value : 0 R/(W)* R/(W)* R/(W)* R/(W)* R/W : R/(W)* Note: * Only 0 can be written to clear the flag for bits 7 to 1. The TCSRX is an 8-bit register which works to select counter clearing timing and to control respective interrupt requesting signals. The TCSRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Meanwhile, as for the timing, see section 17.3, Operation. The FTIA through FTID pins are for fixed inputs inside the LSI under the low power consumption mode excluding the sleep mode. Consequently, when such shifts as "active mode low power consumption mode active mode" are made, wrong edges may be detected depending on the pin status or on the type of the detecting edge. To avoid such error, clear the interrupt requesting flag once immediately after shifting to the active mode from the low power consumption mode. Rev.3.00 Jan. 10, 2007 page 362 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 7Input Capture Flag A (ICFA): This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRA by the input capture signals. When the BUFEA of the TCRX is being set to 1, the ICFA indicates the status that the FRC value has been transferred to the ICRA by the input capture signals and that the ICRA value before being updated has been transferred to the ICRC. This flag should be cleared by use of of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 7 ICFA 0 1 Description [Clearing condition] [Setting condition] When the value of the FRC has been transferred to the ICRA by the input capture signals (Initial value) When 0 is written into the ICFA after reading the ICFA under the setting of ICFA = 1 Bit 6Input Capture Flag B (ICFB): This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRB by the input capture signals. When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value has been transferred to the ICRB by the input capture signals and that the ICRB value before being updated has been transferred to the ICRC. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 6 ICFB 0 1 Description [Clearing condition] [Setting condition] When the value of the FRC has been transferred to the ICRB by the input capture signals (Initial value) When 0 is written into the ICFB after reading the ICFB under the setting of ICFB = 1 Rev.3.00 Jan. 10, 2007 page 363 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 5Input Capture Flag C (ICFC): This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRC by the input capture signals. When an input capture signal occurs while the BUFEA of the TCRX is being set to 1, although the ICFC will be set out, data transference to the ICRC will not be performed. Therefore, in buffer operation, the ICFC can be used as an external interrupt by setting the ICICE bit to 1. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 5 ICFC 0 1 Description [Clearing condition] [Setting condition] When the input capture signal has occurred (Initial value) When 0 is written into the ICFC after reading the ICFC under the setting of ICFC = 1 Bit 4Input Capture Flag D (ICFD): This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRD by the input capture signals. When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the ICFD will be set out, data transference to the ICRD will not be performed. Therefore, in buffer operation, the ICFD can be used as an external interrupt by setting the ICIDE bit to 1. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 4 ICFD 0 1 Description [Clearing condition] [Setting condition] When the input capture signal has occurred (Initial value) When 0 is written into the ICFD after reading the ICFD under the setting of ICFD = 1 Rev.3.00 Jan. 10, 2007 page 364 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 3Output Comparing Flag A (OCFA): This is a status flag indicating the fact that the FRC and the OCRA have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 3 OCFA 0 Description [Clearing condition] (Initial value) When 0 is written into the OCFA after reading the OCFA under the setting of OCFA = 1 1 [Setting condition] When the FRC and the OCRA have come to the comparing match Bit 2Output Comparing Flag B (OCFB): This is a status flag indicating the fact that the FRC and the OCRB have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 2 OCFB 0 Description [Clearing condition] (Initial value) When 0 is written into the OCFB after reading the OCFB under the setting of OCFB = 1 1 [Setting condition] When the FRC and the OCRB have come to the comparing match Bit 1Time Over Flow (OVF): This is a status flag indicating the fact that the FRC overflowed. (H'FFFF H'0000). This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 1 OVF 0 1 Description [Clearing condition] [Setting condition] When the FRC value has become H'FFFF H'0000 (Initial value) When 0 is written into the OVF after reading the OVF under the setting of OVF = 1 Rev.3.00 Jan. 10, 2007 page 365 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 0Counter Clearing (CCLRA): This bit works to select if or not to clear the FRC by occurrence of comparing match A (matching signal of the FRC and OCRA). Bit 0 CCLRA 0 1 Description Prohibits clearing of the FRC by occurrence of comparing match A Permits clearing of the FRC by occurrence of comparing match A (Initial value) 17.2.6 Timer Control Register X (TCRX) Bit : 7 IEDGA 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : 0 R/W The TCRX is an 8-bit read/write register which works to select the input capture signal edge, to designate the buffer operation and to select the inputting clock for the FRC. The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Bit 7Input Capture Signal Edge Selection A (IEDGA): This bit works to select the rising edge or falling edge of the input capture signal A (FTIA). Bit 7 IEDGA 0 1 Description Captures the falling edge of the input capture signal A Captures the rising edge of the input capture signal A (Initial value) Bit 6Input Capture Signal Edge Selection B (IEDGB): This bit works to select the rising edge or falling edge of the input capture signal B (FTIB). Bit 6 IEDGB 0 1 Description Captures the falling edge of the input capture signal B Captures the rising edge of the input capture signal B (Initial value) Rev.3.00 Jan. 10, 2007 page 366 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 5Input Capture Signal Edge Selection C (IEDGC): This bit works to select the rising edge or falling edge of the input capture signal C (FTIC). However, when the DVCTL has been selected as the signal for the input capture signal edge selection C, this bit will not influence the operation. Bit 5 IEDGC 0 1 Description Captures the falling edge of the input capture signal C Captures the rising edge of the input capture signal C (Initial value) Bit 4Input Capture Signal Edge Selection D (IEDGD): This bit works to select the rising edge or falling edge of the input capture signal D (FTID). Bit 4 IEDGD 0 1 Description Captures the falling edge of the input capture signal D Captures the rising edge of the input capture signal D (Initial value) Bit 3Buffer Enabling A (BUFEA): This bit works to select if or not to use the ICRC as the buffer register for the ICRA. Bit 3 BUFEA 0 1 Description Using the ICRC as the buffer register for the ICRA Not using the ICRC as the buffer register for the ICRA (Initial value) Bit 2Buffer Enabling B (BUFEB): This bit works to select if or not to use the ICRD as the buffer register for the ICRB. Bit 2 BUFEB 0 1 Description Using the ICRD as the buffer register for the ICRB Not using the ICRD as the buffer register for the ICRB (Initial value) Rev.3.00 Jan. 10, 2007 page 367 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bits 1 and 0Clock Select (CKS1, 0): These bits work to select the inputting clock to the FRC from among three types of internal clocks and the DVCFG. The DVCFG is the edge detecting pulse selected by the CFG dividing timer. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description Internal clock: Counts at /4 Internal clock: Counts at /16 Internal clock: Counts at /64 DVCFG: The edge detecting pulse selected by the CFG dividing timer (Initial value) 17.2.7 Timer Output Comparing Control Register (TOCR) Bit : 7 ICSB 6 ICSC 0 R/W 5 ICSD 0 R/W 4 OSRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W Initial value : R/W : 0 R/W The TOCR is an 8-bit read/write register which works to select input capture signals and output comparing output level, to permit output comparing outputs and to control switching over of the access of the OCRA and OCRB. See the section 17.2.4, Timer Interrupt Enabling Register (TIER) regarding the input capture inputs A. The TOCR is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Bit 7Selecting the Input Capture B Signals (ICSB): This bit works to select the input capture B signals. Bit 7 ICSB 0 1 Description Selects the FTIB pin for inputting of the input capture B signals Selects the VD as the input capture B signals (Initial value) Rev.3.00 Jan. 10, 2007 page 368 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 6Selecting the Input Capture C Signals (ICSC): This bit works to select the input capture C signals. The DVCTL is the edge detecting pulse selected by the CTL dividing timer. Bit 6 ICSC 0 1 Description Selects the FTIC pin for inputting of the input capture C signals Selects the DVCTL as the input capture C signals (Initial value) Bit 5Selecting the Input Capture D Signals (ICSD): This bit works to select the input capture D signals. Bit 5 ICSD 0 1 Description Selects the FTID pin for inputting of the input capture D signals Selects the NHSW as the input capture D signals (Initial value) Bit 4Selecting the Output Comparing Register (OCRS): The addresses of the OCRA and OCRB are the same. The OCRS works to control which register to choose when reading/writing this address. The choice will not influence the operation of the OCRA and OCRB. Bit 4 OCRS 0 1 Description Selects the OCRA register Selects the OCRB register (Initial value) Bit 3Enabling the Output A (OEA): This bit works to control the output comparing A signals. Bit 3 OEA 0 1 Description Prohibits the output comparing A signal outputs Permits the output comparing A signal outputs (Initial value) Rev.3.00 Jan. 10, 2007 page 369 of 1038 REJ09B0328-0300 Section 17 Timer X1 Bit 2Enabling the Output B (OEB): This bit works to control the output comparing B signals. Bit 2 OEB 0 1 Description Prohibits the output comparing B signal outputs Permits the output comparing B signal outputs (Initial value) Bit 1Output Level A (OLVLA): This bit works to select the output level to output through the FTOA pin by use of the comparing match A (matching signal between the FRC and OCRA). Bit 1 OLVLA 0 1 Description Low level High level (Initial value) Bit 0Output Level B (OLVLB): This bit works to select the output level to output through the FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB). Bit 0 OLVLB 0 1 Description Low level High level (Initial value) Rev.3.00 Jan. 10, 2007 page 370 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.2.8 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 0 6 0 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR consists of twin 8-bit read/write registers and it works to control the module stop mode. When the MSTP10 bit is set to 1, the Timer X1 stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 2Module Stop (MSTP10): This bit works to designate the module stop mode for the Timer X1. MSTPCRH Bit 2 MSTP10 0 1 Description Cancels the module stop mode of the Timer X1 Sets the module stop mode of the Timer X1 (Initial value) Rev.3.00 Jan. 10, 2007 page 371 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.3 17.3.1 Operation Operation of the Timer X1 (1) Output Comparing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX. The contents of the FRC are always being compared with the OCRA and OCRB and, when the value of these two match, the level set by the the OLVLA and OLVLB of the TOCR is output through the FTOA pin and FTOB pin. After resetting, 0 will be output through the FTOA and FTOB pins until the first compare matching occurs. Also, when the CCLRA of the TCSRX is being set to 1, the FRC will be cleared to H'0000 when the comparing match A occurs. (2) Input Capturing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX. The inputs are transferred to the IEDGA through IEDGD of the TCRX through the FTIA through FTID pins and, at the same time, the ICFA through ICFD of the TCSRX are set to 1. At this time, if the ICIAE through ICIED of the TIER are being set to 1, due interrupt request will be issued to the CPU. When the BUFEA and BUFEB of the TCRX are set to 1, the ICRC and ICRD work as the buffer register, respectively, of the ICRA and ICRB. When the edge selected by setting the IEDGA through IEDGD of the TCRX is input through the FTIA and FTIB pins, the value at the time of the FRC is transferred to the ICRA and ICRB and, at the same time, the values of the ICRA and ICRB before updating are transferred to the ICRC and ICRD. At this time, when the ICFA and ICFB are being set to 1 and if the ICIAE and ICIBE of the TIER are being set to 1, due interrupt request will be issued to the CPU. Rev.3.00 Jan. 10, 2007 page 372 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.3.2 Counting Timing of the FRC The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the inputting clock can be selected from among three different types of clocks (/4, /16, and /64) and the DVCFG. (1) In Case of Internal Clock Operation By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (/4, /16, and /64), generated by dividing the system clock () can be selected. Figure 17.3 shows the timing chart at this time. Internal clock FRC input clock N-1 FRC N N+1 Figure 17.3 Count Timing in Case of Internal Clock Operation (2) In Case of DVCFG Clock Operation By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected. The DVCFG clock makes counting by use of the edge detecting pulse being selected by the CFG dividing timer. Figure 17.4 shows the timing chart at this time. CFG DVCFG FRC input clock FRC N N+1 Figure 17.4 Count Timing in Case of CFG Clock Operation Rev.3.00 Jan. 10, 2007 page 373 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.3.3 Output Comparing Signal Outputting Timing When a comparing match occurs, the output level having been set by the OLVL of the TOCR is output through the output comparing signal outputting pins (FTOA and FTOB). Figure 17.5 shows the timing chart in case of the output comparing signal outputting A. FRC N N+1 N N+ 1 OCRA N N Comparing match signal Clearing* OLVLA FTOA Output comparing signal outputting A pin Note: * Execution of the command is to be designated by the software. Figure 17.5 Output Comparing Signal Outputting A Timing 17.3.4 FRC Clearing Timing The FRC can be cleared when the comparing match A occurs. Figure 17.6 shows the timing chart when doing so. Comparing match A signal FRC N H'0000 Figure 17.6 FRC Clearing Timing by Occurrence of the Comparing Match A Rev.3.00 Jan. 10, 2007 page 374 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.3.5 Input Capture Signal Inputting Timing (1) Input Capture Signal Inputting Timing As for the input capture signal inputting, rising or falling edge is selected by settings of the IEDGA through IEDGD bits of the TCRX. Figure 17.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD = 1). Input capture signal inputting pin Input capture signal Figure 17.7 Input Capture Signal Inputting Timing (Under Normal State) (2) Input Capture Signal Inputting Timing when Making Buffer Operation Buffer operation can be made using the ICRA or ICRD as the buffer of the ICRA or ICRB. Figure 17.8 shows the input capture signal inputting timing chart in case both of the rising and falling edges are designated (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1), using the ICRC as the buffer register for the ICRA (BUFEA = 1). FTIA Input capture signal FRC n n+1 N ICRA M n n N ICRC m M M n Figure 17.8 Input Capture Signal Inputting Timing Chart under the Buffer Mode (Under Normal State) Rev.3.00 Jan. 10, 2007 page 375 of 1038 REJ09B0328-0300 Section 17 Timer X1 Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up corresponding to the designated edge change of respective input capture signals. For example, when using the ICRC as the buffer register for the ICRA, when an edge change having been designated by the IEDGC bit is detected with the input capture signals C and if the ICIEC bit is duly set, an interrupt request will be issued. However, in this case, the FRC value will not be transferred to the ICRC. 17.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing The input capture signal works to set the ICFA through ICFD to "1" and, simultaneously, the FRC value is transferred to the corresponding ICRA through ICRD. Figure 17.9 shows the timing chart for the above. Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 17.9 ICFA through ICFD Setting Up Timing Rev.3.00 Jan. 10, 2007 page 376 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing The OCFA and OCFB are being set to 1 by the comparing match signal being output when the values of the OCRA, OCRB, and FRC match. The comparing match signal is generated at the last state of the value match (the timing of the FRC's updating the matching count reading). After the values of the OCRA, OCRB, and FRC match, up until the count up clock signal is generated, the comparing match signal will not be issued. Figure 17.10 shows the OCFA and OCFB setting timing chart. FRC N N+1 OCRA, OCRB N Comparing match signal OCFA, OCFB Figure 17.10 OCF Setting Up Timing 17.3.8 Overflow Flag (CVF) Setting Up Timing The OVF is set to when the FRC overflows (H'FFFF H'0000). Figure 17.11 shows the timing chart for this case. FRC H'FFFF H'0000 Overflowing signal OVF Figure 17.11 OVF Setting Up Timing Rev.3.00 Jan. 10, 2007 page 377 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.4 Operation Mode of the Timer X1 Table 17.4 indicated below shows the operation mode of the Timer X1. Table 17.4 Operation Mode of the Timer X1 Operation mode FRC OCRA, OCRB ICRA to ICRD TIER TCRX TOCR TCSRX Reset Reset Reset Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Functions Functions Functions Sleep Functions Functions Functions Functions Functions Functions Functions Watch Subactive Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Standby Reset Reset Reset Reset Reset Reset Reset Subsleep Reset Reset Reset Reset Reset Reset Reset Module stop Reset Reset Reset Reset Reset Reset Reset 17.5 Interrupt Causes Total seven interrupt causes exist with the Timer X1, namely, ICIA through ICID, OCIA, OCIB, and FOVI. Table 17.5 given below lists the contents of respective interrupt causes. Respective interrupt requests can be permitted or prohibited by setting of respective interrupt enabling bits of the TIER. Also, independent vector addresses are being allocated to respective interrupt causes. Table 17.5 Interrupt Causes of the Timer X1 Abbreviations of the Interrupt Causes ICIA ICIB ICIC ICID OCIA OCIB FOVI Priority Degree Interrupt request by the ICFA Interrupt request by the ICFB Interrupt request by the ICFC Interrupt request by the ICFD Interrupt request by the OCFA Interrupt request by the OCFB Interrupt request by the OVF Low Contents High Rev.3.00 Jan. 10, 2007 page 378 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.6 Exemplary Uses of the Timer X1 Figure 17.12 indicated below shows an example of outputting at optional phase difference of the pulses of the 50% duty. For this setting, follow the procedures listed below. (1) Set the CCLRA bit of the TCSRX to "1". (2) Each time a comparing match occurs, the OLVLA bit and the OLVLB bit are reversed by use of the software. H'FFFF OCRA OCRB H'0000 FRC Clearing the counter FTOA FTOB Figure 17.12 An Exemplary Pulse Outputting Rev.3.00 Jan. 10, 2007 page 379 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.7 Precautions when Using the Timer X1 Pay great attention to the fact that the following competitions and operations occur during operation of the Timer X1. 17.7.1 Competition between Writing and Clearing with the FRC When a counter clearing signal is issued under the T2 state where the FRC is under the writing cycle, writing into the FRC will not be effected and the priority will be given to clearing of the FRC. Figure 17.13 shows the timing chart in this case. Writing cycle with the FRC T1 T2 Address FRC address Internal writing signal Counter clearing signal FRC N H'0000 Figure 17.13 Competition between Writing and Clearing with the FRC Rev.3.00 Jan. 10, 2007 page 380 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.7.2 Competition between Writing and Counting Up with the FRC When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the counting up will not be effected and the priority will be given to count writing. Figure 17.14 shows the timing chart in this case. Writing cycle with the FRC T1 T2 Address FRC address Internal writing signal Inputting clock to the FRC FRC N M Writing data Figure 17.14 Competition between Writing and Counting Up with the FRC Rev.3.00 Jan. 10, 2007 page 381 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.7.3 Competition between Writing and Comparing Match with the OCR When a comparing match occurs under the T2 state where the OCRA and OCRB are under the writing cycle, the priority will be given to writing of the OCR and the comparing match signal will be prohibited. Figure 17.15 shows the timing chart in this case. Writing cycle with the OCR T1 T2 Address OCR address Internal writing signal FRC N N+1 OCR N M Writing data Comparing match signal Prohibited Figure 17.15 Competition between Writing and Comparing Match with the OCR Rev.3.00 Jan. 10, 2007 page 382 of 1038 REJ09B0328-0300 Section 17 Timer X1 17.7.4 Changing over the Internal Clocks and Counter Operations Depending on the timing of changing over the internal clocks, the FRC may count up. Table 17.6 indicated below shows the relations between the timing of changing over the internal clocks (Rewriting of the CKS1 and CKS0) and the FRC operations. When using an internal clock, the counting clock is being generated detecting the falling edge of the internal clock dividing the system clock (). For this reason, like Item No. 3 of table 17.6, count clock signals are issued deeming the timing before the changeover as the falling edge to have the FRC to count up. Also, when changing over between an internal clock and the external clock, the FRC may count up. Table 17.6 Changing over the Internal Clocks and the FRC Operation No. 1 Re-writing Timing for the CKS1 and CKS0 FRC Operation Low Low level changeover Clock before the changeover Clock after the changeover Count clock FRC N N +1 Re-writing of the CKS1 and CKS0 2 Low High level changeover Clock before the changeover Clock after the changeover Count clock FRC N N +1 N +2 Re-writing of the CKS1 and CKS0 Rev.3.00 Jan. 10, 2007 page 383 of 1038 REJ09B0328-0300 Section 17 Timer X1 Re-writing timing for the CKS1 and CKS0 High Low level changeover No. 3 FRC operation Clock before the changeover Clock after the changeover Count clock * FRC N N +1 N +2 Re-writing of the CKS1 and CKS0 4 High High level changeover Clock before the changeover Clock after the changeover Count clock FRC N N +1 N +2 Re-writing of the CKS1 and CKS0 Note: * The count clock signals are issued deeming the changeover timing as the falling edge to have the FRC to count up. Rev.3.00 Jan. 10, 2007 page 384 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) Section 18 Watchdog Timer (WDT) 18.1 Overview This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer mode, an interval timer interrupt is generated each time the counter overflows. 18.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode WOVI interrupt generation in interval timer mode * Internal reset or internal interrupt generated when the timer counter overflows Choice of internal reset or NMI interrupt generation in watchdog timer mode * Choice of 8 counter input clocks Maximum WDT interval: system clock period x 131072 x 256 Rev.3.00 Jan. 10, 2007 page 385 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.1.2 Block Diagram Figure 18.1 shows block diagram of WDT. WOVI (Interrupt request signal) Internal NMI interrupt request signal Internal reset signal* Interrupt control * Reset control Overflow Clock Clock select /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock source WTCNT WTCSR Module bus WDT Legend: WTCSR WTCNT : Timer control/status register : Timer counter Bus interface Note: * The internal reset signal can be generated by means of a register setting. Figure 18.1 Block Diagram of WDT Rev.3.00 Jan. 10, 2007 page 386 of 1038 REJ09B0328-0300 Internal bus Section 18 Watchdog Timer (WDT) 18.1.3 Register Configuration The WDT has two registers, as summarized in table 18.1. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 18.1 WDT Registers Address* Name Watchdog timer control/status register Watchdog timer counter System control register Abbrev. WTCSR WTCNT SYSCR R/W 3 R/(W)* 1 Initial Value H'00 H'00 H'09 2 Write* Read H'FFBC H'FFBD H'FFE8 H'FFBC H'FFBC H'FFE8 R/W R/W Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 18.2.4, Notes on Register Access. 3. Only 0 can be written in bit 7, to clear the flag. Rev.3.00 Jan. 10, 2007 page 387 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.2 18.2.1 Register Descriptions Watchdog Timer Counter (WTCNT) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in WTCSR is set to 1. WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0. Note: * WTCNT is write-protected by a password to prevent accidental overwriting. For details see section 18.2.4, Notes on Register Access. 18.2.2 Watchdog Timer Control/Status Register (WTCSR) Bit : Initial value : 7 OVF 0 6 WT/IT 5 TME 4 RSTS 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W 0 0 0 * R/W : R/(W) R/W R/W R/W Note: * Only 0 can be written to clear the flag. WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to WTCNT, and the timer mode. WTCSR is initialized to H'00 by a reset. Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For details see section 18.2.4, Notes on Register Access. Rev.3.00 Jan. 10, 2007 page 388 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) Bit 7Overflow Flag (OVF): A status flag that indicates that WTCNT has overflowed from H'FF to H'00. Bit 7 OVF 0 Description [Clearing conditions] (1) Write 0 in the TME bit (2) Read WTCSR when OVF = 1, then write 0 in OVF 1 [Setting condition] When WTCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset (Initial value) Bit 6Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI interrupt when TCNT overflows. Bit 6 WT/IT 0 1 Description Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when WTCNT overflows (Initial value) Watchdog timer mode: Sends the CPU a reset or NMI interrupt request when WTCNT overflows Bit 5Timer Enable (TME): Selects whether WTCNT runs or is halted. Bit 5 TME 0 1 Description WTCNT is initialized to H'00 and halted WTCNT counts (Initial value) Bit 4Reset Select (RSTS): Reserved. This bit should not be set to 1. Rev.3.00 Jan. 10, 2007 page 389 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) Bit 3Reset or NMI (RST/NMI): Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in watchdog timer mode. Bit 3 RST/NIMI 0 1 Description An NMI interrupt request is generated An internal reset request is generated (Initial value) Bits 2 to 0Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source, obtained by dividing the system clock () for input to WTCNT. WDT Input Clock Selection Bit 2 CSK2 0 Bit 1 CSK1 0 Bit 0 CSK0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Clock /2 (Initial value) /64 /128 /512 /2048 /8192 /32768 /131072 Overflow Period* (when = 10 MHz) 51.2 s 1.6 ms 3.3 ms 13.1 ms 52.4 ms 209.7 ms 838.9 ms 3.36 s The overflow period is the time from when WTCNT starts counting up from H'00 until overflow occurs. Rev.3.00 Jan. 10, 2007 page 390 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.2.3 System Control Register (SYSCR) Bit : 7 -- 0 -- 6 -- 0 -- 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 0 R/W 1 0 R/W 0 -- 1 -- NMIEG1 NMIEG0 Initial value : R/W : Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules. Bit 3External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. Bit 3 XRST 0 1 Description Reset is generated by watchdog timer overflow Reset is generated by external reset input (Initial value) 18.2.4 Notes on Register Access The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written to by a word transfer instruction. They cannot be written to with byte transfer instructions. Figure 18.2 shows the format of data written to WTCNT and WTCSR. WTCNT and WTCSR both have the same write address. For a write to WTCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to WTCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to WTCNT or WTCSR. Rev.3.00 Jan. 10, 2007 page 391 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) Figure 18.2 Format of Data Written to WTCNT and WTCSR (2) Reading WTCNT and WTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for WTCSR, and H'FFBD for WTCNT. Rev.3.00 Jan. 10, 2007 page 392 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.3 18.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits in WTCSR to 1. Software must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. This ensures that WTCNT does not overflow while the system is operating normally. If WTCNT overflows without being rewritten because of a system crash or other error, the chip is reset, or an NMI interrupt is generated, for 518 system clock periods (518 ). This is illustrated in figure 18.3. An internal reset request from the watchdog timer and reset input from the RES pin are handled via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR. If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request and an NMI pin interrupt request must therefore be avoided. WTCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written to WTCNT WOVF = 1* Internal reset generated Time WT/IT = 1 H'00 written TME = 1 to WTCNT Internal reset signal 518 system clock period Legend: WT/IT : Timer mode select bit TME : Timer enable bit Note: * Cleared to 0 by an internal reset when WOVF is set to 1. XRST is cleared to 0. Figure 18.3 Operation in Watchdog Timer Mode Rev.3.00 Jan. 10, 2007 page 393 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in WTCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 18.4. This function can be used to generate interrupt requests at regular intervals. WTCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI : Interval timer interrupt request generation Figure 18.4 Operation in Interval Timer Mode Rev.3.00 Jan. 10, 2007 page 394 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.3.3 Timing of Setting of Overflow Flag (OVF) The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 18.5. If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF bit in WTCSR is set to 1 and at the same time an NMI interrupt is requested. CK WTCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 18.5 Timing of OVF Setting Rev.3.00 Jan. 10, 2007 page 395 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in WTCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request. 18.5 18.5.1 Usage Notes Contention between Watchdog Timer Counter (WTCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a WTCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 18.6 shows this operation. WTCNT write cycle T1 T2 Internal Internal address Internal write signal WTCNT input clock WTCNT N M Counter write data Figure 18.6 Contention between WTCNT Write and Increment Rev.3.00 Jan. 10, 2007 page 396 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) 18.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 18.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev.3.00 Jan. 10, 2007 page 397 of 1038 REJ09B0328-0300 Section 18 Watchdog Timer (WDT) Rev.3.00 Jan. 10, 2007 page 398 of 1038 REJ09B0328-0300 Section 19 8-Bit PWM Section 19 8-Bit PWM 19.1 Overview The 8-bit PWM incorporates 4 channels of the duty control method. Its outputs can be used to control a reel motor or loading motor. 19.1.1 Features * Conversion period: 256-state * Duty control method 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the 8-bit PWM (1 channel). Internal data bus PW8CR PWRn PWMn Polarity specification R Q S Match signal Comparator OVF 27 20 (n = 3 to 0) Free-running counter (FRC) Legend: PWRn PW8CR PWMn OVF : 8-bit PWM data register n : 8-bit PWM control register : 8-bit PWM square-wave output pin n : Overflow signal from FRC lower 8-bit Figure 19.1 Block Diagram of 8-Bit PWM Rev.3.00 Jan. 10, 2007 page 399 of 1038 REJ09B0328-0300 Section 19 8-Bit PWM 19.1.3 Pin Configuration Table 19.1 shows the 8-bit PWM pin configuration. Table 19.1 Pin Configuration Name 8-bit PWM square-wave output pin 0 8-bit PWM square-wave output pin 1 8-bit PWM square-wave output pin 2 8-bit PWM square-wave output pin 3 Abbrev. PWM0 PWM1 PWM2 PWM3 I/O Output Output Output Output Function 8-bit PWM square-wave output 0 8-bit PWM square-wave output 1 8-bit PWM square-wave output 2 8-bit PWM square-wave output 3 19.1.4 Register Configuration Table 19.2 shows the 8-bit PWM register configuration. Table 19.2 8-Bit PWM Registers Name 8-bit PWM data register 0 8-bit PWM data register 1 8-bit PWM data register 2 8-bit PWM data register 3 8-bit PWM control register Port mode register 3 Note: * Abbrev. PWR0 PWR1 PWR2 PWR3 PW8CR PMR3 R/W W W W W R/W R/W Size Byte Byte Byte Byte Byte Byte Initial Value Address* H'00 H'00 H'00 H'00 H'F0 H'00 H'D126 H'D127 H'D128 H'D129 H'D12A H'FFD0 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 400 of 1038 REJ09B0328-0300 Section 19 8-Bit PWM 19.2 19.2.1 PWR0 Register Descriptions Bit PWM Data Registers 0, 1, 2, and 3 (PWR0, PWR1, PWR2, PWR3) Bit : Initial value : R/W : 7 PW07 0 W 6 PW06 0 W 5 PW05 0 W 4 PW04 0 W 3 PW03 0 W 2 PW02 0 W 1 PW01 0 W 0 PW00 0 W PWR1 Bit : Initial value : R/W : 7 PW17 0 W 6 PW16 0 W 5 PW15 0 W 4 PW14 0 W 3 PW13 0 W 2 PW12 0 W 1 PW11 0 W 0 PW10 0 W PWR2 Bit : Initial value : R/W : 7 PW27 0 W 6 PW26 0 W 5 PW25 0 W 4 PW24 0 W 3 PW23 0 W 2 PW22 0 W 1 PW21 0 W 0 PW20 0 W PWR3 Bit : Initial value : R/W : 7 PW37 0 W 6 PW36 0 W 5 PW35 0 W 4 PW34 0 W 3 PW33 0 W 2 PW32 0 W 1 PW31 0 W 0 PW30 0 W 8-bit PWM data registers 0, 1, 2, and 3 (PWR0, PWR1, PWR2, PWR3) control the duty cycle at 8-bit PWM pins. The data written in PWR0, PWR1, PWR2, and PWR3 correspond to the highlevel width of one PWM output waveform cycle (256 states). When data is set in PWR0, PWR1, PWR2, and PWR3, the contents of the data are latched in the PWM waveform generators, updating the PWM waveform generation data. PWR0, PWR1, PWR2, and PWR3 are write-only registers. When read, all bits are always read as 1. PWR0, PWR1, PWR2, and PWR3 are initialized to H'00 by a reset. Rev.3.00 Jan. 10, 2007 page 401 of 1038 REJ09B0328-0300 Section 19 8-Bit PWM 19.2.2 8-Bit PWM Control Register (PW8CR) Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PWC3 0 R/W 2 PWC2 0 R/W 1 PWC1 0 R/W 0 PWC0 0 R/W Initial value : R/W : The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls PWM functions. PW8CR is initialized to H'00 by a reset. Bits 7 to 4Reserved: They are always read as 1. Writes are disabled. Bits 3 to 0Output Polarity Select (PWC3 to PWC0): These bits select the output polarity of PWMn pin between positive or negative (reverse). Bit n PWCn 0 1 Description PWMn pin output has positive polarity PWMn pin output has negative polarity (Initial value) Note: n = 3 to 0 19.2.3 Port Mode Register 3 (PMR3) Bit : 7 PMR37 0 R/W 6 PMR36 0 R/W 5 PMR35 0 R/W 4 PMR34 0 R/W 3 PMR33 0 R/W 2 PMR32 0 R/W 1 PMR31 0 R/W 0 PMR30 0 R/W Initial value : R/W : The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching is specified for each bit. The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset. For bits other than 5 to 2, see section 11.5, Port 3. Rev.3.00 Jan. 10, 2007 page 402 of 1038 REJ09B0328-0300 Section 19 8-Bit PWM Bits 5 to 2P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): These bits set whether the P3n/PWMn pin is used as I/O pin or it is used as 8-bit PWM output PWMm pin. Bit n PMR3n 0 1 Description P3n/PMWm pin functions as P3n I/O pin P3n/PMWm pin functions as PWMm output pin (Initial value) Note: n = 5 to 2, m = 3 to 0 19.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle and transits to the module stop mode. For details, see section 4.5, Module Stop Mode. The MSTPCR is initialized to H'FFFF by a reset. Bit 4: Module Stop (MSTP4): This bit sets the module stop mode of the 8-bit PWM. MSTPCRL Bit 4 MSTP4 0 1 Description 8-bit PWM module stop mode is released 8-bit PWM module stop mode is set (Initial value) Rev.3.00 Jan. 10, 2007 page 403 of 1038 REJ09B0328-0300 Section 19 8-Bit PWM 19.3 8-Bit PWM Operation The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width determined by the data registers (PWR). The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter. Figure 19.2 shows the output waveform example of 8-bit PWM. The pulse width (Twidth) can be obtained by the following expression: Twidth = (1/) x (PWR setting value) FRC lower 8-bit value H'FF PWRn setting value H'00 PWRn pin output (n = 3 to 0) (Positive polarity) Pulse width T width Pulse width T width (Negative polarity) T width Pulse cycle (256 states) T width Pulse cycle (256 states) Figure 19.2 8-Bit PWM Output Waveform (Example) Rev.3.00 Jan. 10, 2007 page 404 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM Section 20 12-Bit PWM 20.1 Overview The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the drum and capstan motor controller. 20.1.1 Features Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the pulse-pitch control method (periodically overriding part of the output). This reduces lowfrequency components in the pulse output, enabling a quick response without increasing the clock frequency. The pitch of the PWM signal is modified in response to error data (representing lead or lag in relation to a preset speed and phase). Rev.3.00 Jan. 10, 2007 page 405 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from the contents of a data register. Low-frequency components are reduced because the two quantizing pulses have different frequencies. The error data is represented by an unsigned 12-bit binary number. /2 /4 /8 /16 /32 /64 /128 CAPPWM or DRMPWM Counter Pulse generator Output control circuit PWM data register PWM control register Error data * DFUCR Internal data bus Legend: CAPPWM : Capstan mix pin DRMPWM : Drum mix pin Digital filter circuit PTON CP/DP Figure 20.1 Block Diagram of 12-Bit PWM (1 channel) Rev.3.00 Jan. 10, 2007 page 406 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM 20.1.3 Pin Configuration Table 20.1 shows the 12-bit PWM pin configuration. Table 20.1 Pin Configuration Name Capstan mix Drum mix Abbrev. CAPPWM DRMPWM I/O Output Function 12-bit PWM square-wave output 20.1.4 Register Configuration Table 20.2 shows the 12-bit PWM register configuration. Table 20.2 12-Bit PWM Registers Name 12-bit PWM control register Abbrev. CPWCR DPWCR 12-bit PWM data register Note: * CPWDR DPWDR Lower 16 bits of the address. R/W W W R/W R/W Size Byte Byte Word Word Initial Value Address* H'42 H'42 H'F000 H'F000 H'D07B H'D07A H'D07C H'D078 Rev.3.00 Jan. 10, 2007 page 407 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM 20.2 20.2.1 CPWCR Register Descriptions 12-Bit PWM Control Registers (CPWCR, DPWCR) Bit : Initial value : R/W : 7 CPOL 0 W 6 CDC 1 W 5 CHiZ 0 W 4 CH/L 0 W 3 CSF/DF 0 W 2 CCK2 0 W 1 CCK1 1 W 0 CCK0 0 W DPWCR Bit : Initial value : R/W : 7 DPOL 0 W 6 DDC 1 W 5 DHiZ 0 W 4 DH/L 0 W 3 DSF/DF 0 W 2 DCK2 0 W 1 DCK1 1 W 0 DCK0 0 W CPWCR is the PWM output control register for the capstan motor. DPWCR is the PWM output control register for the drum motor. Both are 8-bit writable registers. CPWCR and DPWCR are initialized to H'42 by a reset, or in sleep mode, standby mode, watch mode, subactive mode, subsleep mode, or module stop mode of the servo circuit. Bit 7Polarity Invert (POL): This bit can invert the polarity of the modulated PWM signal for noise suppression and other purposes. This bit is invalid when fixed output is selected (when bit DC is set to 1). Bit 7 POL 0 1 Description Output with positive polarity Output with inverted polarity (Initial value) Bit 6Output Select (DC): Selects either PWM modulated output, or fixed output controlled by the pin output bits (Bits 5 and 4). Rev.3.00 Jan. 10, 2007 page 408 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM Bits 5 and 4PWM Pin Output (Hi-Z, H/L): When bit DC is set to 1, the 12-bit PWM output pins (CAPPWM, DRMPWM) output a value determined by the Hi-Z and H/L bits. The output is not affected by bit POL. In power-down modes, the 12-bit PWM circuit and pin statuses are retained. Before making a transition to a power-down mode, first set bits 6 (DC), 5 (Hi-Z), and 4 (H/L) of the 12-bit PWM control registers (CPWCR and DPWCR) to select a fixed output level. Choose one of the following settings: Bit 6 DC 1 Bit 5 Hi-Z 0 Bit 4 H/L 0 1 1 0 * Legend: * Don't care * * Output state Low output High output High-impedance Modulation signal output (Initial value) Bit 3Output Data Select (SF/DF): Selects whether the data to be converted to PWM output is taken from the data register or from the digital filter circuit. Bit SF/DF 0 1 Description Modulation by error data from the digital filter circuit Modulation by error data written in the data register (Initial value) Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by PWMs and output from the CAPPWM and DRMPWM pins. However, it is possible to output only drum phase filter results from CAPPWM pin and only capstan phase filter result from DRMPWM pin, by DFUCR settings of the digital filter circuit. See the section 28.11 Digital Filters. Rev.3.00 Jan. 10, 2007 page 409 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM Bits 2 to 0Carrier Frequency Select (CK2 to CK0): Selects the carrier frequency of the PWM modulated signal. Do not set them to 111. Bit 2 CK2 0 Bit 1 CK1 0 Bit 0 CK0 0 1 1 0 1 1 0 0 1 1 0 1 Description 2 4 8 16 32 64 128 (Do not set) (Initial value) 20.2.2 CPWDR 12-Bit PWM Data Registers (CPWDR, DPWDR) Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DPWDR Bit : 15 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 DPWDR11 DPWDR10 DPWDR9 DPWDR8 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0 Initial value : 1 R/W : -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The 12-bit PWM data registers (CPWDR and DPWDR) are 12-bit readable/writable registers in which the data to be converted to PWM output is written. The data in these registers is converted to PWM output only when bit SF/DF of the corresponding control register is set to 1. The error data from the digital filter circuit is written in the data register, and then modulated by PWM. At this time, the error data from the digital filter circuit can be monitored by reading the data register. These registers can be accessed by word only, and cannot be accessed by byte. Byte access gives unassured results. Rev.3.00 Jan. 10, 2007 page 410 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM CPWDR and DPWDR are initialized to H'F000 by a reset, or in sleep mode, standby mode, watch mode, subactive mode, subsleep mode, or module stop mode of the servo circuit. 20.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit : Initial value : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When the MSTP1 bit is set to 1, the 12-bit PWM and Servo circuit, stops their operation upon completion of the bus cycle and transits to the module stop mode. For details, see section 4.5, Module Stop Mode. The MSTPCR is initialized to H'FFFF by a reset. Bit 1Module Stop (MSTP1): This bit sets the module stop mode of the 12-bit PWM. This bit also controls the module stop mode of the servo circuit. MSTPCRL Bit 1 MSTP1 0 1 Description Module stop mode of the 12-bit PWM and servo circuit is released Module stop mode of the 12-bit PWM and servo circuit is set (Initial value) Rev.3.00 Jan. 10, 2007 page 411 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM 20.3 20.3.1 Operation Output Waveform The PWM signal generator combines the error data with the output from an internal pulse generator to produce a pulse-width modulated signal. When Vcc/2 is set as the reference value, the following conditions apply: * When the motor is running at the correct sped and phase, the PWM signal is output with a 50% duty cycle. * When the motor is running behind the correct speed or phase, it is corrected by periodically holding part of the PWM signal low. The part held low depends on the size of the error. * When the motor is running ahead of the correct speed or phase, it is corrected by periodically holding part of the PWM signal high. The part held high depends on the size of the error. When the motor is running at the correct speed and phase, the error data is a 12-bit value representing 1/2 (1000 0000 0000), and the PWM output has the same frequency as the selected division clock. After the error data has been converted into a PWM signal, the PWM signal can be smoothed into a DC voltage by an external low-pass filter (LPF). The smoothes error data can be used to control the motor. Figure 20.2 shows sample waveform outputs. The 12-bit PWM pin outputs a low-level signal upon reset, in power-down mode or at modulestop. Rev.3.00 Jan. 10, 2007 page 412 of 1038 REJ09B0328-0300 Counter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 C10 C11 C12 C13 Pulse Generator Corresponds to Pwr3=1 Corresponds to Pwr2=1 Corresponds to Pwr1=1 Corresponds to Pwr0=1 Figure 20.2 Sample Waveform Output by 12-Bit PWM (4 Bits) PWM data register Pwr3 2 1 0 "L" 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Rev.3.00 Jan. 10, 2007 page 413 of 1038 REJ09B0328-0300 Section 20 12-Bit PWM Section 20 12-Bit PWM Rev.3.00 Jan. 10, 2007 page 414 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM Section 21 14-Bit PWM 21.1 Overview The 14-bit PWM is a pulse division type PWM which can be used for V-synthesizer, etc. 21.1.1 Features Features of the 14-bit PWM are given below: * Choice of two conversion periods A conversion period of 32768/ with a minimum modulation width of 2/, or a conversion period of 16384/ with a minimum modulation width of 1/, can be selected. * Pulse division method for less ripple Rev.3.00 Jan. 10, 2007 page 415 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the 14-bit PWM. PWCR Internal data bus PWDRL PWDRU /4 /2 PWM waveform generator PWM14 Legend: PWCR : PWM control register PWDRL : PWM data register L PWDRU : PWM data register U PWM14 : PWM14 output pin Figure 21.1 Block Diagram of 14-Bit PWM 21.1.3 Pin Configuration Table 21.1 shows the 14-bit PWM pin configuration. Table 21.1 Pin Configuration Name PWM 14-bit square-wave output pin Note: * Abbrev. PWM14* I/O Output Function 14-bit PWM square-wave output This pin also functions as P40 general I/O pin. When using this pin, set the pin function by the port mode register 4 (PMR4). For details, see section 11.6, Port 4. Rev.3.00 Jan. 10, 2007 page 416 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM 21.1.4 Register Configuration Table 21.2 shows the 14-bit PWM register configuration. Table 21.2 14-Bit PWM Registers Name PWM control register PWM data register U PWM data register L Note: * Abbrev. PWCR PWDRU PWDRL R/W R/W W W Size Byte Byte Byte Initial Value Address* H'FE H'00 H'00 H'D122 H'D121 H'D120 Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 417 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM 21.2 21.2.1 Register Descriptions PWM Control Register (PWCR) Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PWCR0 0 R/W Initial value : R/W : The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM functions. PWCR is initialized to H'FE by a reset. Bits 7 to 1Reserved: They are always read as 1. Writes are disabled. Bit 0Clock Select (PWCR0): Selects the clock supplied to the 14-bit PWM. Bit 0 PWCR0 0 1 Description The input clock is /2 (t = 2/) (Initial value) The conversion period is 16384/, with a minimum modulation width of 1/ The input clock is /4 (t = 4/) The conversion period is 32768/, with a minimum modulation width of 2/ Note: t/: Period of PWM clock input Rev.3.00 Jan. 10, 2007 page 418 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM 21.2.2 PWDRU PWM Data Registers U and L (PWDRU, PWDRL) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 0 W 0 W 0 W 0 W 0 W 0 W PWDRL Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN waveform cycle. PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written in PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. Both PWDRU and PWDRL are accessible by byte access only. Word access gives unassured results. When 14-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. When writing the 14-bit data, follow these steps: (1) Write the lower 8 bits to PWDRL. (2) Write the upper 6 bits to PWDRU. Write the data first to PWDRL and then to PWDRU. PWDRU and PWDRL are write-only registers. When read, all bits always read 1. PWDRU and PWDRL are initialized to H'C000 by a reset. Rev.3.00 Jan. 10, 2007 page 419 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM 21.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that control the module stop mode functions. When the MSTP5 bit is set to 1, the 14-bit PWM operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset. Bit 5Module Stop (MSTP5): Specifies the module stop mode of the 14-bit PWM. MSTPCRL Bit 5 MSTP5 0 1 Description 14-bit PWM module stop mode is released 14-bit PWM module stop mode is set (Initial value) Rev.3.00 Jan. 10, 2007 page 420 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM 21.3 14-Bit PWM Operation When using the 14-bit PWM, set the registers in this sequence: (1) Set bit PMR40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for PWM output. (2) Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32768/ (PWCR0 = 1) or 16384/ (PWCR0 = 0). (3) Set the output waveform data in PWM data registers U and L (PWDRU, PWDRL). Be sure to write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these registers are latched in the PWM waveform generator, and the PWM waveform generation data is updated in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 21.2. The total high-level width during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be expressed as follows: TH = (data value in PWDRU and PWDRL + 64) x t/2 where t is the period of PWM clock input: 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1). If the data value in PWDRU and PWDRL is from H'3FC0 to H'3FFF, the PWM output stays high. When the data value is H'0000, TH is calculated as follows: TH = 64 x t/2 = 32 t 1 conversion period t f1 t f2 t f63 t f64 t H1 t H2 t H3 t H63 t H64 T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64 Figure 21.2 Waveform Output by 14-Bit PWM Rev.3.00 Jan. 10, 2007 page 421 of 1038 REJ09B0328-0300 Section 21 14-Bit PWM Rev.3.00 Jan. 10, 2007 page 422 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit Section 22 Prescalar Unit 22.1 Overview The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses as a clock source and a 5-bit counter that uses W as a clock source. 22.1.1 Features * Prescalar S (PSS): Generates frequency division clocks that are input to peripheral functions. * Prescalar W (PSW): When a timer A is used as a clock time base, the PSW frequency-divides subclocks and generates input clocks. * Stable oscillation wait time count: During the return from the low power consumption mode excluding the sleep mode, the FRC counts the stable oscillation wait time. * 8-bit PWM The lower 8 bits of the FRC is used as 8-bit PWM cycle and duty cycle generation counters. (Conversion cycle: 256 states) * 8-bit input capture by IC pins Catches the 8 bits of 2 to 2 of the FRC according to the edge of the IC pin for remote control receiving. 15 8 * Frequency division clock output: Can output the frequency division clock for the system clock or the frequency division clock for the subclock from the frequency division clock output pin (TMOW). Rev.3.00 Jan. 10, 2007 page 423 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit 22.1.2 Block Diagram Figure 22.1 shows a block diagram of the prescalar unit. PWM3 PWM2 PWM1 PWM0 212 27 8 bits 20 LSB 18-bit free running counter (FRC) 215 IC pin Interrupt request ICR1 8 bits 28 /32 /16 /8 /4 Stable oscillation wait time count output Prescalar S /131072 to /2 MSB 217 6 bits w/32 w/16 TMOW pin w/8 Prescalar W w/128 MSB 5-bit counter PCSR LSB w/4 Internal data bus Legend: ICR1 : Input capture register 1 PCSR : Prescalar unit control/status register : Input capture input pin IC TMOW : Frequency division clock output pin Figure 22.1 Block Diagram of Prescalar Unit Rev.3.00 Jan. 10, 2007 page 424 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit 22.1.3 Pin Configuration Table 22.1 shows the pin configuration of the prescalar unit. Table 22.1 Pin Configuration Name Input capture input Frequency division clock output Abbrev. IC TMOW I/O Input Output Function Prescalar unit input capture input pin Prescalar unit frequency division clock output pin 22.1.4 Register Configuration Table 22.2 shows the register configuration of the prescalar unit. Table 22.2 Register Configuration Name Input capture register 1 Abbrev. ICR1 R/W R R/W Size Byte Byte Initial Value H'00 H'08 Address* H'D12C H'D12D Prescalar unit control/status PCSR register Note: * Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 425 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit 22.2 22.2.1 Registers Input Capture Register 1 (ICR1) Bit : 7 ICR17 0 R 6 ICR16 0 R 5 ICR15 0 R 4 ICR14 0 R 3 ICR13 0 R 15 8 2 ICR12 0 R 1 ICR11 0 R 0 ICR10 0 R Initial value : R/W : Input capture register 1 (ICR1) captures 8-bit data of 2 to 2 of the FRC according to the edge of the IC pin. ICR1 is an 8-bit read-only register. The write operation becomes invalid. The ICR1 values are undefined until the first capture is generated after the mode has been set to the standby mode, watch mode, subactive mode, and subsleeve mode. When reset, ICR1 is initialized to H'00. 22.2.2 Prescalar Unit Control/Status Register (PCSR) Bit : Initial value : R/W : 7 ICIF 0 R/(W)* 6 ICIE 0 R/W 5 ICEG 0 R/W 4 NCon/off 0 R/W 3 -- 1 -- 2 DCS2 0 R/W 1 DCS1 0 R/W 0 DCS0 0 R/W Note: * Only 0 can be written to clear the flag. The prescalar unit control/status register (PCSR) controls the input capture function and selects the frequency division clock that is output from the TMOW pin. PCSR is an 8-bit read/write enable register. When reset, PCSR is initialized to H'08. Bit 7Input Capture Interrupt Flag (ICIF): Input capture interrupt request flag. This indicates that the input capture was performed according to the edge of the IC pin. Bit 7 ICIF 0 1 Description [Clear condition] When 0 is written after 1 has been read [Set condition] When the input capture was performed according to the edge of the IC pin (Initial value) Rev.3.00 Jan. 10, 2007 page 426 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit Bit 6Input Capture Interrupt Enable (ICIE): When ICIF was set to 1 by the input capture according to the edge of the IC pin, ICIE enables and disables the generation of an input capture interrupt. Bit 6 ICIE 0 1 Description Disables the generation of an input capture interrupt Enables the generation of an input capture interrupt (Initial value) Bit 5IC Pin Edge Select (ICEG): ICEG selects the input edge sense of the IC pin. Bit 5 ICEG 0 1 Description Detects the falling edge of the IC pin input Detects the rising edge of the IC pin input (Initial value) Bit 4Noise Cancel ON/OFF (NCon/off): NCon/off selects enable/disable of the noise cancel function of the IC pin. For the noise cancel function, see section 22.3, Noise Cancel Circuit. Bit 4 NCon/off 0 1 Description Disables the noise cancel function of the IC pin Enables the noise cancel function of the IC pin (Initial value) Bit 3Reseved: When the bit is read, 1 is always read. The write operation is invalid. Rev.3.00 Jan. 10, 2007 page 427 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit Bits 2 to 0Frequency Division Clock Output Select (DCS2 to DCS0): DCS2 to DCS0 select eight types of frequency division clocks that are output from the TMOW pin. Bit 2 DCS2 0 Bit 1 DCS1 0 Bit 0 DCS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Outputs PSS, /32 Outputs PSS, /16 Outputs PSS, /8 Outputs PSS, /4 Outputs PSW, W/32 Outputs PSW, W/16 Outputs PSW, W/8 Outputs PSW, W/4 (Initial value) 22.2.3 Port Mode Register 1 (PMR1) Bit : 7 PMR17 0 R/W 6 PMR16 0 R/W 5 PMR15 0 R/W 4 PMR14 0 R/W 3 PMR13 0 R/W 2 PMR12 0 R/W 1 PMR11 0 R/W 0 PMR10 0 R/W Initial value : R/W : The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00. Bit 7P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used as a P17 I/O pin or a TMOW pin for division clock output. Bit 7 PMR17 0 1 Description The P17/TMOW pin functions as a P17 I/O pin The P17/TMOW pin functions as a TMOW pin for division clock output (Initial value) Rev.3.00 Jan. 10, 2007 page 428 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit Bit 6P16/IC Pin Switching (PMR16): PMR16 sets whether the P16/IC pin is used as a P16 I/O pin or an IC pin for the input capture input of the prescalar unit. Bit 6 PMR16 0 1 Description The P16/IC pin functions as a P16 I/O pin The P16/IC pin functions as an IC input function (Initial value) 22.3 Noise Cancel Circuit The IC pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such as remote control receiving. The noise cancel circuit samples the input values of the IC pin twice at an interval of 256 states. If the input values are different, they are assumed to be noise. The IC pin can specify enable/disable of the noise cancel function according to the bit 4 (NCon/off) of the prescalar unit control/status register (PCSR). 22.4 22.4.1 Operation Prescalar S (PSS) The PSS is a 17-bit counter that uses the system clock ( = fosc) as an input clock and generates the frequency division clocks (/131072 to /2) of the peripheral function. The low-order 17 bits of the 18-bit free running counter (FRC) correspond to the PSS. The FRC is incremented by one clock. The PSS output is shared by the timer and serial communication interface (SCI), and the frequency division ratio can independently be set by each built-in peripheral function. When reset, the FRC is initialized to H'00000, and starts increment after reset has been released. Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and subsleep mode, the PSS operation is also stopped. In this case, the FRC is also initialized to H'00000. The FRC cannot be read and written from the CPU. Rev.3.00 Jan. 10, 2007 page 429 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit 22.4.2 Prescalar W (PSW) PSW is a counter that uses the subclock as an input clock. The PSW also generates the input clock of the timer A. In this case, the timer A functions as a clock time base. When reset, the PSW is initialized to H'00, and starts increment after reset has been released. Even if the mode has been shifted to the standby mode*, watch mode*, subactive mode*, and subsleep mode*, the PSW continues the operation as long as the clocks are supplied by the X1 and X2 pins. The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode register A (TMA) to 11. Note: * When the timer A is in module stop mode, the operation is stopped. Figure 22.2 shows the supply of the clocks to the peripheral function by the PSS and PSW. /131072 to /2 OSC1 System fosc clock oscillator System clock duty correction circuit Prescalar S Timer SCI OSC2 Medium speed clock frequency divider w/4 TMOW pin X1 Subclock oscillator X2 (fx) w Subclock frequency dividers (1/2, 1/4, and 1/8) w/128 Prescalar W Timer A CPU ROM RAM Peripheral register I/O port System clock selection Figure 22.2 Clock Supply 22.4.3 Stable Oscillation Wait Time Count For the count of the stable oscillation stable wait time during the return from the low power consumption mode excluding the sleep mode, see section 4, Power-Down State. Rev.3.00 Jan. 10, 2007 page 430 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit 22.4.4 8-Bit PWM This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It counts 7 0 the cycle and the duty cycle at 2 to 2 of the FRC. It can be used for controlling reel motors and loading motors. For details, see section 19, 8-Bit PWM. 22.4.5 8-Bit Input Capture Using IC Pin 15 8 This function catches the 8-bit data of 2 to 2 of the FRC according to the edge of the IC pin. It can be used for remote control receiving. For the edge of the IC pin, the rising and falling edges can be selected. The IC pin has a built-in noise cancel circuit. See section 22.3, Noise Cancel Circuit. An interrupt request is generated due to the input capture using the IC pin. Note: Rewriting the ICEG bit, NCon/off bit, or PMR16 bit is incorrectly recognized as edge detection according to the combinations between the state and detection edge of the IC pin and the ICIF bit may be set after up to 384 seconds. 22.4.6 Frequency Division Clock Output The frequency division clock can be output from the TMOW pin. For the frequency division clock, eight types of clocks can be selected according to the DCS2 to DCS0 bits in PCSR. The clock in which the system clock was frequency-divided is output in active mode and sleep mode and the clock in which the subclock was frequency-divided is output in active mode*, sleep mode*, and subactive mode. Note: * When the timer A is in module stop mode, no clock is output. Rev.3.00 Jan. 10, 2007 page 431 of 1038 REJ09B0328-0300 Section 22 Prescalar Unit Rev.3.00 Jan. 10, 2007 page 432 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Section 23 Serial Communication Interface 1 (SCI1) 23.1 Overview The serial communication interface 1 (SCI1) can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 23.1.1 Features SCI1 features are listed below. (1) Choice of asynchronous or clock synchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the SI1 pin level directly in case of a framing error Clock synchronous mode Serial data communication is synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length: 8 bits Receive error detection: Overrun errors detected Rev.3.00 Jan. 10, 2007 page 433 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (2) Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data (3) Built-in baud rate generator allows any bit rate to be selected (4) Choice of serial clock source: internal clock from baud rate generator or external clock from SCK1 pin (5) Four interrupt sources Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently Rev.3.00 Jan. 10, 2007 page 434 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.1.2 Block Diagram Figure 23.1 shows a block diagram of the SCI1. Module data bus RDR1 TDR1 SCMR1 SSR1 SCR1 BRR1 Baud rate generator /4 /16 /64 SI1 RSR SO1 SMR1 Transmission/ reception control Parity gfeneration Clock Parity check TSR SCK1 External clock TEI TXI RXI ERI Legend: RSR RDR1 TSR TDR1 SMR1 SCR1 SSR1 SCMR1 BRR1 : Receive shift register : Receive data register1 : Transmit shift register : Transmit data register1 : Serial mode register1 : Serial control register1 : Serial status register1 : Serial interface mode register1 : Bit rate register1 Figure 23.1 Block Diagram of SCI1 Rev.3.00 Jan. 10, 2007 page 435 of 1038 REJ09B0328-0300 Internal data bus Bus interface Section 23 Serial Communication Interface 1 (SCI1) 23.1.3 Pin Configuration Table 23.1 shows the serial pins used by the SCI1. Table 23.1 SCI Pins Channel 1 Pin Name Serial clock pin 1 Receive data pin 1 Transmit data pin 1 Symbol SCK1 SI1 SO1 I/O I/O Input Output Function SCI1 clock input/output SCI1 receive data input SCI1 transmit data output 23.1.4 Register Configuration The SCI1 has the internal registers shown in table 23.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 23.2 SCI Registers Channel 1 Name Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Serial interface mode register 1 Common Module stop control register Abbrev. SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 MSTPCRH MSTPCRL Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. R/W R/W R/W R/W R/W 2 R/(W)* Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'FF H'FF 1 Address* H'D148 H'D149 H'D14A H'D14B H'D14C H'D14D H'D14E H'FFEC H'FFED R R/W R/W R/W Rev.3.00 Jan. 10, 2007 page 436 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.2 23.2.1 Bit : R/W : Register Descriptions Receive Shift Register (RSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- RSR is a register used to receive serial data. The SCI1 sets serial data input from the SI1 pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR1 automatically. RSR cannot be directly read or written to by the CPU. 23.2.2 Receive Data Register (RDR1) Bit : Initial value : R/W : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R RDR1 is a register that stores received serial data. When the SCI1 has received one byte of serial data, it transfers the received serial data from RSR to RDR1 where it is stored, and completes the receive operation. After this, RSR is receiveenabled. Since RSR and RDR1 function as a double buffer in this way, continuous receive operations can be performed. RDR1 is a read-only register, and cannot be written to by the CPU. RDR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Rev.3.00 Jan. 10, 2007 page 437 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.2.3 Bit : R/W : Transmit Shift Register (TSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a register used to transmit serial data. To perform serial data transmission, the SCI1 first transfers transmit data from TDR1 to TSR, then sends the data to the SO1 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR1 to TSR, and transmission started, automatically. However, data transfer from TDR1 to TSR is not performed if the TDRE bit in SSR1 is set to 1. TSR cannot be directly read or written to by the CPU. 23.2.4 Transmit Data Register (TDR1) Bit : Initial value : R/W : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TDR1 is an 8-bit register that stores data for serial transmission. When the SCI1 detects that TSR is empty, it transfers the transmit data written in TDR1 to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR1 during serial transmission of the data in TSR. TDR1 can be read or written to by the CPU at all times. TDR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Rev.3.00 Jan. 10, 2007 page 438 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.2.5 Serial Mode Register (SMR1) Bit : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR1 is an 8-bit register used to set the SCI1's serial transfer format and select the baud rate generator clock source. SMR1 can be read or written to by the CPU at all times. SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7Communication Mode (C/A): Selects asynchronous mode or clock synchronous mode as the SCI1 operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clock synchronous mode (Initial value) Bit 6Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of TDR1 is not transmitted, and LSBfirst/MSB-first selection is not available. (Initial value) Rev.3.00 Jan. 10, 2007 page 439 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 5Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/E 0 1 Description Even parity* 2 Odd parity* 1 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev.3.00 Jan. 10, 2007 page 440 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 3Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit* 1 (Initial value) 2 2 stop bits* Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 23.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Rev.3.00 Jan. 10, 2007 page 441 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bits 1 and 0Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from , /4, /16, and /64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 23.2.8, Bit Rate Register (BRR1). Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description clock /4 clock /16 clock /64 clock (Initial value) 23.2.6 Serial Control Register (SCR1) Bit : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR1 is a register that performs enabling or disabling of SCI1 transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR1 can be read or written to by the CPU at all times. SCR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR1 to TSR and the TDRE flag in SSR1 is set to 1. Bit 7 TIE 0 1 Note: * Description Transmit-data-empty interrupt (TXI) request disabled* Transmit-data-empty interrupt (TXI) request enabled TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. (Initial value) Rev.3.00 Jan. 10, 2007 page 442 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 6Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR1 and the RDRF flag in SSR1 is set to 1. Bit 6 RIE 0 1 Note: * Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI1. Bit 5 TE 0 1 Description Transmission disabled* 2 Transmission enabled* 1 (Initial value) Notes: 1. The TDRE flag in SSR1 is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR1 and the TDRE flag in SSR1 is cleared to 0. SMR1 setting must be performed to decide the transmission format before setting the TE bit to 1. Bit 4Receive Enable (RE): Enables or disables the start of serial reception by the SCI1. Bit 4 RE 0 1 Description 1 Reception disabled* 2 Reception enabled* (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR1 setting must be performed to decide the reception format before setting the RE bit to 1. Rev.3.00 Jan. 10, 2007 page 443 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 3Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR1 set to 1. The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] (1) When the MPIE bit is cleared to 0 1 (2) When data with MPB = 1 is received Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR1, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR1, is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR1 is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR1 are set to 1) and FER and ORER flag setting is enabled. (Initial value) Bit 2Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation if there is no valid transmit data in TDR1 when the MSB is transmitted. Bit 2 TEIE 0 1 Note: * Description Transmit-end interrupt (TEI) request disabled* Transmit-end interrupt (TEI) request enabled* (Initial value) TEI cancellation can be performed by reading 1 from the TDRE flag in SSR1, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Bits 1 and 0Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI1 clock source and enable or disable clock output from the SCK1 pin. The combination of the CKE1 and CKE0 bits determines whether the SCK1 pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI1's operating mode must be decided using Rev.3.00 Jan. 10, 2007 page 444 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) SMR1 before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 23.9. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Internal clock/SCK1 pin functions as I/O 1 port* Clock synchronous mode Internal clock/SCK1 pin functions as serial 1 clock output* 1 Asynchronous mode Internal clock/SCK1 pin functions as clock 2 output* Clock synchronous mode Internal clock/SCK1 pin functions as serial clock output 1 0 Asynchronous mode External clock/SCK1 pin functions as clock 3 input* Clock synchronous mode External clock/SCK1 pin functions as serial clock input 1 Asynchronous mode External clock/SCK1 pin functions as clock 3 input* Clock synchronous mode External clock/SCK1 pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 23.2.7 Serial Status Register (SSR1) Bit : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written to clear the flag. SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI1, and multiprocessor bits. SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. Rev.3.00 Jan. 10, 2007 page 445 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR1 to TSR and the next serial data can be written to TDR1. Bit 7 TDRE 0 1 Description [Clearing condition] When 0 is written in TDRE after reading TDRE = 1 [Setting conditions] (1) When the TE bit in SCR1 is 0 (2) When data is transferred from TDR1 to TSR and data can be written to TDR1 (Initial value) Bit 6Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR1. Bit 6 RDRF 0 1 Description [Clearing condition] When 0 is written in RDRF after reading RDRF = 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR1 Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. (Initial value) Rev.3.00 Jan. 10, 2007 page 446 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 5Overrun Error (ORER) Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 1 Description [Clearing condition] When 0 is written in ORER after reading ORER = 1 [Setting condition] 2 When the next serial reception is completed while RDRF = 1* (Initial value)* 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR1, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clock synchronous mode, serial transmission cannot be continued, either. Bit 4Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 1 Description [Clearing condition] When 0 is written in FER after reading FER = 1 [Setting condition] When the SCI1 checks the stop bit at the end of the receive data when reception 2 ends, and the stop bit is 0* Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clock synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Rev.3.00 Jan. 10, 2007 page 447 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 3Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written in PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does 2 not match the parity setting (even or odd) specified by the O/E bit in SMR1* Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clock synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Bit 2Transmit End (TEND): Indicates that there is no valid data in TDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 1 Description [Clearing condition] When 0 is written in TDRE after reading TDRE = 1 [Setting conditions] (1) When the TE bit in SCR1 is 0 (2) When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character (Initial value) Rev.3.00 Jan. 10, 2007 page 448 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 1Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Note: * Description [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Retains its previous state when the RE bit in SCR1 is cleared to 0 with multiprocessor format. (Initial value)* Bit 0Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 23.2.8 Bit Rate Register (BRR1) Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR1. BRR1 can be read or written to by the CPU at all times. BRR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Table 23.3 shows sample BRR1 settings in asynchronous mode, and table 23.4 shows sample BRR1 settings in clock synchronous mode. Rev.3.00 Jan. 10, 2007 page 449 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Table 23.3 BRR1 Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 n 1 1 0 0 0 0 0 0 N 141 103 207 103 51 25 12 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.00 2.097152 n 1 1 0 0 0 0 0 0 N 148 108 217 108 54 26 13 6 Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 2.4576 n 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 3 Error (%) n -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 Operating Frequency (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3.6864 n 2 1 1 0 0 0 0 0 0 0 N 64 191 95 191 95 47 23 11 5 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 4 n 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 4.9152 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 5 Error (%) n 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 Rev.3.00 Jan. 10, 2007 page 450 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Operating Frequency (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 6 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 6.144 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 7.3728 n 2 2 1 1 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 8 n 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 Operating Frequency (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 9.8304 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 10 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 Rev.3.00 Jan. 10, 2007 page 451 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Table 23.4 BRR1 Settings for Various Bit Rates (Clock Synchronous Mode) Operating Frequency (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M Legend: Blank: Cannot be set. : Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Note: As far as possible, the setting should be made so that the error is no more than 1%. 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* 4 n 2 2 1 1 0 0 0 0 0 0 0 0 N 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 8 n N 10 n N Rev.3.00 Jan. 10, 2007 page 452 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) The BRR1 setting is found from the following equations. * Asynchronous mode: N= 64 x 22n -1x B x 10 6 - 1 * Clock synchronous mode: N= 8 x 22n -1 x B x 106 - 1 Where B: N: : n: Bit rate (bits/s) BRR1 setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR1 Setting n 0 1 2 3 Clock /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = { (N + 1) x B x 64 x 22n -1 x 106 -1 } x 100 Table 23.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 23.6 and 23.7 show the maximum bit rates with external clock input. Rev.3.00 Jan. 10, 2007 page 453 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Table 23.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 Rev.3.00 Jan. 10, 2007 page 454 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Table 23.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 Table 23.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) (MHz) External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2 4 6 8 10 Rev.3.00 Jan. 10, 2007 page 455 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.2.9 Serial Interface Mode Register (SCMR1) Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : SCMR1 is an 8-bit readable/writable register used to select SCI1 functions. SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 to 4Reserved: These bits cannot be modified and are always read as 1. Bit 3Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR1 contents are transmitted LSB-first Receive data is stored in RDR1 LSB-first TDR1 contents are transmitted MSB-first Receive data is stored in RDR1 MSB-first (Initial value) Bit 2Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR1. Bit 2 SINV 0 1 Description TDR1 contents are transmitted without modification Receive data is stored in RDR1 without modification TDR1 contents are inverted before being transmitted Receive data is stored in RDR1 in inverted form (Initial value) Rev.3.00 Jan. 10, 2007 page 456 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Bit 1Reserved: This bit cannot be modified and is always read as 1. Bit 0Serial Communication Interface Mode Select (SMIF): 1 should not be written in this bit. Bit 0 SMIF 0 1 Description Normal SCI1 mode Reserved mode (Initial value) 23.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit : Initial value : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 MSTP0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset. Bit 0Module Stop (MSTP8): Specifies the SCI1 module stop mode. MSTPCRH Bit 0 MSTP8 0 1 Description SCI1 module stop mode is cleared SCI1 module stop mode is set (Initial value) Rev.3.00 Jan. 10, 2007 page 457 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.3 23.3.1 Operation Overview The SCI1 can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR1 as shown in table 23.8. The SCI1 clock is determined by a combination of the C/A bit in SMR1 and the CKE1 and CKE0 bits in SCR1, as shown in table 23.9. (1) Asynchronous Mode Data length: Choice of 7 or 8 bits Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) Detection of framing, parity, and overrun errors, and breaks, during reception Choice of internal or external clock as SCI1 clock source * When internal clock is selected: The SCI1 operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output * When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) (2) Clock Synchronous Mode Transfer format: Fixed 8-bit data Detection of overrun errors during reception Choice of internal or external clock as SCI1 clock source * When internal clock is selected: The SCI1 operates on the baud rate generator clock and a serial clock is output off-chip * When external clock is selected: The built-in baud rate generator is not used, and the SCI1 operates on the input serial clock Rev.3.00 Jan. 10, 2007 page 458 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Table 23.8 SMR1 Settings and Serial Transfer Format Selection SMR1 Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 Clock synchronous mode 8-bit data No Asynchro-nous 8-bit data Yes mode (multiprocessor 7-bit data format) No Yes 7-bit data No Mode SCI1 Transfer Format Data length Multiprocessor bit Parity bit No Stop bit length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Asynchro-nous 8-bit data No mode Table 23.9 SMR1 and SCR1 Settings and SCI1 Clock Source Selection SMR1 Bit 7 C/A 0 SCR1 Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clock synchronous mode Internal Mode Asynchronous mode SCI1 Transfer Clock Clock Source Internal SCK1 Pin Function SCI1 does not use SCK1 pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock External Inputs serial clock Rev.3.00 Jan. 10, 2007 page 459 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI1, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 23.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI1 monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI1 performs synchronization at the falling edge of the start bit in reception. The SCI1 samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 P arity bit 1 1 Stop bit(s) 1 Transmit/receive data 7 or 8 bits 1 bit 1 bit, 1 or 2 bits or none One unit of transfer data (character or frame) Figure 23.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev.3.00 Jan. 10, 2007 page 460 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (1) Data Transfer Format Table 23.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR1. Table 23.10 Serial Transfer Formats (Asynchronous Mode) SMR1 Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data S 8-bit data STOP STOP S 8-bit data P STOP S 8-bit data P STOP STOP S 7-bit data STOP S 7-bit data STOP STOP S 7-bit data P STOP S 7-bit data P STOP STOP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data MPB STOP S 7-bit data MPB STOP STOP Legend: S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit Rev.3.00 Jan. 10, 2007 page 461 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (2) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK1 pin can be selected as the SCI1's serial clock, according to the setting of the C/A bit in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI1 clock source selection, see table 23.9. When an external clock is input at the SCK1 pin, the clock frequency should be 16 times the bit rate used. When the SCI1 is operated on an internal clock, the clock can be output from the SCK1 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 23.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 23.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Rev.3.00 Jan. 10, 2007 page 462 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (3) Data Transfer Operations (a) SCI1 Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI1 as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR1. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. Figure 23.4 shows a sample SCI1 initialization flowchart. Start initialization [1] Set the clock selection in SCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR1 settings are made. [1] [2] Set the data transfer format in SMR1 and SCMR1. [3] Write a value corresponding to the bit rate to BRR1. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the SO1 and SI1 pins to be used. Clear TE and RE bits in SCR1 to 0 Set CKE1 and CKE0 bits in SCR1 (TE, RE bits 0) Set data transfer format in SMR1 and SCMR1 Set value in BRR1 Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Figure 23.4 Sample SCI Initialization Flowchart Rev.3.00 Jan. 10, 2007 page 463 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (b) Serial Data Transmission (Asynchronous Mode) Figure 23.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI1 initialization: The SO1 pin is automatically designated as the transmit data output pin. [2] SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag is set to 1, then write transmit data to TDR1 and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR1, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set PCR for the port corresponding to the SO1 pin to 1, clear PDR to 0, then clear the TE bit in SCR1 to 0. Read TDRE flag in SSR1 [1] No TDRE = 1 Yes Write transmit data to TDR1 and clear TDRE flag in SSR1 to 0 No All data transmitted? Yes [3] Read TEND flag in SSR1 No TEND = 1 Yes No Break output? Yes Clear PDR to 0 and set PCR to 1 [4] Clear TE bit in SCR1 to 0 < End > Figure 23.5 Sample Serial Transmission Flowchart Rev.3.00 Jan. 10, 2007 page 464 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) In serial transmission, the SCI1 operates as described below. [1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR. [2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the SO1 pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI1 checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR1 to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to 1 at this time, a TEI interrupt request is generated. Figure 23.6 shows an example of the operation for transmission in asynchronous mode. Rev.3.00 Jan. 10, 2007 page 465 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Start bit Data D0 D1 D7 1 Parity Stop bit bit Start bit Data D0 D1 D7 Parity bit Stop bit 0 0/1 1 0 0/1 1 Idle state 1 (mark state) TDRE TEND TXI interrupt Data written to TDR1 and request TDRE flag cleared to 0 generated in TXI interrupt handling routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 23.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.3.00 Jan. 10, 2007 page 466 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (c) Serial Data Reception (Asynchronous Mode) Figure 23.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization Start reception [1] [1] SCI1 initialization: The SI1 pin is automatically designated as the receive data input pin. [2][3] Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the SI1 pin. [4] SCI1 status check and receive data read: Read SSR1 and check that RDRF = 1, then read the receive data in RDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR1, and clear the RDRF flag to 0. Read ORER, PER, FER flags in SSR1 [2] PER FER ORER = 1 No Yes [3] Error handling (Continued on next page) Read RDRF flag in SSR1 [4] No RDRF = 1 Yes Read receive data in RDR1, and clear RDRF flag in SSR1 to 0 No All data received? Yes Clear RE bit in SCR1 to 0 < End > [5] Figure 23.7 Sample Serial Reception Data Flowchart (1) Rev.3.00 Jan. 10, 2007 page 467 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) [3] Error handling No ORER = 1 Yes Overrun error handling No FER = 1 Yes Yes Break? No Framing error handling Clear RE bit in SCR1 to 0 No PER = 1 Yes Parity error handling Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 23.7 Sample Serial Reception Data Flowchart (2) Rev.3.00 Jan. 10, 2007 page 468 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) In serial reception, the SCI1 operates as described below. [1] The SCI1 monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI1 carries out the following checks. [a] Parity check: The SCI1 checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR1. [b] Stop bit check: The SCI1 checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI1 checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR1. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR1. If a receive error* is detected in the error check, the operation is as shown in table 23.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. Table 23.11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbrev. ORER Occurrence Condition When the next data reception is completed while the RDRF flag in SSR1 is set to 1 When the stop bit is 0 Data Transfer Receive data is not transferred from RSR to RDR1 Receive data is transferred from RSR to RDR1 Framing error Parity error FER PER When the received data differs from Receive data is transferred from the parity (even or odd) set in RSR to RDR1 SMR1 Rev.3.00 Jan. 10, 2007 page 469 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Figure 23.8 shows an example of the operation for reception in asynchronous mode. Start bit Data D0 D1 D7 1 Parity Stop bit bit Start bit Data D0 D1 D7 Parity Stop bit bit 0 0/1 1 0 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt RDR1 data read and RDRF flag request cleared to 0 in generation RXI interrupt handling routine 1 frame ERI interrupt request generated by framing error Figure 23.8 Example of SCI1 Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 23.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 23.9 shows an example of inter-processor communication using a multiprocessor format. Rev.3.00 Jan. 10, 2007 page 470 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (1) Data Transfer Format There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 23.10. (2) Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle: receiving station specification H'AA (MPB = 0) Data transmission cycle: data transmission to receiving station specified by ID Legend: MPB : Multiprocessor bit Figure 23.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) (3) Data Transfer Operations (a) Multiprocessor Serial Data Transmission Figure 23.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Rev.3.00 Jan. 10, 2007 page 471 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Initialization Start transmission [1] [1] SCI1 initialization: The SO1 pin is automatically designated as the transmit data output pin. [2] SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag is set to 1, then write transmit data to TDR1. Set the MPBT bit in SSR1 to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR1, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR1 to 0. Read TDRE flag in SSR1 [2] No TDRE = 1 Yes Write transmit data to TDR1 and set MPBT bit in SSR1 Clear TDRE flag to 0 No Transmission end? Yes [3] Read TEND flag in SSR1 No TEND = 1 Yes No Break output? Yes [4] Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR1 to 0 < End > Figure 23.10 Sample Multiprocessor Serial Transmission Flowchart Rev.3.00 Jan. 10, 2007 page 472 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) In serial transmission, the SCI1 operates as described below. [1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR. [2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the SO2 pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI1 checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. Rev.3.00 Jan. 10, 2007 page 473 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Figure 23.11 shows an example of SCI1 operation for transmission using a multiprocessor format. Multiprocessor Stop bit bit Multiprocessor Stop bit bit 1 1 Start bit Data D0 D1 D7 Start bit Data D0 D1 D7 0 0/1 1 0 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR1 and TDRE flag cleared to 0 request in TXI interrupt handling general routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 23.11 Example of SCI1 Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) (b) Multiprocessor Serial Data Reception Figure 23.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Rev.3.00 Jan. 10, 2007 page 474 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Initialization Start reception [1] [1] SCI1 initialization: The SI1 pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR1 to 1. [3] SCI1 status check, ID reception and comparison: Read SSR1 and check that the RDRF flag is set to 1, then read the receive data in RDR1 and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI1 status check and data reception: Read SSR1 and check that the RDRF flag is set to 1, then read the data in RDR1. [5] Receive error handling and break detectioon: If a receive error occurs, read the ORER and FER flags in SSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the SI1 in value. Set MPIE bit in SCR1 to 1 Read ORER and FER flags in SSR1 FER ORER = 1 No Read RDRF flag in SSR1 No RDRF = 1 Yes Read receive data in RDR1 No This station's ID? Yes Read ORER and FER flags in SSR1 [2] Yes [3] FER ORER = 1 No Read RDRF flag in SSR1 Yes [4] No RDRF = 1 Yes Read receive data in RDR1 No All data received? Yes Clear RE bit in SCR1 to 0 < End > (Continued on next page) [5] Error handling Figure 23.12 Sample Multiprocessor Serial Reception Flowchart (1) Rev.3.00 Jan. 10, 2007 page 475 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) [5] Error handling No ORER = 1 Yes Overrun error handling No FER = 1 Yes Yes Break? No Framing error handling Clear RE bit in SCR1 to 0 Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 23.12 Sample Multiprocessor Serial Reception Flowchart (2) Figure 23.13 shows an example of SCI1 operation for multiprocessor format reception. Rev.3.00 Jan. 10, 2007 page 476 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 1 Start bit Data (ID1) D0 D1 D7 1 Stop MPB bit 1 Start bit Data (Data 1) D0 D1 D7 0 Stop MPB bit 1 1 Idle state (mark state) 0 0 MPIE RDRF RDR1 value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR1 data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR1 retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) D0 D1 D7 1 Stop MPB bit 1 Start bit Data (Data 2) D0 D1 D7 0 Stop MPB bit 1 1 Idle state (mark state) 0 0 MPIE RDRF RDR1 value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR1 data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 23.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.3.00 Jan. 10, 2007 page 477 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.3.4 Operation in Clock Synchronous Mode In clock synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI1, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 23.14 shows the general format for clock synchronous serial communication. One unit of transfer data (character or frame) * * Synchronous clock LSB MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Serial data Don't care Bit 0 Don't care Note: * High except in continuous transmit/reception Figure 23.14 Data Format in Clock Synchronous Communication In clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In clock synchronous serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clock synchronous mode, the SCI1 receives data in synchronization with the rising edge of the serial clock. (1) Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. (2) Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK1 pin can be selected, according to the setting of the C/A bit in SMR1 and the CKE1 and CKE0 bits in SCR1. For details on SCI1 clock source selection, see table 23.9. When the SCI1 is operated on an internal clock, the serial clock is output from the SCK1 pin. Rev.3.00 Jan. 10, 2007 page 478 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, select an external clock as the clock source. (3) Data Transfer Operations (a) SCI1 Initialization (Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI1 as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR1. Figure 23.15 shows a sample SCI1 initialization flowchart. Rev.3.00 Jan. 10, 2007 page 479 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) [1] Set the clock selection in SCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR1 and SCMR1. [1] [3] Write a value corresponding to the bit rate to BRR1. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the SO1 and SI1 pins to be used. Start initialization Clear TE and RE bits in SCR1 to 0 Set CKE1 and CKE0 bits in SCR1 (TE, RE bits 0) Set data transfer format in SMR1 and SCMR1 Set value in BRR1 Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Figure 23.15 Sample SCI Initialization Flowchart Rev.3.00 Jan. 10, 2007 page 480 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (b) Serial Data Transmission (Clock Synchronous Mode) Figure 23.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI1 initialization: The SO1 pin is automatically designated as the transmit data output pin. [2] SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag is set to 1, then write transmit data to TDR1 and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR1, and then clear the TDRE flag to 0. Read TDRE flag in SSR1 [2] No TDRE = 1 Yes Write transmit data to TDR1 and clear TDRE flag in SSR1 to 0 No All data transmitted? Yes [3] Read TEND flag in SSR1 No TEND = 1 Yes Clear TE bit in SCR1 to 0 < End > Figure 23.16 Sample Serial Transmission Flowchart Rev.3.00 Jan. 10, 2007 page 481 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) In serial transmission, the SCI1 operates as described below. [1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR. [2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. When clock output mode has been set, the SCI1 outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI1 checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the MSB (bit 7) is sent, and the SO1 pin maintains its state. If the TEIE bit in SCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. [4] After completion of serial transmission, the SCK1 pin is held in a constant state. Figure 23.17 shows an example of SCI1 operation in transmission. Transfer direction Synchronous clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR1 and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 23.17 Example of SCI1 Operation in Transmission Rev.3.00 Jan. 10, 2007 page 482 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (c) Serial Data Reception (Clock Synchronous Mode) Figure 23.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Rev.3.00 Jan. 10, 2007 page 483 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Initialization Start reception [1] [1] SCI1 initialization: The SI1 pin is automatically designated as the receive data input pin. [2][3] Receive error handling: IF a receive error occurs, read the ORER flag in SSR1, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI1 status check and receive data read: Read SSR1 and check that the RDRF flag is set to 1, then read the receive data in RDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by and RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR1, and clearing the RDRF flag to 0 Read ORER flag in SSR1 Yes ORER = 1 No [2] [3] Error handling (Continued below) Read RDRF flag in SSR1 [4] No RDRF = 1 Yes Read receive data in RDR1, and clear RDRF flag in SSR1 to 0 No All data received? Yes Clear RE bit in SCR1 to 0 < End > [3] Error handling [5] Overrun error handling Clear ORER flag in SSR1 to 0 < End > Figure 23.18 Sample Serial Reception Flowchart Rev.3.00 Jan. 10, 2007 page 484 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) In serial reception, the SCI1 operates as described below. [1] The SCI1 performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI1 checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR1. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR1. If a receive error is detected in the error check, the operation is as shown in table 23.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 23.19 shows an example of SCI1 operation in reception. Synchronous clock Serial data RDRF ORER Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request generated RDR1 data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Figure 23.19 Example of SCI1 Operation in Reception (d) Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 23.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Rev.3.00 Jan. 10, 2007 page 485 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) [1] SCI1 initialization: The SO1 pin is designated as the transmit data output pin, and the SI1 pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag is set to 1, then write transmit data to TDR1 and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR1, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI1 status check and receive data read: Read SSR1 and check that the RDRF flag is set to 1, then read the receive data in RDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR1, and clearing the RDRF flag to 0. Also before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR1 and clear Initialization Start transfer [1] Read TDRE flag in SSR1 No TDRE = 1 Yes Write transmit data to TDR1 and clear TDRE flag in SSR1 to 0 [2] Read ORER flag in SSR1 Yes [3] Error handling ORER = 1 No Read RDRF flag in SSR1 No RDR = 1 Yes Read receive data in RDR1, and clear RDRF flag in SSR1 to 0 [4] No All data received? Yes Clear TE and RE bits in SCR1 to 0 [5] < End > Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 23.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.3.00 Jan. 10, 2007 page 486 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.4 SCI1 Interrupts The SCI1 has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 23.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR1. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR1 is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR1 is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR1 is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR1 is set to 1, an ERI interrupt request is generated. Table 23.12 SCI1 Interrupt Sources Channel 1 Interrupt Source ERI RXI TXI TEI Description Interrupt by receive error (ORER, FER, or PER) Interrupt by receive data register full (RDRF) Interrupt by transmit data register empty (TDRE) Interrupt by transmit end (TEND) Low Priority* High The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance, and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be accepted in this case. Rev.3.00 Jan. 10, 2007 page 487 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) 23.5 Usage Notes The following points should be noted when using the SCI1. (1) Relation between Writes to TDR1 and the TDRE Flag The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred from TDR1 to TSR. When the SCI1 transfers data from TDR1 to TSR, the TDRE flag is set to 1. Data can be written to TDR1 regardless of the state of the TDRE flag. However, if new data is written to TDR1 when the TDRE flag is cleared to 0, the data stored in TDR1 will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR1. (2) Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR1 is as shown in table 23.13. If there is an overrun error, data is not transferred from RSR to RDR1, and the receive data is lost. Table 23.13 State of SSR1 Status Flags and Transfer of Receive Data SSR1 Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 x x x Receive Data Transfer RSR RDR1 Receive Errors x Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR1. x: Receive data is not transferred from RSR to RDR1. (3) Break Detection and Processing When a framing error (FER) is detected, a break can be detected by reading the SI1 pin value directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI1 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Rev.3.00 Jan. 10, 2007 page 488 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) (4) Sending a Break The SO1 pin has a dual function as an I/O port whose direction (input or output) is determined by PDR and PCR. This feature can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of PDR (the pin does not function as the SO1 pin until the TE bit is set to 1). Consequently, PCR and PDR for the port corresponding to the SO1 pin should first be set to 1. To send a break during serial transmission, first clear PDR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the SO1 pin becomes an I/O port, and 0 is output from the SO1 pin. (5) Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. (6) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI1 operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI1 samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock. This is illustrated in figure 23.21. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 23.21 Receive Data Sampling Timing in Asynchronous Mode Rev.3.00 Jan. 10, 2007 page 489 of 1038 REJ09B0328-0300 Section 23 Serial Communication Interface 1 (SCI1) Thus the receive margin in asynchronous mode is given by equation (1) below. M = (0.5 - D - 0.5 1 ) - (L - 0.5) F - (1 + F ) x 100% 2N N .....(1) Where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by equation (2) below. When D = 0.5 and F = 0, M = (0.5 - = 46.875% 1 ) x 100% 2 x 16 .....(2) However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in system design. Rev.3.00 Jan. 10, 2007 page 490 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) Section 24 Serial Communication Interface 2 (SCI2) 24.1 Overview The serial communication interface 2 (SCI2) that has a 32-byte data buffer carries out clocked synchronous serial transmission of 32 bytes by a single operation. 24.1.1 Features SCI2 features are listed below. * 32 bytes data transfer can be automatically carried out * Choice of 7 internal clocks (/256, /64, /32, /16, /8, /4, and /2) and an external clock as serial clock source * Interrupt occurs when transmission has been completed or an error has occurred * Data transfer at intervals of 1 byte can be set Data transfer can be carried out at intervals of 1 byte. The interval can be selected from a multiple of internal clock cycle by 56, 24, or 8 times * Start of data transfer can be controlled by input of chip select * Strobe pulse is output for each 1-byte transfer Rev.3.00 Jan. 10, 2007 page 491 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.1.2 Block Diagram Figure 24.1 shows a block diagram of the SCI2. Internal clock /256, /64, /32, /16, /8, /4, /2 SCK2 STAR STRB CS Transmit/ receive control circuit EDAR SCR2 SCSR2 SO2 SCK2 Shift register Data buffer (32 bytes) SI2 Interrupt generation circuit Interrupt request Legend: STAR : Starting address register EDAR : Ending address register SCR2 : Serial control register 2 SCSR2 : Serial control status register SCK2 : SCI2 clock input/output pin STRB : SCI2 strobe signal output pin CS : SCI2 chip select signal input pin SO2 : SCI2 transmit data output pin SI2 : SCI2 receive data input pin Figure 24.1 Block Diagram of SCI2 Rev.3.00 Jan. 10, 2007 page 492 of 1038 REJ09B0328-0300 Internal data bus Section 24 Serial Communication Interface 2 (SCI2) 24.1.3 Pin Configuration Table 24.1 shows pin configuration of the SCI2. Table 24.1 Pin Configuration Name SCI2 Clock SCI2 Data input SCI2 Data output SCI2 Strobe SCI2 Chip select Abbrev. SCK2 SI2 SO2 STRB CS I/O I/O Input Output Output Input Function SCI2 clock input/output pin SCI2 receive data input pin SCI2 transmit data output pin SCI2 strobe signal output pin SCI2 chip select signal input pin 24.1.4 Register Configuration Table 24.2 shows register configuration of the SCI2. Table 24.2 Register Configuration Name Starting address register Ending address register Serial control register 2 Serial control status register 2 Serial data buffer (32 bytes) Note: * Abbrev. STAR EDAR SCR2 SCSR2 R/W R/W R/W R/W R/W R/W Initial Value H'E0 H'E0 H'20 H'60 Undefined Address* H'D0E0 H'D0E1 H'D0E2 H'D0E3 H'D0C0 to H'D0DF Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 493 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.2 24.2.1 Register Descriptions Starting Address Register (STAR) Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STA4 0 R/W 3 STA3 0 R/W 2 STA2 0 R/W 1 STA1 0 R/W 0 STA0 0 R/W Initial value : R/W : The STAR is a readable/writable register that specifies the transfer starting address within the address space (H'FFD0C0 to H'FFD0DF) to which a 32-byte data buffer is assigned. The 5 loworder bits of the STAR correspond to the 5 low-order bits of the address of 32-byte buffer. The range for executing continuous data transfer on STAR and EDAR is specified. When the value of STAR is equal to that of EDAR, only one-byte transfer is carried out. Since the 7 to 5 bits of the STAR are reserved, writes are disabled. When each bit is read, 1 is read at all times. The STAR is initialized to H'E0 by a reset. 24.2.2 Ending Address Register (EDAR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 EDA4 0 R/W 3 EDA3 0 R/W 2 EDA2 0 R/W 1 EDA1 0 R/W 0 EDA0 0 R/W The EDAR is a readable/writable register that specifies the transfer ending address within the address space (H'FFD0C0 to H'FFD0DF) to which 32-byte data buffer is assigned. The 5 loworder bits of EDAR correspond to the 5 low-order bits of the address of 32-byte buffer. The range for executing continuous data transfer is specified by the EDAR and the STAR. If the value of the STAR is equal to that of the EDAR, only one-byte transfer is carried out. Since the 7 to 5 bits of the EDAR are reserved, writes are disabled. When each bit is read, 1 is read at all times. The EDAR is initialized to H'E0 by a reset. Rev.3.00 Jan. 10, 2007 page 494 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.2.3 Serial Control Register 2 (SCR2) Bit : 7 TEIE 0 R/W 6 ABTIE 0 R/W 5 -- 1 -- 4 GAP1 0 R/W 3 GAP0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : The SCR 2 is a readable/writable register that enables or disables generation of SCI2 interrupt and selects an data transfer interval and transfer clock when an internal clock is used. The SCR2 is initialized to H'20 by a reset. Bit 7Transmit End Interrupt Enable (TEIE): Enables or disables the occurrence of transmitend interrupt when data transfer has been completed and TEI of the SCR2 has been set to 1. Bit 7 TEIE 0 1 Description Transmit-end interrupt disabled Transmit-end interrupt enabled (Initial value) Bit 6Transmit Cutoff Interrupt (ABTIE): Enables or disables the occurrence of transmitcutoff interrupt when the CS pin has entered a high level during transmission and ABT of the SCRS2 has been set to 1. Bit 6 ABTIE 0 1 Description Transmit-cutoff interrupt disabled Transmit-cutoff interrupt enabled (Initial value) Bit 5Reserved: When read, 1 is read at all times. Writes are disabled. Rev.3.00 Jan. 10, 2007 page 495 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) Bits 4 and 3Transmit Data Interval Select 1 and 0 (GAP1, GAP0): When an internal clock is used, data can be transmitted at 1-byte intervals. During that time, the SCK2 pin retains the high level. When data is transmitted without intervals, the STRB signal retains the low level. Bit 4 GAP1 0 0 1 1 Bit 3 GAP0 0 1 0 1 Description Data transmission without intervals Data intervals: 8 clocks Data intervals: 24 clocks Data intervals: 56 clocks (Initial value) Bits 2 to 0Transfer Clock Select 2 to 0 (CKS2 to CKS0): Selects transfer clock. Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 SCK2 inputExternal clock Clock SCK2 Pin Source SCK2 output Prescaler Division Ratio /64 /32 /16 /8 /4 /2 Transfer Clock Cycle = 10 MHz = 5 MHz 25.6 s 6.4 s 3.2 s 1.6 s 0.8 s 0.4 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s 0.4 s Prescaler S /256 (Initial value) Rev.3.00 Jan. 10, 2007 page 496 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.2.4 Serial Control Status Register 2 (SCSR2) Bit : 7 TEI 6 -- 5 -- 4 SOL 0 R/W 3 ORER 0 R/(W)* 2 WT 0 R/(W)* 1 ABT 0 R/(W)* 0 STF 0 R/W Initial value : 0 1 1 R/(W)* R/W : -- -- Note: * Only 0 can be written to clear the flag. The SCSR2 is an 8-bit register that indicates the SCI2's state of operation and error. The SCSR2 is initialized to H'60 by a reset. Bit 7Transmit End Interrupt Request Flag (TEI): Indicates that data transmission or reception has been completed. Bit 7 TEI 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When transmission or reception has been completed (Initial value) Bits 6 and 5Reserved: When each bit is read, 1 is read at all times. Writes are disabled. Bit 4Extension Data Bit (SOL): The SOL sets the output level of the SO2 pin. When read, the output level of the SO2 pin is read. Output of the SO2 pin after completion of transmission retains the value of final bit of transfer data, but the output level of the SO2 pin can be changed by operating this bit before or after transmission. However, setting of the SOL bit becomes invalid when the next transmission is started. Therefore, if the output level of the SO2 pin is changed after completion of transmission, write operation for SOL must be performed every time when transmission is terminated. Since writing to this register during data transfer may cause malfunction, write operation must not be performed during transmission. Bit 4 SOL 0 Description Read Write 1 Read Write The SO2 pin output is at a low level The SO2 pin output is changed to a low level The SO2 pin output is at a high level The SO2 pin output is changed to a high level (Initial value) Rev.3.00 Jan. 10, 2007 page 497 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) Bit 3Overrun Error Flag (ORER): The ORER indicates an occurrence of overrun error while an external clock is used. When excessive pulses are overlapped with the normal transfer clock caused by external noise, etc. during transmission, this bit is set to 1. At this time data transfer cannot be assured. When a clock is input after completion of transmission, it is also found to be in the state of overrun and this bit is set to 1. However, overrun is not detected when the CS pin is at a high level. Bit 3 ORER 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When excessive pulses are overlapped with a normal transfer clock while an external clock is used, or when a clock is input after completion of transmission (Initial value) Bit 2Wait Flag (WT): The WT indicates that read/ or write to serial data buffer (32 bytes) has been executed during transmission and in the CS input standby mode. The instruction at that time is ignored and this bit is set to 1. Bit 2 WT 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] When an instruction to read/write to serial data buffer (32 bits) is directed during transmission and in the CS input standby mode (Initial value) Rev.3.00 Jan. 10, 2007 page 498 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) Bit 1Abort Flag (ABT): The ABT indicates that the CS pin has entered a high level during transmission. When a high level of the CS pin is detected during transfer, the transfer is immediately cut off, and this bit is set to 1, and then the SCK2 and SO2 pins go into the high impedance state. At this time values of internal registers other than SCSR2 and serial data buffer (32 bytes) are retained. Transfer cannot be carried out while this bit is set to 1. Resume transfer after clearing to 0. Bit 1 ABT 0 1 Description [Clearing condition] When 0 is written after reading 1 [Setting condition] During transfer and when CS pin has entered a high level (Initial value) Bit 0Start Flag (STF): The STF controls the start of transfer operations. When this bit is set to 1 and PMR30 of PMR3 is 0, transfer operation of the SCI2 is started. When PMR30 of PMR3 is 1, the low level of the CS pin is detected and transfer is started. This bit retains 1 during transfer and in the CS input standby mode, and it is cleared to 0 after completion of transfer and when transfer is cut off by the CS pin. Therefore, this bit can be used as a busy flag. When this bit is cleared to 0 during transfer, the transfer is cut off and the SCI2 is initialized. At this time the contents of internal registers other than the SCSR2 and the serial data buffer (32 bytes) are retained. Bit 0 STF 0 Description Read Write 1 Read Write Transfer operations stops Transfer operation discontinues and the SCI2 is initialized During transfer operation or in CS input standby mode Transfer operation starts (Initial value) Rev.3.00 Jan. 10, 2007 page 499 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.2.5 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTPCR is set to 1, the SCI2 stops at the end of bus cycle and a transition is made to the module stop mode. For details, see section 4.5 Module Stop Mode. The MSTPCR is initialized to H'FFFF by a reset. Bit 7Module Stop (MSTP7): Specifies the SCI2 module stop mode. MSTPCRL Bit 7 MSTP7 0 1 Description SCI2 module stop mode is cleared SCI2 module stop mode is set (Initial value) Rev.3.00 Jan. 10, 2007 page 500 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.3 Operation The SCI2, comprising 32 bytes serial data buffer, can continuously transmit a maximum of 32 bytes data by a single operation, synchronized with clock pulse. Installation of a register enables to select transmit, receive, or simultaneous transmit/receive. When transmit is set, the value of serial data buffer is retained even after completion of transmission. An internal or external clock can be selected as transfer clock. When an internal clock is selected, data can be transmitted at 1-byte intervals. The strobe signal can also be output from the STRB pin. When an external clock is selected, malfunction due to clock can be detected by the overrun flag. The start of transfer and its forced cutoff can be controlled by CS input. Forced cutoff can be detected by the abort flag. 24.3.1 Clock Selection of a transfer clock can be made from seven internal clocks and an external clock. When an internal clock is selected, the SCK2 pin becomes a clock output pin. 24.3.2 Data Transfer Format Figures 24.2 and 24.3 show transfer format of the SCI2. LSB-first transfer that allows to transmit/receive from the lowest-order bit of data is performed. Transmit data is output from the fall of the transfer clock to its next fall. Receive data is collected at the rise of the transfer clock. When an internal clock is selected as a transfer clock, data can be transferred at intervals of 1 byte. The SCK2 output is retained at a high level between transfer data. The strobe signal can be output from the STRB pin. Selection of interval of transfer data is set at GAP1 or GAP0. Rev.3.00 Jan. 10, 2007 page 501 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 SO2/SI2 Figure 24.2 Transfer Format (Transfer Data without Intervals) Rev.3.00 Jan. 10, 2007 page 502 of 1038 REJ09B0328-0300 STRB SCK2 CS Start of transfer Bit 0 Bit 1 End of transfer Bit 7 8, 24, and 56 clocks SCK2 SO2/SI2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 CS STRB End of transfer Figure 24.3 Transfer Format (Transfer Data with Intervals) Section 24 Serial Communication Interface 2 (SCI2) Rev.3.00 Jan. 10, 2007 page 503 of 1038 REJ09B0328-0300 Start of transfer Section 24 Serial Communication Interface 2 (SCI2) 24.3.3 Data Transfer Operations (1) SCI2 Initialization To carry out data transfer, first initialize the SCI2 using software. Initialization is performed as described below: (1) Use PMR2, PMR3, STAR, EDAR, and SCR2 to set the pin and transmission mode while STF of SCSR2 is set to 0. (2) The SCI2 pin is also used as a port. Switching of a port is performed on PMR3. The SO2 pin allows to select CMOS output or NMOS open drain output on PMR2. Transfer clock and transfer data intervals can be set on SCR2. (3) The starting and ending addresses in the transfer data area are set on STAR and EDAR. If the value of the ending address is smaller than that of the starting address, transfer data at H'FFD0DF and then return to H'FFD0C0 so that transfer to the ending address can be carried out as shows in figure 24.4. If the value of the starting address is equal to that of the ending address is equal, perform one-byte transfer. H'FFD0C0 End Ending address Start Starting address H'FFD0DF Figure 24.4 If the Value of the Ending Address Is Smaller Than That of the Starting Address Rev.3.00 Jan. 10, 2007 page 504 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) (2) Transmit Operations Transmit operations are performed as described below: (1) Set PMR26 and PMR27 of PMR2 to 1 and set them to the SO2 and SCK2 pins, respectively. Set the SO2 pin to the open drain output using PMR20 of PMR2 and set them to the CS and STRB pins, respectively, using PMR30 and PMR31 of PMR3, as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2. (3) Write transmit data to serial data buffer. In transmit operations, the contents of the data buffer will be retained even after the end of transmission. When the same data is transmitted again, it is not necessary to write data. (4) Set STAR to the 5 low-order bits at the transmission starting address and EDAR to the 5 low-order bits at the transmission ending address. (5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF. While PMR30 of PMR3 is set to 1, transmission is started when low level of the CS pin is detected. (6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0. When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of starting transmission. When transmission has been completed, synchronous clock is not output until the next STF is set. During that time, the SO2 pin continues to output the value of final bit of the immediately preceding data. When an external clock is selected, data is transmitted, synchronized with the clock input from the SCK2 pin. If the synchronous clock is continuously input after completion of transmission, no transmission is performed as the overrun state has been found and then ORER of the SCSR2 is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data. However, if the CS of PMR3 is set to 1, overrun is not detected when the CS pin is at a high level. The output value of the SO2 pin while transmission is being stopped can be changed by SOL of SCSR2. Data buffer cannot be read or written from CPU during transmission or in the CS standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write instruction is executed, buffer does not change. When a Read/Write instruction has been executed during transmission or in the CS input standby mode, WT of the SCSR2 is set. While PMR30 of PMR3 is set to 1, transmission is immediately cut off when a high level of the CS pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0. The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to 0. Rev.3.00 Jan. 10, 2007 page 505 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) (3) Receive Operations Receive operations are performed as described below: (1) Set PMR25 and PMR27 of PMR2 to 1 and set them to the SI2 and SCK2 pins, respectively. Set them to the CS pin, using PMR30 of PMR3 as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2. (3) Set STAR to 5 low-order bits at the receive starting address and EDAR to 5 low-order bits at the receive ending address. This enables to determine the area in the serial data buffer where receive data is stored. (4) Set STF to 1. When PMR30 of PMR3 is set to 0, reception is started by setting STF. While PMR30 of PMR3 is set to 1, reception is started when low level of the CS pin is detected. (5) After completion of reception, TEI of SCSR2 is set to 1. STF is cleared to 0. (6) Read the receive data stored from the serial data buffer. When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of starting reception. When reception has been completed, synchronous clock is not output until the next STF is set. When an external clock is selected, data is received, synchronized with the clock input from the SCK2 pin. If the synchronous clock is continuously input after completion of reception, no reception is performed as the overrun state has been found and then ORER of the SCSR2 is set to 1. However, if the CS of PMR3 is set to 1, overrun is not detected when the CS pin is at a high level. Data buffer cannot be read or written from CPU during reception or in the CS standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write instruction is executed, buffer does not change. When a Read/Write instruction has been executed during reception or in the CS input standby mode, WT of the SCSR2 is set. While CS of PMR3 is set to 1, transmission is immediately cut off when a high level of the CS pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0. The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to 0. Rev.3.00 Jan. 10, 2007 page 506 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) (4) Simultaneous Transmit/Receive Operations Simultaneous transmit/receive operations are performed as described below: (1) Set PMR25, PMR26 and PMR27 of PMR2 to 1 and set them to the SI2, SO2 and SCK2 pins, respectively. Set the SO2 pin to open drain output, using PMR20 of PMR2, and set them to the CS and STRB pins, respectively, using PMR30 and PMR31, as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2. (3) Write transmit data to serial data buffer. In the simultaneous transmit/receive operations, the receive data is stored in the same address alternately with the transmit data. (4) Set STAR to 5 low-order bits at the transmission starting address and EDAR to 5 low-order bits at the transmission ending address. (5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF. While PMR30 of PMR3 is set to 1, transmission is started when low level of the CS pin is detected. (6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0. (7) Read the receive data stored from the serial data buffer. When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of starting transmission. When transmission has been completed, synchronous clock is not output until the next STF is set. During that time, the SO2 pin continues to output the value of final bit of the preceding data. When an external clock is selected, data is transmitted, synchronized with the clock input from the SCK2 pin. If the synchronous clock is continuously input after completion of transmission, no transmission is performed as the overrun state has been found and then ORER of the SCSR2 is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data. However, if the CS of PMR3 is set to 1, overrun is not detected when the CS pin is at a high level. The output value of the SO2 pin while transmission is being stopped can be changed by SOL of SCSR2. Data buffer cannot be read or written from CPU during transmission or in the CS standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write instruction is executed, buffer does not change. When a Read/Write instruction has been executed during transmission or in the CS input standby mode, WT of the SCSR2 is set. While the CS of PMR3 is set to 1, transmission is immediately cut off when a high level of the CS pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0. The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to 0. Rev.3.00 Jan. 10, 2007 page 507 of 1038 REJ09B0328-0300 Section 24 Serial Communication Interface 2 (SCI2) 24.4 Interrupt Sources An interrupt source of the SCI2 is transmission cutoff by completion of transmission and the CS pin, to which different vector addresses are assigned. On completion of data transfer, TEI of SCSR2 is set to 1, and transfer-end interrupt request is generated. This interrupt can specify enable/disable by setting TEIE of SCR2. While PMR30 of PMR3 is set to 1, transfer is cut off when the CS pin enters a high level during data transfer, and ABT of SCSR2 is set to 1 and then transfer cutoff interrupt request is generated. This interrupt can specify enable/disable by setting ABTIE of SCR2. In the case of transfer cutoff by the CS pin, overrun error, and read/write to serial data buffer during transfer and in the CS standby mode, ABT, ORER, and WT of the SCSR2 is set to 1, respectively. These bits allow to determine error factors. Rev.3.00 Jan. 10, 2007 page 508 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Section 25 I C Bus Interface (IIC) 25.1 2 2 Overview 2 The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) 2 interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however. 2 Each I C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 25.1.1 Features * Selection of addressing format or non-addressing format I C bus format: addressing format with acknowledge bit, for master/slave operation 2 Serial format: non-addressing format without acknowledge bit, for master operation only * Conforms to Philips I C bus interface (I C bus format) 2 2 * Two ways of setting slave address (I C bus format) 2 * Start and stop conditions generated automatically in master mode (I C bus format) 2 * Selection of acknowledge output levels when receiving (I C bus format) 2 * Automatic loading of acknowledge bit when transmitting (I C bus format) 2 * Wait function in master mode (I C bus format) 2 A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function in slave mode (I C bus format) 2 A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. * Three interrupt sources Data transfer end (including transmission mode transition with I C bus format and address reception after loss of master arbitration) 2 Address match: when any slave address matches or the general call address is received in 2 slave receive mode (I C bus format) Stop condition detection * Selection of 16 internal clocks (in master mode) * Direct bus drive (with SCL and SDA pins) Two pins-P24/SCL and P23/SDA- (normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. Rev.3.00 Jan. 10, 2007 page 509 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.1.2 Block Diagram 2 Figure 25.1 shows a block diagram of the I C bus interface. Figure 25.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to input pins depend on the power (Vcc) voltage of this LSI. SCL PS Clock control ICCR Noise canceller ICMR Bus state decision circuit Arbitration decision circuit ICSR ICDRT ICDRS ICDRR SDA Output data control circuit Noise canceler Address comparator SAR, SARX Legend: ICCR : I2C control register ICMR : I2C mode register ICSR : I2C status register ICDR : I2C data register SAR : Slave address register SARX : Slave address register X : Prescaler PS 2 Interrupt generator Figure 25.1 Block Diagram of I C Bus Interface Rev.3.00 Jan. 10, 2007 page 510 of 1038 REJ09B0328-0300 Internal data bus Interrupt request Section 25 I C Bus Interface (IIC) 2 VCC VCC SCLin SCLout SCL SCL SDAin SDAout SDA SDA SCL SDA (Master) This chip SCLin SCLout SCLin SCLout SDAin SDAout (Slave 1) 2 SDAin SDAout (Slave 2) Figure 25.2 I C Bus Interface Connections (Example: This Chip as Master) 25.1.3 Pin Configuration 2 Table 25.1 summarizes the input/output pins used by the I C bus interface. Table 25.1 I C Bus Interface Pins Name Serial clock pin Serial data pin Abbrev. SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output 2 Rev.3.00 Jan. 10, 2007 page 511 of 1038 REJ09B0328-0300 SCL SDA Section 25 I C Bus Interface (IIC) 2 25.1.4 Register Configuration 2 Table 25.2 summarizes the registers of the I C bus interface. Table 25.2 Register Configuration Name I C bus control register I C bus status register I C bus data register I C bus mode register Slave address register Second slave address register Serial/timer control register Module stop control register 2 2 2 2 Abbrev. ICCR ICSR ICDR ICMR SAR SARX STCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'01 H'00 H'00 H'00 H'01 H'00 H'FF H'FF 1 Address* H'D158 H'D159 2 H'D15E* 2 H'D15F* H'D15F* 2 H'D15E* 2 H'FFEE H'FFEC H'FFED Notes: 1. Lower 16 bits of the address. 2 2. The register that can be written or read depends on the ICE bit in the I C bus control 2 register. The slave address register can be accessed when ICE = 0, and the I C bus mode register can be accessed when ICE = 1. Rev.3.00 Jan. 10, 2007 page 512 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.2 25.2.1 Register Descriptions I C Bus Data Register (ICDR) Bit : 7 ICDR7 6 ICDR6 -- R/W 5 ICDR5 -- R/W 4 ICDR4 -- R/W 3 ICDR3 -- R/W 2 ICDR2 -- R/W 1 ICDR1 -- R/W 0 ICDR0 -- R/W 2 Initial value : R/W : -- R/W ICDRR Bit : 7 ICDRR7 Initial value : R/W : -- R 6 ICDRR6 -- R 5 ICDRR5 -- R 4 ICDRR4 -- R 3 ICDRR3 -- R 2 ICDRR2 -- R 1 ICDRR1 -- R 0 ICDRR0 -- R ICDRS Bit : 7 ICDRS7 Initial value : R/W : -- -- 6 ICDRS6 -- -- 5 ICDRS5 -- -- 4 ICDRS4 -- -- 3 ICDRS3 -- -- 2 ICDRS2 -- -- 1 ICDRS1 -- -- 0 ICDRS0 -- -- ICDRT Bit : 7 ICDRT7 Initial value : R/W : -- W 6 ICDRT6 -- W 5 ICDRT5 -- W 4 ICDRT4 -- W 3 ICDRT3 -- W 2 ICDRT2 -- W 1 ICDRT1 -- W 0 ICDRT0 -- W TDRE, RDRF (Internal flag) Bit : -- TDRE Initial value : R/W : 0 -- -- RDRF 0 -- ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and Rev.3.00 Jan. 10, 2007 page 513 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 affect the status of internal flags such as TDRE and RDRF. 2 After transmission/reception of one frame of data using ICDRS, if the I C bus is in transmit mode and the next data is in ICDRT (the TDRE flag is 0), data is transferred automatically from ICDRT 2 to ICDRS. After transmission/reception of one frame of data using ICDRS, if the I C bus is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0), data is transferred automatically from ICDRS to ICDRR. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. TDRE 0 Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] (Initial value) (1) When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) (2) When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected (3) When a stop condition is detected with the I C bus format selected (4) In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) 1 The next transmit data can be written in ICDR (ICDRT) [Setting conditions] (1) In transmit mode (TRS = 1), when a start condition is detected in the bus line 2 state after a start condition is issued in master mode with the I C bus format or serial format selected (2) When data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) (3) When a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1) after detection of a start condition 2 Rev.3.00 Jan. 10, 2007 page 514 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) RDRF 0 Description The data in ICDR (ICDRR) is invalid [Clearing condition] When ICDR (ICDRR) receive data is read in receive mode 1 The ICDR (ICDRR) receive data can be read [Setting condition] When data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) (Initial value) 2 25.2.2 Slave Address Register (SAR) Bit : 7 SVA6 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W Initial value : R/W : 0 R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset. Bits 7 to 1Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0, 2 differing from the addresses of other slave devices connected to the I C bus. Bit 0Format Select (FS): Used together with the FSX bit in SARX to select the communication format. * I C bus format: addressing format with acknowledge bit 2 * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only Rev.3.00 Jan. 10, 2007 page 515 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode. SAR Bit 0 FS 0 SARX Bit 0 FSX 0 1 Operating Mode I C bus format * 2 2 SAR and SARX slave addresses recognized (Initial value) SAR slave address recognized SARX slave address ignored SAR slave address ignored SARX slave address recognized SAR and SARX slave addresses ignored I C bus format * * 1 0 I C bus format * * 2 1 Clock synchronous serial format * 25.2.3 Second Slave Address Register (SARX) Bit : 7 SVAX6 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W Initial value : R/W : 0 R/W SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SARX is initialized to H'01 by a reset and in hardware standby mode. Bits 7 to 1Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to 2 SVAX0, differing from the addresses of other slave devices connected to the I C bus. Rev.3.00 Jan. 10, 2007 page 516 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 0Format Select X (FSX): Used together with the FS bit in SAR to select the communication format. * I C bus format: addressing format with acknowledge bit 2 * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 25.2.4 I C Bus Mode Register (ICMR) Bit : 7 MLS Initial value : R/W : 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W 2 ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'00 by a reset. Bit 7MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. 2 Do not set this bit to 1 when the I C bus format is used. Bit 7 MLS 0 1 Description MSB-first LSB-first (Initial value) Rev.3.00 Jan. 10, 2007 page 517 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 6Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data 2 and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode. Bit 6 WAIT 0 1 Description Data and acknowledge bits transferred consecutively Wait inserted between data and acknowledge bits (Initial value) Rev.3.00 Jan. 10, 2007 page 518 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bits 5 to 3Transfer Clock Select (CKS2 to CKS0): These bits, together with the IICX bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bit 6 IICX 0 Bit 5 CKS2 0 Bit 4 CKS1 0 Bit 3 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 Transfer Rate = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz = 10 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz Rev.3.00 Jan. 10, 2007 page 519 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bits 2 to 0Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be 2 transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge bit. Bit 2 BC2 0 Bit 1 BC1 0 Bit 0 BC0 0 1 1 0 1 1 0 0 1 1 0 1 Bits/Frame Synchronous Serial Format 8 1 2 3 4 5 6 7 I C Bus Format 9 (Initial value) 2 3 4 5 6 7 8 2 Rev.3.00 Jan. 10, 2007 page 520 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 2 25.2.5 I C Bus Control Register (ICCR) Bit : 7 ICE 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 ACKE 0 R/W 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 1 W Initial value : R/W : 0 R/W Note: * Only 0 can be written to clear the flag. ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables 2 acknowledgement, confirms the I C bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. ICCR is initialized to H'01 by a reset. Bit 7I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer 2 operations are enabled. When ICE is cleared to 0, the I C bus interface module is disabled, and the internal state is initialized. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1. Bit 7 ICE 0 Description I C bus interface module disabled, with SCL and SDA signal pins set to port function 2 SAR and SARX can be accessed. The internal state of the I C bus interface module is initialized. (Initial value) I C bus interface module enabled for transfer operations (pins SCL and SDA are driving the bus) ICMR and ICDR can be accessed 2 2 2 2 2 2 2 1 Bit 6I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C bus interface to the CPU. Bit 6 IEIC 0 1 Description Interrupts disabled Interrupts enabled (Initial value) Rev.3.00 Jan. 10, 2007 page 521 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 5Master/Slave Select (MST) Bit 4Transmit/Receive Select (TRS) MST selects whether the I C bus interface operates in master mode or slave mode. 2 TRS selects whether the I C bus interface operates in transmit mode or receive mode. 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first frame after a start condition. Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. MST and TRS select the operating mode as follows. Bit 5 MST 0 Bit 4 TRS 0 1 1 0 1 Description Slave receive mode Slave transmit mode Master receive mode Master transmit mode (Initial value) 2 Bit 5 MST 0 Description Slave mode [Clearing conditions] (1) When 0 is written by software (2) When bus arbitration is lost after transmission is started in I C bus format master mode 1 Master mode [Setting conditions] (1) When 1 is written by software (in cases other than clearing condition 2) (2) When 1 is written in MST after reading MST = 0 (in case of clearing condition 2) 2 (Initial value) Rev.3.00 Jan. 10, 2007 page 522 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Bit 4 TRS 0 Description Receive mode [Clearing conditions] (1) When 0 is written by software (in cases other than setting condition 3) (2) When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3) (3) When bus arbitration is lost after transmission is started in I C bus format master mode 1 Transmit mode [Setting conditions] (1) When 1 is written by software (in cases other than clearing conditions 3) (2) When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3) (3) When a 1 is received as the R/W bit of the first frame in I C bus format slave mode 2 2 2 (Initial value) Bit 3Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the 2 acknowledge bit returned from the receiving device when using the I C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Bit 3 ACKE 0 1 Description The value of the acknowledge bit is ignored, and continuous transfer is performed (Initial value) If the acknowledge bit is 1, continuous transfer is interrupted Rev.3.00 Jan. 10, 2007 page 523 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 2Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. 2 It is not possible to write to BBSY in slave mode; the I C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. Bit 2 BBSY 0 Description Bus is free [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected 2 2 2 (Initial value) Bit 1I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 25.3.6, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. Rev.3.00 Jan. 10, 2007 page 524 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Bit 1 IRIC 0 Description Waiting for transfer, or transfer in progress [Clearing condition] When 0 is written in IRIC after reading IRIC = 1 1 Interrupt requested [Setting conditions] * I C bus format master mode (1) When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) (2) When a wait is inserted between the data and acknowledge bit when WAIT = 1 (3) At the end of data transfer (at the rise of the 9th transmit clock pulse, and at the fall of the 8th transmit/receive clock pulse when a wait is inserted) (4) When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) (5) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) * I C bus format slave mode (1) When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (2) When the general call address is detected (when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (3) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) (4) When a stop condition is detected (when the STOP or ESTP flag is set to 1) * Synchronous serial format (1) At the end of data transfer (when the TDRE or RDRF flag is set to 1) (2) When a start condition is detected with serial format selected When conditions are occured such that the TDRE or RDRF flag is set to 1 2 2 2 2 (Initial value) When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a Rev.3.00 Jan. 10, 2007 page 525 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The IRTR flag (the DTC* start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address 2 match in I C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC*. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 25.3 shows the relationship between the flags and the transfer states. Note: * This LSI does not incorporate DTC. Table 25.3 Flags and Transfer States MST 1/0 1 1 1 1 0 0 0 0 0 TRS 1/0 1 1 1/0 1/0 0 0 0 0 1/0 BBSY ESTP STOP IRTR 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 AASX AL 0 0 0 0 0 1/0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 AAS 0 0 0 0 0 1/0 1 1 0 0 ADZ 0 0 0 0 0 1/0 0 1 0 0 ACKB State 0 0 0 0/1 0/1 0 0 0 0 0/1 Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match Slave mode transmit/receive end (except after SARX match) Slave mode transmit/receive end (after SARX match) Stop condition detected 0 0 0 1/0 1 1/0 1 1 0 0 0 1/0 0 0 1/0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0/1 Rev.3.00 Jan. 10, 2007 page 526 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 0Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. Bit 0 SCP 0 1 Description Writing 0 issues a start or stop condition, in combination with the BBSY flag Reading always returns a value of 1 Writing is ignored (Initial value) 25.2.6 I C Bus Status Register (ICSR) Bit : 7 ESTP 6 STOP 0 5 IRTR 0 4 AASX 0 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 R/(W)* 0 ACKB 0 R/W 2 Initial value : 0 R/W : R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. ICSR is initialized to H'00 by a reset. Bit 7Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been 2 detected during frame transfer in I C bus format slave mode. Bit 7 ESTP 0 Description No error stop condition [Clearing conditions] (1) When 0 is written in ESTP after reading ESTP = 1 (2) When the IRIC flag is cleared to 0 1 * In I C bus format slave mode Error stop condition detected [Setting condition] When a stop condition is detected during frame transfer * In other modes No meaning Rev.3.00 Jan. 10, 2007 page 527 of 1038 REJ09B0328-0300 2 (Initial value) Section 25 I C Bus Interface (IIC) 2 Bit 6Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been 2 detected after completion of frame transfer in I C bus format slave mode. Bit 6 STOP 0 Description No normal stop condition [Clearing conditions] (1) When 0 is written in STOP after reading STOP = 1 (2) When the IRIC flag is cleared to 0 1 * In I C bus format slave mode Error stop condition detected [Setting condition] When a stop condition is detected after completion of frame transfer * In other modes No meaning 2 (Initial value) Rev.3.00 Jan. 10, 2007 page 528 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 5I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag 2 (IRTR): Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC* activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. Note: * This LSI does not incorporate DTC. Bit 5 IRTR 0 Description Waiting for transfer, or transfer in progress [Clearing conditions] (1) When 0 is written in IRTR after reading IRTR = 1 (2) When the IRIC flag is cleared to 0 1 Continuous transfer state [Setting conditions] * * In I C bus interface slave mode When the TDRE or RDRF flag is set to 1 when AASX = 1 In other modes When the TDRE or RDRF flag is set to 1 2 2 (Initial value) Rev.3.00 Jan. 10, 2007 page 529 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 4Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected. Bit 4 AASX 0 Description Second slave address not recognized [Clearing conditions] (1) When 0 is written in AASX after reading AASX = 1 (2) When a start condition is detected (3) In master mode 1 Second slave address recognized [Setting condition] When the second slave address is detected in slave receive mode while FSX = 0 (Initial value) 2 Bit 3Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The 2 I C bus interface monitors the bus. When two or more master devices attempt to seize the bus at 2 nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL 0 Description Bus arbitration won [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] (1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode (2) If the internal SCL line is high at the fall of SCL in master transmit mode (Initial value) Rev.3.00 Jan. 10, 2007 page 530 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 2Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 2 AAS 0 Description Slave address or general call address not recognized [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AAS after reading AAS = 1 (3) In master mode 1 Slave address or general call address recognized [Setting condition] When the slave address or general call address is detected in slave receive mode 2 2 (Initial value) Bit 1General Call Address Recognition Flag (ADZ): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ 0 Description General call address not recognized [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in ADZ after reading ADZ = 1 (3) In master mode 1 General call address recognized [Setting condition] If the general call address is detected when FSX = 0 or FS = 0 is selected in the slave receive mode. (Initial value) Rev.3.00 Jan. 10, 2007 page 531 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 0Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal software is read. Bit 0 ACKB 0 Description Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: Indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowledged the data (signal is 1) 25.2.7 Serial/Timer Control Register (STCR) Bit : 7 -- 6 IICX 0 R/W 5 IICRST 0 R/W 4 -- 0 -- 3 FLSHE 0 R/W 2 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Initial value : R/W : 0 -- STCR is an 8-bit readable/writable register that controls the I C bus interface operating mode. STCR is initialized to H'00 by a reset. Bit 7Reserved Bit 6I C Transfer Select (IICX): This bit, together with bits CKS2 to CKS0 in ICMR of I C, 2 selects the transfer rate in master mode. For details, see section 25.2.4, I C Bus Mode Register (ICMR). 2 2 Rev.3.00 Jan. 10, 2007 page 532 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Bit 5I C Controller Reset (IICRST): This bit controls the initialization of the internal state of 2 2 the I C bus interface. When the I C bus interface operating mode is hung because of 2 communications error, and the IICRST bit is then set to 1, the I C bus interface controller is 2 initialized of the internal state, and this allows the internal state of the I C bus interface to be initialized without making port settings or initializing registers. For the detail, refer to section 25.3.9, Initialization of Internal State. 2 The initialization is continuous and the I C bus interface cannot operate, when the IICST bit remains set to 1. Therefore, be sure to clear the IICRST bit after setting it. Bit 5 IICRST 0 1 Description I C bus interface controller is not reset I C bus interface controller is reset 2 2 2 (Initial value) Bits 3Flash Memory Control Resister Enable (FLSHE): This bit selects the control resister of the flash memory. For details, refer to section 7.3.4 or 8.3.5, Serial/Timer Control Resister (STCR). Bits 4 and 2 to 0Reserved 25.2.8 Module Stop Control Register (MSTPCR) MSTPCRH Bit : Initial value : R/W : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. 2 When the corresponding bit in MSTPCR is set to 1, operation of the corresponding I C module is halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset. It is not initialized in standby mode. Rev.3.00 Jan. 10, 2007 page 533 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 MSTPCRL Bit 6Module Stop (MSTP6): Specifies I C module stop mode. MSTPCRL Bit 6 MSTP6 0 1 Description I C module stop mode is cleared I C module stop mode is set 2 2 2 (Initial value) Rev.3.00 Jan. 10, 2007 page 534 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.3 25.3.1 2 Operation I C Bus Data Format 2 2 The I C bus interface has serial and I C bus formats. 2 The I C bus formats are addressing formats with an acknowledge bit. These are shown in figure 25.3. The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 25.4. 2 Figure 25.5 shows the I C bus timing. The symbols used in figures 25.3 to 25.5 are explained in table 25.4. (a) FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 W m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = 1 or above) (b) Start condition transmission, FS = 0 or FSX = 0 S 1 SLA 7 R/W 1 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 R/W 1 1 A 1 DATA n2 m2 A/A 1 P 1 Upper: Transfer bit count (n1 and n2 = 1 to 8) Lower: Transfer frame count (m1 and m2 = 1 or above) Figure 25.3 I C Bus Data Formats (I C Bus Formats) FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = 1 or above) 2 2 Figure 25.4 I C Bus Data Format (Serial Format) 2 Rev.3.00 Jan. 10, 2007 page 535 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 2 8 9 A 1-7 DATA 8 9 A/A P Figure 25.5 I C Bus Timing Table 25.4 I C Bus Data Format Symbols S SLA R/W A DATA P Start condition. The master device drives SDA from high to low while SCL is hig Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR Stop condition. The master device drives SDA from low to high while SCL is high 2 25.3.2 2 Master Transmit Operation In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations synchronize with the ICDR writing are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS, WAIT, CKS2 to CKS0 in ICMR, and bit IICX in STCR, according to the operating mode. [2] Read the BBSY flag in ICCR to confirm that the bus is free. [3] Set bits MST and TRS to 1 in ICCR to select master transmit mode. [4] Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and generates the start condition. [5] Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. [6] Write the data (slave address + R/W) to ICDR. After the start condition instruction has been issued and the start conditon has been generated, write data to ICDR. If this procedure is not 2 followed, data may not be output correctly. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7bit slave address and transmit/receive direction. As indicating the end of the transfer, and so Rev.3.00 Jan. 10, 2007 page 536 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 the IRIC flag is cleared to 0. After writing ICDR, clear IRIC immediately not to execute other interrupt handling routine. If one frame of data has been transmitted before the IRIC clearing, it can not be determine the end of transmission. The master device sequentially sends the transmission clock and the data written to ICDR using the timing shown in figure 25.6. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. [7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [8] Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the transmit operation. [9] Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC immediately not to execute other interrupt handling routine. The master device sequentially sends the transmission clock and the data written to ICDR. Transmission of the next frame is performed in synchronization with the internal clock. [10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [11] Read the ACKB bit in ICSR and confirm ACKB is cleared to 0. When there is data to be transmitted, go to the step [9] to continue next transmission. When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to end transmission. [12] Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev.3.00 Jan. 10, 2007 page 537 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Start condition Geberation SCL (master output) SDA (master output) SDA (slave output) IRIC IRTR ICDR Note: Data write timing in ICDR ICDR Writing prohibited [5] 1 bit 7 2 bit 6 3 bit 5 4 bit 4 5 bit 3 6 bit 2 7 bit 1 8 bit 0 R/W [7] A 9 1 bit 7 2 bit 6 2 Slave address Data 1 address + R/W Data 1 ICDR Writing enable User processing [4] Write BBSY = 1 and SCP = 0 (start condition issuance) [6] ICDR write [6] IRIC clear [9] ICDR write [9] IRIC clear These processes are executed continuously. These processes are executed continuously. Figure 25.6 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) Rev.3.00 Jan. 10, 2007 page 538 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an 2 acknowledge signal. The slave device transmits data. I C bus interface module consists of the data buffers of ICDRR and ICDRS, so data can be received continuously in master receive mode. For this construction, when stop condition issuing timing delayed, it may occurs the internal contention between stop condition issuance and SCL clock output for next data receiving, and then the extra SCL clock would be outputted automatically or the SCL line would be held to low. And 2 for I C bus interface system, the acknowledge bit must be set to 1 at the last data receiving, so the change timing of ACKB bit in ICSR should be controlled by software. To take measures against these problems, the wait function should be used in master receive mode. The reception procedure and operations with the wait function in master receive mode are described below. [1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the WAIT bit in ICMR to 1. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting). [2] When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. In order to detect wait operation, set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC immediately not to execute other interrupt handling routine. If one frame of data has been received before the IRIC clearing, it can not be determine the end of reception. [3] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. If the first frame is the last receive data, execute step [10] to halt reception. [4] Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock and drives SDA at the 9th receive clock pulse to return an acknowledge signal. [5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to receive next data. [6] Read ICDR. [7] Clear the IRIC flag to detect next wait operation. From clearing of the IRIC flag to negation of a wait as described in step [4] (and [9]) to clearing of the IRIC flag as described in steps [5], [6], and [7], must be performed within the time taken to transfer one byte. [8] The IRIC flags set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. If this frame is the last receive data, execute step [10] to halt reception. [9] Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock and drives SDA at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [5] to [9]. Rev.3.00 Jan. 10, 2007 page 539 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 [10] Set the ACKB bit in ICSR to 1 so as to return "No acknowledge" data. Also set the TRS bit to 1 to switch from receive mode to transmit mode. [11] Clear IRIC flag to 0 to release from the Wait State. [12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th receive clock pulse. [13] Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the IRIC flag to 0. Clearing of the IRIC flag should be after the WAIT = 0. (If the stop-condition generation command is executed after clearing the IRIC flag to 0 and then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be generated.) [14] Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high, and generates the stop condition. Master transmit mode Master receive mode SCL (master output) SDA (slave output) 9 A 1 Bit7 2 Bit6 3 Bit5 4 Bit4 5 Bit3 6 Bit2 7 Bit1 8 Bit0 [3] A 9 1 Bit7 2 Bit6 3 Bit5 4 Bit4 5 Bit3 Data 1 SDA (master output) IRIC IRTR ICDR [5] Data 2 Data 1 User processing [2] IRIC clearance [1] TRS cleared to 0 [2] ICDR read (dummy read) WAIT set to 1 ACKB cleared to 0 [4] IRIC clearance [6] ICDR read (Data 1) [7] IRIC clearance These processes are executed continuously. These processes are executed continuously. Figure 25.7 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) Rev.3.00 Jan. 10, 2007 page 540 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 SCL (master output) 8 9 1 Bit7 2 Bit6 3 Bit5 4 Bit4 5 Bit3 6 Bit2 7 Bit1 8 Bit0 [8] A 9 1 Bit7 2 Bit6 Data 4 SDA Bit0 (slave output) Data 2 SDA (master output) IRIC IRTR ICDR [8] A [5] Data 3 [5] Data 1 Data 2 Data 3 User processing [9] IRIC clearance [6] ICDR read (Data 2) [7] IRIC clearance [9] IRIC Clearance [6] ICDR read (Data 3) [7] IRIC clearance These processes are executed continuously. These processes are executed continuously. Figure 25.8 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) Continued 25.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The receive procedure and operations in slave receive mode are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode. [2] A start condition output by the master device sets the BBSY flag to 1 in ICCR. [3] After the slave device detects the start condition, if the first frame matches its slave address, it functions as the slave device designated as the master device. If the 8th bit data (R/W) is 0, TRS bit in ICCR remains 0 and executes slave receive operation. [4] At the ninth clock pulse of the receive frame, the slave device drives SDA low to acknowledge the transfer. At the same time, the IRIC flag is set to 1 in ICCR. If IEIC is 1 in ICCR, a CPU interrupt is requested. If the RDRF internal flag is 0, it is set to 1 and continuous reception is performed. If the RDRF internal flag is 1, the slave device holds SCL low from the fall of the receive clock until it has read the data in ICDR. [5] Read ICDR and clear IRIC to 0 in ICCR. At this time, the RDFR flag is cleared to 0. Steps [4] and [5] can be repeated to receive data continuously. When a stop condition is detected (a low-to-high transition of SDA while SCL is high), the BBSY flag is cleared to 0 in ICCR. Rev.3.00 Jan. 10, 2007 page 541 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Start condition issurance SCL (Master output) SCL (Slave output) SDA (Master output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 2 1 2 3 4 5 6 7 8 9 1 2 Slave address R/W [4] A Data 1 RDRF IRIC Interrupt request generated ICDRS Address + R/W ICDRR Address + R/W User processing [5] Read ICDR [5] Clear IRIC Figure 25.9 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (1) Rev.3.00 Jan. 10, 2007 page 542 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) SCL (Master output) SCL (Slave output) SDA (Master output) 2 7 8 9 1 2 3 4 5 6 7 8 9 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 SDA (Slave output) [4] Data 2 [4] A A RDRF IRIC Interrupt request generated Data 1 Interrupt request generated Data 2 ICDRS ICDRR Data 1 Data 2 User processing [5] Read ICDR [5] Clear IRIC Figure 25.10 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (2) Rev.3.00 Jan. 10, 2007 page 543 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave transmit mode are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode. [2] After the slave device detects a start condition, if the first frame matches its slave address, at the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same time, the IRIC flag is set to 1 in ICCR, and if the IEIC bit in ICCR is set to 1 at this time, an interrupt request is sent to the CPU. If the eighth data bit (R/W) is 1, the TRS bit is set to 1 in ICCR, automatically causing a transition to slave transmit mode. The slave device holds SCL low from the fall of the transmit clock until data is written in ICDR. [3] Clear the IRIC flag to 0, then write data in ICDR. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0, then write the next data in ICDR. The slave device outputs the written data serially in step with the clock output by the master device, with the timing shown in figure 25.11. [4] When one frame of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC is set to 1 in ICCR. If the TDRE internal flag is 1, the slave device holds SCL low from the fall of the transmit clock until data is written in ICDR. The master device drives SDA low at the ninth clock pulse to acknowledge the data. The acknowledge signal is stored in the ACKB bit in ICSR, and can be used to check whether the transfer was carried out normally. If TDRE internal flag is set to 0, the data written in ICDR is transferred to ICDRS, then transmission starts and TDRE internal flag and IRIC and IRTR flags are all set to 1 again. [5] To continue transmitting, clear IRIC to 0, then write the next transmit data in ICDR. Steps [4] and [5] can be repeated to transmit continuously. To end the transmission, write H'FF in ICDR so that the SDA may be freed on the slave side. When a stop condition is detected (a low-tohigh transition of SDA while SCL is high), the BBSY flag will be cleared to 0 in ICCR. Rev.3.00 Jan. 10, 2007 page 544 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Slave receive mode SCL (Master output) SCL (Slave output) Slave transmit mode 2 8 9 1 2 3 4 5 6 7 8 9 1 2 SDA (Slave output) SDA (Master output) R/W A [2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Data 1 A Data 2 TDRE [3] Interrupt request generated Data 2 IRIC Interrupt request generated Interrupt request generated Data 1 ICDRT ICDRS Data 1 Data 2 User processing [3] Clear IRIC [3] Write ICDR [3] Write ICDR [5] Clear IRIC [5] Write ICDR Figure 25.11 Example of Timing in Slave Transmit Mode (MLS = 0) 25.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 25.12 shows the IRIC set timing and SCL control. Rev.3.00 Jan. 10, 2007 page 545 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 2 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA 8 A 1 IRIC User processing Clear IRIC Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 25.12 IRIC Setting Timing and SCL Control Rev.3.00 Jan. 10, 2007 page 546 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.3.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 25.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock SCL or SDA input signal C D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 25.13 Block Diagram of Noise Canceler 25.3.8 Sample Flowcharts 2 Figures 25.14 to 25.17 show sample flowcharts for using the I C bus interface in each mode. Rev.3.00 Jan. 10, 2007 page 547 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Start Initialize Read BBSY in ICCR No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Write BBSY = 1 and SCP = 0 in ICCR [3] Select master transmit mode. [1] Initialize [2] Test the status of the SCL and SDA lines. [4] Start condition issuance Read IRIC in ICCR No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No No No [5] Wait for a start condition generation [6] Set transmit data for the first byte (slave address + R/W). (After writing ICDR, clear IRIC immediately) [7] Wait for 1 byte to be transmitted. [8] Test the acknowledge bit, transferred from slave device. Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing ICDR, clear IRIC immediately) [10] Wait for 1 byte to be transmitted. IRIC = 1? Yes Read ACKB in ICSR [11] Test for end of transfer No End of transmission or ACKB = 1? Yes Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance Figure 25.14 Flowchart for Master Transmit Mode (Example) Rev.3.00 Jan. 10, 2007 page 548 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Master receive mode Set TRS = 0 in ICCR Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Last receive ? No Clear IRIC in ICCR [4] Clear IRIC to trigger the 9th clock. (to end the wait insertion) [5] Wait for 1 byte to be received. (9th clock risig edge) Yes [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. [1] Select receive mode [3] Wait for 1 byte to be received. (8th clock falling edge) Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR [6] Read the received data. [7] Clear IRIC Read IRIC in ICCR No IRIC = 1? Yes Yes Last receive ? No Read IRIC in ICCR [8] Wait for the next data to be received. (8th clock falling edge) [9] Clear IRIC to trigger the 9th clock. (to end the wait insertion) Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC in ICCR Read IRIC in ICCR No [10] Set ACKB = 1 so as to return No acknowledge, or set TRS = 1 so as not to issue Extra clock. [11] Clear IRIC to trigger the 9th clock. (to end the wait insertion) [12] Wait for 1 byte to be received. IRIC = 1? Yes Set WAIT = 0 in ICMR Read ICDR Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR End [14] Stop condition issuance. [13] Set WAIT = 0. Read ICDR. Clear IRIC. (Note: After setting WAIT = 0, IRIC should be cleared to 0) Figure 25.15 Flowchart for Master Receive Mode (Example) Rev.3.00 Jan. 10, 2007 page 549 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC flag in ICCR No IRIC = 1? Yes Read AAS and ADZ flags in ICSR AAS = 1 and ADZ = 0? Yes Read TRS bit in ICCR TRS = 0? Yes Last receive? No Read ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No [4] IRIC = 1? Yes [3] Start receiving. The first read is a dummy read. Set ACKB = 0 in ICSR Read ICDR Clear IRIC flag in ICCR [6] Start the last receive. Read IRIC flag in ICCR No [7] IRIC = 1? Yes Read ICDR Clear IRIC flag in ICCR End [8] [7] Wait for the transfer to end. [8] Read the last receive data. [5] [6] [5] Set acknowledge data for the last receive. [4] Wait for the transfer to end. [2] Wait for 1 byte to be received (slave address) Yes No Slave transmit mode No General call address processing *Description omitted [2] [1] [3] [1] Select slave receive mode. Figure 25.16 Flowchart for Slave Transmit Mode (Example) Rev.3.00 Jan. 10, 2007 page 550 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No [1] [3] Test for end of transfer. [4] Select slave receive mode. [5] Dummy read (to release the SCL line). [2] IRIC = 1? Yes Read ACKB bit in ICSR No End of transmission (ACKB = 1)? [3] Yes Set TRS = 0 in ICCR Read ICDR Clear IRIC flag in ICCR End [4] [5] Figure 25.17 Flowchart for Slave Receive Mode (Example) Rev.3.00 Jan. 10, 2007 page 551 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.3.9 2 Initialization of Internal State 2 This I C is capable of forcibly initializing internal state of I C if deadlock develops during communication. The initialization is done by setting IICRST bit in STCR register, or clearing ICE bit. For details, see section 25.2.7, Serial/Time control Register (STCR). (1) Range of Initialization The following is initialized by this function: * Internal flags of TDRE and RDRF * Programmable logic controller for signal receiving and sending. * Internal latches used for holding outputs from SCL and SDA pins (wait, clock, data output, etc.). The following is not initialized by this function: * Register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, and STCR). * Internal latches employed for maintaining data read from the registers which is used for setting or clearing flags on ICMR, ICCR, and ICSR registers. * Values on the ICMR register bit counters (BC2 to BC0). * Interrupt factors currently generated (interrupt factors transferred to the interrupt controller). (2) Precautions on Initialization * Interrupt flags and interrupt factors are not cleared by this function. Thus, you need to clear them own as needed. * Other register flags are not basically cleared, too. Thus, you need to clear them as needed. * When this I C is initialized with IICRST bit, write data specified by IICRST bit is maintained. 2 2 When clearing I C, set IICRST bit once, then clear it using the MOV instruction. The I C cannot operate with the IICRST bit set to 1. Don't try to use bit operation instructions such as BCLR. 2 * If you try to clear a flag while data sending or receiving is taking place, I C module stops sending or receiving at that moment and frees the SCL and SDA pins. When resuming the communication, initialize registers as needed so that the system communication capability may function as intended. 2 Rev.3.00 Jan. 10, 2007 page 552 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Clear function of this module does not directly rewrite value of BBSY bit. However, depending on state of SCL and SDA pins and the timing in which they are made free, BBSY bit can be cleared. Other bits and flags can also be affected by status change. In order to avoid these troubles, the following procedures must be observed in initialization of I C. (1) Implement initialization of internal state by setting IICRST bit or ICE bit. (2) Execute the stop condition issue instruction (setting BBSY = 0 and SCP = 0 to write) and wait for a duration equivalent to 2 clocks of the transfer rate. (3) Execute initialization of internal state again by setting IICRST bit or ICE bit. (4) Initialize each I C register (re-setting). 2 2 Rev.3.00 Jan. 10, 2007 page 553 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 25.4 Usage Notes (1) In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that the SCL may briefly remain at a high level immediately after BBSY is cleared to 0. (2) Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. (a) Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) (b) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) (3) Table 25.5 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 25.5 I C Bus Timing (SCL and SDA Output) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO 6 tcyc when IICX is 0, 12 tcyc when 1. Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28 tcyc to 256 tcyc 0.5 tSCLO 0.5 tSCLO 0.5 tSCLO -1 tcyc 0.5 tSCLO -1 tcyc 1 tSCLO 0.5 tSCLO +2 tcyc 1 tSCLLO -3 tcyc 1 tSCLL -(6 tcyc or 12 tcyc*) 3 tcyc Unit ns ns ns ns ns ns ns ns ns ns Notes Figure 29.10 (reference) 2 (4) SCL and SDA input is sampled in synchronization with the internal clock. The AC timing 2 therefore depends on the system clock cycle tcyc, as shown in table 29.6. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. Rev.3.00 Jan. 10, 2007 page 554 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 (5) The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high2 speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds 2 the time determined by the input clock of the I C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 25.6. Table 25.6 Permissible SCL Rise Time (tsr) Values Time Indication [ns] IICX 0 tcyc Indication 7.5 tcyc High-speed mode 1 17.5 tcyc I C Bus Specification (Max.) = 5 MHz = 8 MHz = 10 MHz Normal mode 1000 300 937 750 2 2 Normal mode 1000 High-speed mode 300 (6) The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns 2 and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, as 2 shown in table 25.5. However, because of the rise and fall times, the I C bus interface specifications may not be satisfied at the maximum transfer rate. Table 25.7 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. 2 tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing 2 permits this output timing for use as slave devices connected to the I C bus. 2 tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input 2 timing permits this output timing for use as slave devices connected to the I C bus. 2 Rev.3.00 Jan. 10, 2007 page 555 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Table 25.7 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) Normal mode -1000 High-speed mode High-speed mode High-speed mode High-speed mode High-speed mode High-speed mode High-speed mode High-speed mode High-speed mode 2 2 Item tSCLHO tcyc Indication 0.5 tSCLO (-tSr) 0.5 tSCLO (-tSf) 0.5 tSCLO -1 tcyc (-tSr) 0.5 tSCLO -1 tcyc (-tSf) 1 tSCLO (-tSr) 0.5 tSCLO +2 tcyc (-tSr) I2C Bus Specification (Min.) = 5 MHz 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 0 0 4000 950 4750 1000*1 3800*1 750*1 4550 800 9000 2200 4400 1350 3100 400 1300 -1400*1 600 = 8 MHz 3875*1 825*1 4625 875 9000 2200 4250 1200 3325 625 2200 -500*1 375 = 10 MHz 3900*1 850*1 4650 900 9000 2200 4200 1150 3400 700 2500 -200*1 300 -300 tSCLLO Normal mode -250 -250 tBUFO Normal mode -1000 -300 tSTAHO Normal mode -250 -250 tSTASO Normal mode -1000 -300 tSTOSO Normal mode -1000 -300 tSDASO 1 tSCLLO*3 -3 tcyc (master) (-tSr) tSDASO (slave) tSDAHO 1 tSCLL*3 -12 tcyc*2 (-tSr) 3 tcyc Normal mode -1000 -300 Normal mode -1000 -300 Normal mode 0 0 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS2 to CKS0. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6 tcyc). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). Rev.3.00 Jan. 10, 2007 page 556 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 (7) Precautions on reading ICDR at the end of master receive mode When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high level, thereby generating the stop condition. Now you can read received data from ICDR. If, however, any data is remaining on the buffer, received data on ICDRS is not transferred to ICDR, thus you won't be able to read the second byte data. When it is required to read the second byte data, issue the stop condition from the master receive state (TRS bit is 0). Before reading data from ICDR register, make sure that BBSY bit on ICCR register is 0, stop condition is generated and bus is made free. If you try to read received data after the stop condition issue instruction (setting ICCR's BBSY = 0 and SCP = 0 to write) has been executed but before the actual stop condition is generated, clock may not be appropriately signaled when the next master sending mode is turned on. Thus, reasonable care is needed for determining when to read the received data. After the master receive is complete, if you want to re-write I C control bit (such as clearing MST bit) for switching the sending/receiving mode or modifying settings, it must be done during period (a) indicated in figure 25.18 (after making sure ICCR register BBSY bit is cleared to 0). Stop condition (a) SDA SCL Internal clock BBSY bit Master receive mode ICDR read inhibit period Bit 0 8 A 9 Start condition 2 The stop condition issue instruction (BBSY = 0 and SCP = 0 set to write) is executed Generation of the stop condition is checked (BBSY = 0 is set to read) Start condition is issued Figure 25.18 Precautions on Reading the Master Receive Data Rev.3.00 Jan. 10, 2007 page 557 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 (8) Notes on start condition issuance for retransmission Figure 25.19 shows the timing of start conditon issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. After start condition issuance is done and determined the start condition, write the transmit data to ICDR. [1] Wait for end of 1-byte transfer IRIC = 1 ? Yes Clear IRIC in ICSR Start condition issuance? Yes Read SCL pin No [2] No No [1] [2] Determine wheter SCL is low [3] Issue restart condition instruction for transmission Other processing [4] Determine whether start condition is generated or not [5] Set transmit data (slave address + R/W) SCL = Low ? Yes Write BBSY = 1, SCP = 0 (ICSR) Note: Program so that processing instruction [3] to [5] is executed continuously. [3] [4] IRIC = 1 ? Yes Write transmit data to ICDR [5] No Start condition (retransmission) SCL 9 SDA ACK bit 7 IRIC [5] ICDR write (next transmit data) [4] IRIC determination [3] Issue restart condition instruction for retransmission [2] Determination of SCL = Low [1] IRIC determination Figure 25.19 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission Rev.3.00 Jan. 10, 2007 page 558 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 (9) Notes on I C bus interface stop condition instruction issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below. 9th clock SCL VIH As waveform rise is late, SCL is detected as low SDA Stop condition IRIC [2] Stop condition instruction issuance [1] Determination of SCL = Low High period secured 2 Figure 25.20 Timing of Stop Condition Issuance (10) Notes on WAIT Function (a) Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall. (1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode (2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock. (b) Error phenomenon Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the 7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally. Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall. (c) Restrictions Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2 through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th clock. If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC counter is turned to 1 or 0, please confirm the SCL pins are in L' state after the counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 25.21.) Rev.3.00 Jan. 10, 2007 page 559 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Transmit/receive data 9 1 7 2 6 3 5 When BC2-0 2 IRIC clear 2 ASD SCL BC2-BC0 IRIC (operation example) A 9 0 1 7 2 6 Transmit/receive data A 7 2 1 8 SCL = `L' confirm 0 IRIC clear 3 5 4 4 5 3 6 IRIC flag clear available IRIC flag clear available IRIC flag clear unavailable Figure 25.21 IRIC Flag Clear Timing on WAIT Operation (11) Notes on ICDR Reads and ICCR Access in Slave Transmit Mode In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 25.22. Normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem with reading the ICDR register or reading or writing to the ICCR register. To ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. (1) Make sure that reading received data from the ICDR register, or reading or writing to the ICCR register, is completed before the next slave address receive operation starts. (2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the ICDR register, or reading or writing to the ICCR register. 2 Rev.3.00 Jan. 10, 2007 page 560 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Waveforms if problem occurs SDA SCL TRS R/W 8 Address received Period when ICDR reads and ICCR reads and writes are prohibited (6 system clock cycles) A 9 Data transmission ICDR write Bit 7 2 Detection of 9th clock cycle rising edge Figure 25.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode (12) Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 25.23) 2 in the slave mode of the I C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. However, at other times (indicated as (b) in figure 25.23) the value set in the TRS bit is put on hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than taking effect immediately. This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an address receive operation following a restart condition input with no stop condition intervening. When receiving an address in the slave mode, clear the TRS bit to 0 during the period indicated as (a) in figure 25.23. To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS bit to 0 and then perform a dummy read of the ICDR register. Rev.3.00 Jan. 10, 2007 page 561 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) Resumption condition 2 (a) SDA SCL (a) TRS bit (b) TRS bit 8 9 (b) A 1 2 3 4 5 6 7 8 9 Data transmission Address reception Period in which TRS bit setting is retained TRS bit effective value TRS bit setting value Detection of rise of 9th transmit/receive clock Detection of rise of 9th transmit/receive clock Figure 25.23 TRS Bit Setting Timing in Slave Mode (13) Notes on Arbitration Lost in Master Mode The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX 2 register, the I C bus interface erroneously recognizes that the address call has occurred. (See figure 25.24.) In multi-master mode, a bus conflict could happen. When The I C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. 2 2 Rev.3.00 Jan. 10, 2007 page 562 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) * Arbitration is lost * The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data does not match DATA2 A DATA3 A 2 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Data contention I2C bus interface (Slave receive mode) S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device Figure 25.24 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. (14) Notes on Interrupt Occurrence after ACKB Reception Conditions to cause this failure The IRIC flag is set to 1 when both of the following conditions are satisfied. * 1 is received as the acknowledge bit for transmit data and the ACKB bit in ICSR is set to 1 * Rising edge of the 9th transmit/receive clock is input to the SCL pin When the above two conditions are satisfied in slave receive mode, an unnecessary interrupt occurs. Figure 25.25 shows the note on interrupt occurrence in slave mode after receiving 1 as the acknowledge bit (ACKB = 1). 2 Rev.3.00 Jan. 10, 2007 page 563 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 (1) For the last transmit data in master transmit mode or slave transmit mode, 1 is received as the acknowledge bit. If the ACKE bit in ICCR is set to 1 at this time, the ACKB bit in ICSR is set to 1. (2) After switching to slave receive mode, the start condition is input, and address reception is performed next. (3) Even if the received address does not match the address set in SAR or SARX, the IRIC flag is set to 1 at the rise of the 9th transmit/receive clock, thus causing an interrupt to occur. Note that if the slave address matches, an interrupt is to be generated at the rise of the 9th transmit/receive clock as normal operation, so this is not erroneous operation. Restriction In a transmit operation of the I C bus interface module, carry out the following countermeasures. (1) After 1 is received as the acknowledge bit for transmit data, clear the ACKE bit in ICCR to 0 to clear the ACKB bit to 0. (2) To enable acknowledge bit reception afterwards, set the ACKE bit to 1 again. Slave reception mode 2 Master transmit mode or slave transmit mode Stop condition Start condition (2) Address that does not match is received. SDA N Address A Data SCL 8 9 1 2 3 4 5 6 7 8 9 1 2 ACKB bit IRIC flag Countermeasure: Clear the ACKE bit to 0 to clear the ACKB bit. (3) Unnecessary interrupt occurs (received address is invalid). Stop condition detection (1) Acknowledge bit is received and the ACKB bit is set to 1. Figure 25.25 Note on Interrupt Occurrence in Slave Mode after ACKB = 1 Reception Rev.3.00 Jan. 10, 2007 page 564 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 (15) Notes on TRS Bit Setting and ICDR Register Access Conditions to cause this failure Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are satisfied. Master mode Figure 25.26 shows the notes on ICDR reading (TRS = 1) in master mode. (1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full). (2) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state) (3) Sets to receive mode (TRS = 0), after transmitting Rev.1 frame of issued start condition by master mode. Slave mode Figure 25.27 shows the notes on ICDR writing (TRS = 0) in slave mode. (1) Writes ICDR register in receive mode (TRS = 0), after entering the start condition by slave mode (TDRE = 0 state). Address match with Rev.1 frame, receive 1 by R/W bit, and switches to transmit mode (TRS = 1). When these conditions are satisfied, the low fixation of the SCL pins is cancelled without ICDR register access after Rev.1 frame is transferred. Restriction Please carry out the following countermeasures when transmitting/receiving via the IIC bus interface module. (1) Please read the ICDR registers in receive mode, and write them in transmit mode. (2) In receiving operation with master mode, please issue the start condition after clearing the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the DDCSWR register on bus-free state (BBSY = 0). Rev.3.00 Jan. 10, 2007 page 565 of 1038 REJ09B0328-0300 Section 25 I C Bus Interface (IIC) 2 Along with ICDRS: ICDRR transfer Stop condition Start condition Cancel condition of SCL = Low fixation is set. SDA SCL TRS bit RDRF bit ICDRS data full A 8 9 1 2 3 Address 4 5 6 7 8 A 9 Data 1 2 3 (3) TRS = 0 (2) RDRF = 0 (1) ICDRS data full ICDR read Detection of 9th clock rise (TRS = 1) TRS = 0 setting Figure 25.26 Notes on ICDR Reading with TRS = 1 Setting in Master Mode Along with ICDRS: ICDRR transfer Stop condition Start condition Cancel condition of SCL = Low fixation SDA SCL TRS bit TDRE bit 8 A 9 1 2 3 Address 4 5 6 7 8 A 9 1 2 Data 3 4 (2) TRS = 1 (1) TDRE = 0 ICDR write TRS = 0 setting Automatic TRS = 1 setting by receiving R/W = 1 Figure 25.27 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode Rev.3.00 Jan. 10, 2007 page 566 of 1038 REJ09B0328-0300 Section 26 A/D Converter Section 26 A/D Converter 26.1 Overview This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12 analog input channels to be selected. 26.1.1 Features A/D converter features are listed below. * 10-bit resolution * 12 input channels * Sample and hold function * Choice of software, hardware (internal signal) triggering, or external triggering for A/D conversion start. * A/D conversion end interrupt request generation Rev.3.00 Jan. 10, 2007 page 567 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.1.2 Block Diagram Figure 26.1 shows a block diagram of the A/D converter. Internal data bus Reference Voltage AVCC Successive approximation register A D R A H R 10-bit D/A A D C S R A D C R AVSS Hardware control circuit A D T S R AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB ADTRG (HSW timing generator) Vref Analog multiplexer + Chopper type comparator Control circuit DFG ADTRG Sample-andhold circuit /2 /4 Interrupt request Legend: ADR : Software trigger A/D result register AHR : Hardware trigger A/D result register ADCR : A/D control register ADCSR : A/D control/status register ADTSR : A/D trigger selection register ADTRG, DFG : Hardware trigger ADTRG : A/D external trigger input Figure 26.1 Block Diagram of A/D Converter Rev.3.00 Jan. 10, 2007 page 568 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.1.3 Pin Configuration Table 26.1 summarizes the input pins used by the A/D converter. Table 26.1 A/D Converter Pins Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin A Analog input pin B A/D external trigger input pin Abbrev. AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply Analog block ground and A/D conversion reference voltage Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 Analog input channel 8 Analog input channel 9 Analog input channel A Analog input channel B External trigger input for starting A/D conversion Rev.3.00 Jan. 10, 2007 page 569 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.1.4 Register Configuration Table 26.2 summarizes the registers of the A/D converter. Table 26.2 A/D Converter Registers Name Abbrev. R/W R R R R R/W 1 R (W)* Size Byte Byte Byte Byte Byte Byte Byte Byte Initial Value Address* H'00 H'00 H'00 H'00 H'40 H'01 H'FC H'00 H'D130 H'D131 H'D132 H'D133 H'D134 H'D135 H'D136 H'FFCD 2 Software trigger A/D result ADRH register H Software trigger A/D result ADRL register L Hardware trigger A/D result AHRH register H Hardware trigger A/D result AHRL register L A/D control register A/D control/status register A/D trigger selection register Port mode register 0 ADCR ADCSR ADTSR PMR0 R/W R/W Notes: 1. Only 0 can be written in bits 7 and 6, to clear the flag. Bits 3 to 1 are read-only. 2. Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 570 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.2 26.2.1 Register Descriptions Software-Triggered A/D Result Register (ADR) ADRH Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 -- 0 -- ADRL 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value : R/W : The software-triggered A/D result register (ADR) is a register that stores the result of an A/D conversion started by software. The A/D-converted data is 10-bit data. Upon completion of software-triggered A/D conversion, the 10-bit result data is transferred to ADR and the data is retained until the next softwaretriggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes (bits 15 to 8) of ADR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0 are always read as 0. ADR can be read by the CPU at any time, but the ADR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 26.3, Interface to Bus Master. ADR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. 26.2.2 Hardware-Triggered A/D Result Register (AHR) AHRH Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 -- 0 -- AHRL 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0 Initial value : R/W : The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D conversion started by hardware (internal signal: ADTRG and DFG) or by external trigger input (ADTRG). The A/D-converted data is 10-bit data. Upon completion of hardware- or external-triggered A/D conversion, the 10-bit result data is transferred to AHR and the data is retained until the next hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes (bits 15 to 8) of AHR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0 are always read as 0. Rev.3.00 Jan. 10, 2007 page 571 of 1038 REJ09B0328-0300 Section 26 A/D Converter AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 26.3, Interface to Bus Master. AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. 26.2.3 A/D Control Register (ADCR) Bit : Initial value : R/W : 7 CK 0 R/W 6 -- 1 -- 5 HCH1 0 R/W 4 HCH0 0 R/W 3 SCH3 0 R/W 2 SCH2 0 R/W 1 SCH1 0 R/W 0 SCH0 0 R/W ADCR is a register that sets A/D conversion speed and selects analog input channel. When executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0. ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Bit 7Clock Select (CK): Sets A/D conversion speed. Bit 7 CK 0 1 Description Conversion frequency is 266 states Conversion frequency is 134 states (Initial value) Note: A/D conversion starts when 1 is written in SST, or when HST is set to 1. The conversion period is the time from when this start flag is set until the flag is cleared at the end of conversion. Actual sample-and-hold takes place (repeatedly) during the conversion frequency shown in figure 26.2. Rev.3.00 Jan. 10, 2007 page 572 of 1038 REJ09B0328-0300 Section 26 A/D Converter States Instruction execution WRITE MOV.B Start flag Conversion frequency Conversion period (134 or 266 states) Interrupt request flag IRQ sampling (CPU) Note: IRQ sampling; When conversion ends, the start flag is cleared and the interrupt request flag is set. The CPU recognizes the interrupt in the last execution state of an instruction, and executes interrupt exception handling after completing the instruction. Figure 26.2 Internal Operation of A/D Converter Bit 6Reserved: This bit cannot be modified and always reads 1. Writes are disabled. Bits 5 and 4Hardware Channel Select (HCH1, HCH0): These bits select the analog input channel that is converted by hardware triggering or triggering by an external input. Only channels AN8 to ANB are available for hardware- or external-triggered conversion. Bit 5 HCH1 0 Bit 4 HCH0 0 1 1 0 1 Analog Input Channel AN8 AN9 ANA ANB (Initial value) Rev.3.00 Jan. 10, 2007 page 573 of 1038 REJ09B0328-0300 Section 26 A/D Converter Bits 3 to 0Software Channel Select (SCH3 to SCH0) These bits select the analog input channel that is converted by software triggering. When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode register 0 (PMR0). For pin settings, see section 26.2.6, Port Mode Register 0 (PMR0). Bit 3 SCH3 0 Bit 2 SCH2 0 Bit 1 SCH1 0 Bit 0 SCH0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 * * Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB No channel selected for software-triggered conversion (Initial value) Legend: * Don't care. Note: If conversion is started by software when SCH3 to SCH0 are set to 11**, the conversion result is undetermined. Hardware- or external-triggered conversion, however, will be performed on the channel selected by HCH1 and HCH0. Rev.3.00 Jan. 10, 2007 page 574 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.2.4 A/D Control/Status Register (ADCSR) Bit : 7 SEND 6 HEND 5 ADIE 4 SST 3 HST 2 BUSY 0 R 1 SCNL 0 R 0 -- 1 -- 0 0 0 0 0 Initial value : R/(W)* R/(W)* R/W R/W R R/W : Note: * Only 0 can be written to bits 7 and 6, to clear the flag. The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D conversion, or check the status of the A/D converter. A/D conversion starts when 1 is written in SST flag. A/D conversion can also start by setting HST flag to 1 by hardware- or external-triggering. For ADTRG start by HSW timing generator in hardware triggering, see section 28.4, HSW (HeadSwitch) Timing Generator. When conversion ends, the converted data is stored in the software-triggered A/D result register (ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0. If software-triggering and hardware- or external-triggering are generated at the same time, priority is given to hardware- or external-triggering. ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Bit 7Software A/D End Flag (SEND): Indicates the end of A/D conversion. Bit 7 SEND 0 1 Description [Clearing Condition] 0 is written after reading 1 [Setting Condition] Software-triggered A/D conversion has ended (Initial value) Rev.3.00 Jan. 10, 2007 page 575 of 1038 REJ09B0328-0300 Section 26 A/D Converter Bit 6Hardware A/D End Flag (HEND): Indicates that hardware- or external-triggered A/D conversion has ended. Bit 6 HEND 0 1 Description [Clearing Condition] 0 is written after reading [Setting Condition] Hardware- or external-triggered A/D conversion has ended (Initial value) Bit 5A/D Interrupt Enable (ADIE): Selects enable or disable of interrupt (ADI) generation upon A/D conversion end. Bit 5 ADIE 0 1 Description Interrupt (ADI) upon A/D conversion end is disabled Interrupt (ADI) upon A/D conversion end is enabled (Initial value) Bit 4Software A/D Start Flag (SST): Starts software-triggered A/D conversion and indicates or controls the end of conversion. This bit remains 1 during software-triggered A/D conversion. When 0 is written in this bit, software-triggered A/D conversion operation can forcibly be aborted. Bit 4 SST 0 Description Read: Indicates that software-triggered A/D conversion has ended or been stopped (Initial value) Write: Software-triggered A/D conversion is aborted 1 Read: Indicates that software-triggered A/D conversion is in progress Write: Starts software-triggered A/D conversion Rev.3.00 Jan. 10, 2007 page 576 of 1038 REJ09B0328-0300 Section 26 A/D Converter Bit 3Hardware A/D Status Flag (HST): Indicates the status of hardware- or external-triggered A/D conversion. When 0 is written in this bit, A/D conversion is aborted regardless of whether it was hardware-triggered or external-triggered. Bit 3 HST 0 Description Read: Hardware- or external-triggered A/D conversion is not in progress(Initial value) Write: Hardware- or external-triggered A/D conversion is aborted. 1 Hardware- or external-triggered A/D conversion is in progress. Bit 2Busy Flag (BUSY): During hardware- or external-triggered A/D conversion, if software attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead the BUSY flag is set to 1. This flag is cleared when the hardware-triggered A/D result register (AHR) is read. Bit 2 BUSY 0 1 Description No contention for A/D conversion (Initial value) Indicates an attempt to execute software-triggered A/D conversion while hardware- or external-triggered A/D conversion was in progress Bit 1Software-Triggered Conversion Cancel Flag (SCNL): Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered A/D conversion. This flag is cleared when A/D conversion is started by software. Bit 1 SCNL 0 1 Description No contention for A/D conversion (Initial value) Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered A/D conversion Bit 0Reserved: This bit cannot be modified and always reads 1. Writes are disabled. Rev.3.00 Jan. 10, 2007 page 577 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.2.5 Trigger Select Register (ADTSR) Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 TRGS1 0 R/W 0 TRGS0 0 R/W Initial value : R/W : The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start factor. ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Bits 7 to 2Reserved: These bits are reserved and are always read as 1. Writes are disabled. Bits 1 and 0Trigger Select: These bits select hardware- or external-triggered A/D conversion start factor. Set these bits when A/D conversion is not in progress. Bit 1 TRGS1 0 Bit 0 TRGS0 0 1 1 0 1 Description Hardware- or external-triggered A/D conversion is disabled (Initial value) Hardware-triggered (ADTRG) A/D conversion is selected Hardware-triggered (DFG) A/D conversion is selected External-triggered (ADTRG) A/D conversion is selected 26.2.6 Port Mode Register 0 (PMR0) Bit : 7 PMR07 0 R/W 6 PMR06 0 R/W 5 PMR05 0 R/W 4 PMR04 0 R/W 3 PMR03 0 R/W 2 PMR02 0 R/W 1 PMR01 0 R/W 0 PMR00 0 R/W Initial value : R/W : Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is specified for each bit. PMR0 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Rev.3.00 Jan. 10, 2007 page 578 of 1038 REJ09B0328-0300 Section 26 A/D Converter Bits 7 to 0P07/AN7 to P00/AN0 pin switching (PMR07 to PMR00): These bits set the P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channel. Bit n PMR0n 0 1 Description P0n/ANn functions as a general-purpose input port P0n/ANn functions as an analog input channel (Initial value) Note: n = 7 to 0 26.2.7 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR consists of 8-bit readable/writable registers and performs module stop mode control. When the MSTP2 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset Bit 2Module Stop (MSTP2): Specifies the A/D converter module stop mode. MSTPCRL Bit 2 MSTP2 0 1 Description A/D converter module stop mode is cleared A/D converter module stop mode is set (Initial value) Rev.3.00 Jan. 10, 2007 page 579 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.3 Interface to Bus Master ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data reading from ADR and AHR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADR and AHR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 26.3 shows the data flow for ADR access. The data flow for AHR access is the same. Upper byte read Module data bus Bus master (H'AA) Bus interface TEMP (H'40) ADRH (H'AA) Lower byte read ADRL (H'40) Bus master (H'40) Bus interface Module data bus TEMP (H'40) ADRH (H'AA) ADRL (H'40) Figure 26.3 ADR Access Operation (Reading H'AA40) Rev.3.00 Jan. 10, 2007 page 580 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. 26.4.1 Software-Triggered A/D Conversion A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. Conversion can be software-triggered on any of the 12 channels provided by analog input pins AN0 to ANB. Bits SCH3 to SCH0 in ADCR select the analog input pin used for softwaretriggered A/D conversion. Pins AN8 to ANB are also available for hardware- or external-triggered conversion. When conversion ends, SEND flag in ADCSR bit is set to 1. If ADIE bit in ADCSR is also set to 1, an A/D conversion end interrupt occurs. If the conversion time or input channel selection in ADCR needs to be changed during A/D conversion, to avoid malfunctions, first clear the SST bit to 0 to halt A/D conversion. If software writes 1 in the SST bit to start software-triggered conversion while hardware- or external-triggered conversion is in progress, the hardware- or external-triggered conversion has priority and the software-triggered conversion is not executed. At this time, BUSY flag in ADCSR is set to 1. The BUSY flag is cleared to 0 when the hardware-triggered A/D result register (AHR) is read. If conversion is triggered by hardware while software-triggered conversion is in progress, the software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and SCNL flag in ADCSR is set to 1. The SCNL flag is cleared when software writes 1 in the SST bit to start conversion after the hardware-triggered conversion ends. Rev.3.00 Jan. 10, 2007 page 581 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.4.2 Hardware- or External-Triggered A/D Conversion The system contains the hardware trigger function that allows to turn on A/D conversion at a specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the incoming external trigger (ADTRG). This function can be used to measure an analog signal that varies in synchronization with an external signal at a fixed timing. To execute hardware- or external-triggered A/D conversion, select appropriate start factor in TRGS1 and TRGS0 bits in ADTSR. When the selected triggering occurs, HST flag in ADCSR is set to 1 and A/D conversion starts. The HST flag remains 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. For ADTRG start by HSW timing generator in hardware triggering, see section 28.4, HSW (Head-Switch) Timing Generator. Setting of the analog input pins on four channels from AN8 to ANB can be modified with the hardware trigger or the incoming external trigger. Setting is done from HCH1 and HCH0 bits on ADCR. Pins AN8 to ANB are also available for software-triggered conversion. When conversion ends, HEND flag in ADCSR is set to 1. If ADIE bit in ADCSR is also set to 1, an A/D conversion end interrupt occurs. If the conversion time or input channel selection in ADCR needs to be changed during A/D conversion, to avoid malfunctions, first clear the HST flag to 0 to halt A/D conversion. If software writes 1 in the SST bit to start software-triggered conversion while hardware- or external-triggered conversion is in progress, the hardware- or external-triggered conversion has priority and the software-triggered conversion is not executed. At this time, BUSY flag in ADCSR is set to 1. The BUSY flag is cleared to 0 when the hardware-triggered A/D result register (AHR) is read. If conversion is triggered by hardware while software-triggered conversion is in progress, the software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and SCNL flag in ADCSR is set to 1 (the SCNL flag is cleared when software writes 1 in the SST bit to start conversion after the hardware-triggered conversion ends). The analog input channel changes automatically from the channel that was undergoing software-triggered conversion (selected by bits SCH3 to SCH0 in ADCR) to the channel selected by bits HCH1 and HCH0 in ADCR for hardware- or external-triggered conversion. After the hardware- or external-triggered conversion ends, the channel reverts to the channel selected by the software-triggered conversion channel select bits in ADCR. Hardware- or external-triggered conversion has priority over software-triggered conversion, so the A/D interrupt-handling routine should check the SCNL and BUSY flags when it processes the converted data. Rev.3.00 Jan. 10, 2007 page 582 of 1038 REJ09B0328-0300 Section 26 A/D Converter 26.5 Interrupt Sources When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end interrupt can be enabled or disabled by ADIE bit in ADCSR. Figure 26.4 shows the block diagram of A/D conversion end interrupt. A/D control/status register (ADCSR) SEND HEND ADIE A/D conversion end interrupt (ADI) To interrupt controller Figure 26.4 Block Diagram of A/D Conversion End Interrupt Rev.3.00 Jan. 10, 2007 page 583 of 1038 REJ09B0328-0300 Section 26 A/D Converter Rev.3.00 Jan. 10, 2007 page 584 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) Section 27 Address Trap Controller (ATC) 27.1 Overview The address trap controller (ATC) is capable of generating interrupt by setting an address to trap, when the address set appears during bus cycle. 27.1.1 Features Address to trap can be set independently at three points. 27.1.2 Block Diagram Figure 27.1 shows a block diagram of the address trap controller. Modules bus Bus interface TRCR TAR0 TAR1 TAR2 Trap condition comparator Internal bus Interrupt request Legend: TRCR : Trap control register TAR0 to 2 : Trap address register 0 to 2 Figure 27.1 Block Diagram of ATC Rev.3.00 Jan. 10, 2007 page 585 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.1.3 Register Configuration Table 27.1 Register List Name Address trap control register Trap address register 0 Trap address register 1 Trap address register 2 Note: * Abbrev. ATCR TAR0 TAR1 TAR2 R/W R/W R/W R/W R/W Initial Value H'F8 H'F00000 H'F00000 H'F00000 Address* H'FFB9 H'FFB0 to H'FFB2 H'FFB3 to H'FFB5 H'FFB6 to H'FFB8 Lower 16 bits of the address. 27.2 27.2.1 Register Descriptions Address Trap Control Register (ATCR) Bit : 7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TRC2 0 R/W 1 TRC1 0 R/W 0 TRC0 0 R/W Initial value : R/W : 1 -- Bits 7 to 3Reserved: When read, 1 is read at all times. Writes are disabled. Bit 2Trap Control 2 (TRC2): Sets ON/OFF operation of the address trap function 2. Bit 2 TRC2 0 1 Description Address trap function 2 disabled Address trap function 2 enabled (Initial value) Bit 1Trap Control 1 (TRC1): Sets ON/OFF operation of the address trap function 1. Bit 1 TRC1 0 1 Description Address trap function 1 disabled Address trap function 1 enabled (Initial value) Rev.3.00 Jan. 10, 2007 page 586 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) Bit 0Trap Control 0 (TRC0): Sets ON/OFF operation of the address trap function 0. Bit 0 TRC0 0 1 Description Address trap function 0 disabled Address trap function 0 enabled (Initial value) 27.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) Bit : 7 A23 6 A22 0 R/W 6 A14 0 R/W 6 A6 0 R/W 5 A21 0 R/W 5 A13 0 R/W 5 A5 0 R/W 4 A20 0 R/W 4 A12 0 R/W 4 A4 0 R/W 3 A19 0 R/W 3 A11 0 R/W 3 A3 0 R/W 2 A18 0 R/W 2 A10 0 R/W 2 A2 0 R/W 1 A17 0 R/W 1 A9 0 R/W 1 A1 0 R/W 0 A16 0 R/W 0 A8 0 R/W 0 -- 0 -- Initial value : R/W : Bit : 0 R/W 7 A15 Initial value : R/W : Bit : 0 R/W 7 A7 Initial value : R/W : 0 R/W The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0) The TAR sets the address to trap. The function of the TAR2 to TAR0 is the same. The TAR is initialized to H'00 by a reset. TARA bits 7 to 0: Addresses 23 to 16 (A23 to A16) TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8) TARC bits 7 to 0: Addresses 7 to 1 (A7 to A1) If the value installed in this register and internal address buses A23 to A1 match as a result of comparison, an interruption occurs. For the address to trap, set to the address where the first byte of an instruction exists. In the case of other addresses, it may not be considered that the condition has been satisfied. Bit 0 of this register is fixed at 0. The address to trap becomes an even address. The range where comparison is made is H'000000 to H'FFFFFE. Rev.3.00 Jan. 10, 2007 page 587 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.3 Precautions in Usage Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur after the trap instruction has been executed, depending on a combination of instructions immediately preceding the setting up of the address trap. If the instruction to trap immediately follows the branch instruction or the conditional branch instruction, operation may differ, depending on whether the condition was satisfied or not, or the address to be stacked may be located at the branch. Figures 27.2 to 27.22 show specific operations. For information as to where the next instruction prefetch occurs during the execution cycle of the instruction, see appendix A.5, Bus Status during Instruction Execution, of this manual or section 2.7, Bus State during Execution of Instruction, H8S/2600 Series, H8S/2000 Series Software Manual. (R:W NEXT is the next instruction prefetch.) 27.3.1 Basic Operations After terminating the execution of the instruction being executed in the second state from the trap address prefetch, the address trap interrupt exception handling is started. (1) Figure 27.2 shows the operation when the instruction immediately preceding the trap address is that of 3 states or more of the execution cycle and the next instruction prefetch occurs in the state before the last 2 states. The address to be stacked is 0260. MOV NOP Internal instruc- instruc- operation tion tion pre-fetch pre-fetch Data read Start of exception handling (ER3 = H'0000) Immediately Address preceding 025E MOV.B @ER3+,R2L Instruction * 0260 NOP 0262 NOP 0264 NOP Address bus 025E 0260 0000 0262 MOV execution Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.2 Basic Operations (1) Note: In the figure above, the NOP instruction is used as the typical example of instruction with execution cycle of 1 state. Other instructions with the execution cycle of 1 state also apply (Ex. MOV.B, Rs, Rd). Rev.3.00 Jan. 10, 2007 page 588 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (2) Figure 27.3 shows the operation when the instruction immediately preceding the trap address is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the second state from the last. The address to be stacked is 0268. MOV NOP Data instruc- instruc- read tion tion pre-fetch pre-fetch NOP instruction pre-fetch Start of exception handling Address bus 0266 0268 0000 026A MOV execution Interrupt request signal NOP execution 026C Immediately Address preceding 0266 MOV.B R2L, @0000 instruction * 0268 NOP 026A NOP 026C NOP Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.3 Basic Operations (2) (3) Figure 27.4 shows the operation when the instruction immediately preceding the trap address is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to be stacked is 025C. NOP NOP NOP NOP instruc- instruc- instruc- instruction tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 0256 0258 025A 025C NOP NOP NOP execu- execu- execution tion tion Address Immediately 0256 NOP * 0258 NOP preceding 025A NOP instruction 025C NOP 025E NOP 025E Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.4 Basic Operations (3) Rev.3.00 Jan. 10, 2007 page 589 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.3.2 Enable The address trap function becomes valid after executing one instruction following the setting of the enable bit of the address trap control register (TRCR) to 1. 029C *029E 02A0 02A2 02A4 02A6 BSET #0, @TRCR MOV.W R0, R1 MOV.B R1L, R3H NOP CMP.W R0, R1 NOP After executing the MOV instruction, the address trap interrupt does not arise, and the next instruction is executed. Note: * Trap setting address Figure 27.5 Enable 27.3.3 Bcc Instruction (1) When the condition is satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is satisfied by the Bcc instruction and then branched, transition is made to the address trap interrupt after executing the instruction at the branch. The address to be stacked is 02A8. BEQ NOP CMP NOP instruc- instruc- instruc- instruction tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling (NEXT = H'02A6) 029C * 029E 02A0 02A2 02A4 02A6 02A8 BEQ NEXT:8 NOP NOP NOP NOP CMP.W R0, R1 NOP Address bus 029C 029E 02A6 02A8 BEQ execution CMP execution 02AA Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.6 When the Condition Is Satisfied by Bcc Instruction (8-Bit Displacement) Rev.3.00 Jan. 10, 2007 page 590 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (2) When the condition is not satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction and prefetching the next instruction. The address to be stacked is 02A2. BEQ NOP CMP NOP instruc- instruc- instruc- instruction tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling (NEXT = H'02A8) 029E * 02A0 02A2 02A4 02A6 NEXT: 02A8 02AA BEQ NEXT:8 NOP NOP NOP NOP CMP.W R0, R1 NOP Address bus 029E 02A0 02A8 02A2 BEQ execution NOP execution 02A4 Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.7 When the Condition Is Not Satisfied by Bcc Instruction (8-Bit Displacement) Rev.3.00 Jan. 10, 2007 page 591 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (3) When condition is not satisfied by Bcc instruction (16-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction (if the trap address instruction is that of 2 states or more. If the instruction is that of 1 state, after executing two instructions). The address to be stacked is 02C0. BEQ instruction pre-fetch Data fetch Internal operation NOP NOP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Start of exception handling (NEXT = H'02C4) 02B8 BEQ NEXT:16 * 02BC NOP 02BE NOP 02C0 NOP 02C2 NOP NEXT: 02C4 NOP Address bus 02B8 02BA 02BC 02BE 02C0 NOP NOP execu- execution tion 02C2 BEQ execution Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.8 When the Condition Is Not Satisfied by Bcc Instruction (16-Bit Displacement) Rev.3.00 Jan. 10, 2007 page 592 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (4) When the condition is not satisfied by Bcc instruction (Trap address at branch) When the trap address is at the branch of the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made into the address trap interrupt after executing the next instruction (if the next instruction is that of 2 states or more. If the next instruction is that of 1 state, after executing two instructions). The address to be stacked is 0262. BEQ NOP CMP NOP NOP instruc- instruc- instruc- instruc- instruction tion tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling (NEXT = H'0266) 025C 025E 0260 0262 0264 NEXT: * 0266 0268 BEQ NEXT:8 NOP NOP NOP NOP CMP.W R0, R1 NOP Address bus 025C 025E 0266 0260 0262 BEQ execution NOP NOP execu- execution tion 0264 Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.9 When the Condition Is Not Satisfied by Bcc Instruction (Trap Address at Branch) Rev.3.00 Jan. 10, 2007 page 593 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.3.4 BSR Instruction (1) BSR Instruction (8-Bit Displacement) When the trap address is the next instruction to the BSR instruction and the addressing mode is an 8-bit displacement, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C2. BSR NOP MOV instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Stack saving Start of exception handling 0294 * 0296 0298 : (@ER0 = H'02C2) BSR @ER0 NOP NOP : MOV.W R4, @OUT NOP Address bus 0294 0296 02C2 SP-2 SP-4 BSR execution 02C4 02C2 02C4 Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.10 BSR Instruction (8-Bit Displacement) Rev.3.00 Jan. 10, 2007 page 594 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.3.5 JSR Instruction (1) JSR Instruction (Register Indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C8. JSR NOP MOV instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Stack saving Start of exception handling (@ER0 = H'02C8) 029A * 029C 029E : JSR @ER0 NOP NOP : MOV.W R4, @OUT NOP Address bus 029A 029C 02C8 SP-2 SP-4 JSRexecution 02CA 02C8 02CE Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.11 JSR Instruction (Register Indirect) (2) JSR Instruction (Memory Indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02EA. JSR NOP instruc- instruction tion pre-fetch pre-fetch Data fetch Stack saving NOP instruction pre-fetch Start of exception handling 006C : 0294 * 0296 0298 : 02EA 02EC H'02EA : JSR @@H'6C:8 NOP NOP : NOP NOP Address bus 0294 0296 006C 006E SP-2 SP-4 02EA JSR execution 02EC Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.12 JSR Instruction (Memory Indirect) Rev.3.00 Jan. 10, 2007 page 595 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.3.6 JMP Instruction (1) JMP Instruction (Register Indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02AA. JMP NOP MOV instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Data fetch NOP instruction pre-fetch Start of exception handling (@ER0 = H'02A4) 029A * 029C 029E 02A0 02A2 02A4 02AA JMP @ER0 NOP NOP NOP NOP MOV.L #DATA, ER1 NOP Address bus 029A 029C 02A4 02A6 02A8 02AA JMP execution Interrupt request signal MOV.L execution 02AC Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.13 JMP Instruction (Register Indirect) (2) JMP Instruction (Memory Indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02E4. JMP NOP instruc- instruction tion pre-fetch pre-fetch Data fetch Internal NOP opera- instruction tion pre-fetch Start of exception handling 006C : 0294 * 0296 0298 : 02E4 02E6 H'02E4 : JMP @@H'6C:8 NOP NOP : NOP NOP Address bus 0294 0296 006C 006E 006C 02E4 JMP execution 02E6 Interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.14 JMP Instruction (Memory Indirect) Rev.3.00 Jan. 10, 2007 page 596 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 27.3.7 RTS Instruction When the trap address is the next instruction to the RTS instruction, transition is made to the address trap interrupt after reading the CCR and PC from the stack and prefetching the instruction at the return location. The address to be stacked is 0298. RTS NOP instruc- instruction tion pre-fetch pre-fetch Stack storing Internal NOP opera- instruction tion pre-fetch Start of exception handling Address bus 02AC 02AE SP SP+2 SP 0298 029A 0296 0298 029A BSR SUB NOP NOP : 02AC * 02AE : RTS NOP RTS execution Break interrupt request signal Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.15 RTS Instruction 27.3.8 SLEEP Instruction (1) SLEEP Instruction 1 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does not occur in the last state, the SLEEP instruction is not executed and transition is made to the address trap interrupt without going into SLEEP mode. The address to be stacked is 0274. MOV SLEEP Data NOP instruc- instrucinstrucwrite tion tion tion pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 0272 0274 FFF9 MOV execution Interrupt request signal 0276 SLEEP cancel SP-2 SP-4 0272 * 0274 0276 0278 : MOV.B R2L, @FFF8 SLEEP NOP NOP : Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.16 SLEEP Instruction (1) Rev.3.00 Jan. 10, 2007 page 597 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (2) SLEEP Instruction 2 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling. The address to be stacked is 0264. NOP SLEEP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 0260 0262 NOP SLEEP execution execution Interrupt request signal 0264 SLEEP mode SP-2 SP-4 0260 * 0262 0264 0266 : NOP SLEEP NOP NOP : Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.17 SLEEP Instruction (2) (3) SLEEP Instruction 3 When the trap address is the next instruction to the SLEEP instruction, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling. The address to be stacked is 0282. SLEEP NOP instruc- instruction tion pre-fetch pre-fetch Start of exception h andling Address bus 0280 SLEEP execution Interrupt request signal 0282 SLEEP mode SP-2 SP-4 027E 0280 * 0282 0284 : NOP SLEEP NOP NOP : Note: * Trap setting address The underlines address is the one to be actually stacked. Figure 27.18 SLEEP Instruction (3) Rev.3.00 Jan. 10, 2007 page 598 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (4) SLEEP Instruction 4 (Standby or Watch Mode Setting) When the trap address is the SLEEP instruction and the instruction immediately preceding the SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode is cancelled by the NMI interrupt, transition is made to NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector reading. However, if the address trap interrupt arises before starting execution of the NMI interrupt processing, transition is made to the address trap exception handling. The address to be stacked is the starting address of the NMI interrupt processing. NOP SLEEP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch NMI interrupt Address trap interruption Address bus 0262 0264 0266 SLEEP Standby execution mode Interrupt request signal SP-2 SP-2 0262 * 0264 0266 NOP SLEEP NOP Note: * Trap setting address Figure 27.19 SLEEP Instruction (4) (Standby or Watch Mode Setting) Rev.3.00 Jan. 10, 2007 page 599 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (5) SLEEP Instruction 5 (Standby or Watch Mode Setting) When the trap address is the next instruction to the SLEEP instruction, this puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode is cancelled by the NMI interruption, transition is made to the NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector reading. However, if the address trap interrupt arises before starting execution of the NMI interrupt processing, transition is made to the address trap exception handling. The address to be stacked is the starting address of the NMI interrupt processing. NOP SLEEP instruc- instruction tion pre-fetch pre-fetch NMI interruption Address trap interrupt Address bus 0280 0282 0284 SLEEP Standby execution mode Interrupt request signal SP-2 SP-2 0280 0282 * 0284 NOP SLEEP NOP Note: * Trap setting address Figure 27.20 SLEEP Instruction (5) (Standby or Watch Mode Setting) 27.3.9 Competing Interrupt (1) General Interrupt (Interrupt Other Than NMI) When the ATC interrupt request is made at the timing in (1) (A) against the general interrupt request, the interruption appears to take place in the ATC at the timing earlier than usual, because higher priority is assigned to the ATC interrupt processing (Simultaneous interrupt with the general interrupt has no effect on processing). The address to be stacked is 029E. For comparison, the case where the trap address is set at 02A0 if no general interrupt request was made is shown in (2). The address to be stacked is 02A4. Rev.3.00 Jan. 10, 2007 page 600 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) 0296 MOV.B R2L, @Port 029A NOP 029C NOP Set one of these to the 029E NOP 02A0 NOP trap address 02A2 NOP 02A4 NOP Start of general (1) NOP MOV instruc- Data instruction tion read pre-fetch pre-fetch Data write interrupt processing NOP NOP instruc- instruction tion pre-fetch pre-fetch Range of start of ATC interrupt processing Address bus 0296 0298 029A Port 029C 029E 02A0 SP-2 SP-4 Vector Vector MOV execution NOP NOP execu- execution tion General Interrupt request signal (A) Interrupt request signal Address to be stacked (2) 0296 MOV.B R2L, @Port 029A NOP 029C NOP 029E NOP 02A0 NOP Trap address 02A2 NOP 02A4 NOP MOV NOP instruc- Data instruction read tion pre-fetch pre-fetch Data write NOP NOP NOP NOP NOP instruc- instruc- instruc- instruc- instruction tion tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch Start of ATC interrupt processing Address bus 0296 0298 029A Port 029C 029E 02A0 02A2 02A4 02A6 SP-2 MOV execution NOP NOP NOP NOP NOP execu- execu- execu- execu- execution tion tion tion tion Interrupt request signal Figure 27.21 Competing Interrupt (General Interrupt) Rev.3.00 Jan. 10, 2007 page 601 of 1038 REJ09B0328-0300 Section 27 Address Trap Controller (ATC) (2) In Case of NMI When the NMI interruption request is made at the timing in (1) (A) against the ATC interrupt request, the interrupt appears to take place in NMI at the timing earlier than usual, because higher priority is assigned to the NMI interrupt processing. The ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing. The address to be stacked is 02E0 for the NMI and 340 for the ATC. When the ATC interrupt request is made at the timing in (2) (B) against the NMI interrupt request, the ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing. The address to be stacked is 02E6 for the NMI and 0340 for the ATC. Rev.3.00 Jan. 10, 2007 page 602 of 1038 REJ09B0328-0300 (1) NMI interrupt processing Start of ATC interrupt processing NOP NOP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Start of ATC interrupt processing NOP instruction pre-fetch 02E2 NMI vector read SP-2 SP-4 Vector Vector Vector 0340 0342 SP-6 SP-8 Vector Address bus 02DC 02DE 02E0 NOP NOP execu- execution tion (A) NMI interrupt request signal ATC interrupt request signal 02DC 02DE 02E0 02E2 02E4 02E6 02E8 : : 0340 NOP (1) Set to the trap address NOP NOP NOP NOP (2) Set one of these to NOP the trap address NOP : : The starting address of NMI interrupt NOP instruction pre-fetch (2) NOP NOP NOP NOP NOP NOP instruc- instruc- instruc- instruc- instruc- instruction tion tion tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch NMI interrupt processing Start of ATC Interrupt processing 02E8 SP-2 SP-4 Vector Vector Vector 0340 0342 Address bus 02DC 02DE 02E0 02E2 02E4 02E6 Figure 27.22 Competing Interrupt (In Case of NMI) (B) NMI interrupt request signal Section 27 Address Trap Controller (ATC) Rev.3.00 Jan. 10, 2007 page 603 of 1038 REJ09B0328-0300 ATC interrupt request signal Section 27 Address Trap Controller (ATC) Rev.3.00 Jan. 10, 2007 page 604 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Section 28 Servo Circuits 28.1 28.1.1 Overview Functions Servo circuits for a video cassette recorder are included on-chip. The functions of the servo circuits can be divided into four groups, as listed in table 28.1. Rev.3.00 Jan. 10, 2007 page 605 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Table 28.1 Servo Circuit Functions Group (1) Input and output circuits Function CTL I/O amplifier CFGDuty compensation input DFG, DPG separation/overlap input Reference signal generators HSW timing generator Description Gain variable input amplifier Output amplifier with rewrite mode Duty accuracy: 50 2% (Zero cross type comparator) Overlap input available: Three-level input method, DFG noise mask function V compensation, field detection, external signal sync, V sync when in REC mode, REF30 signal output to outside Head-switching signals, FIFO 20 stages Compatible with DFG counter soft-reset Four-head high-speed Chroma-rotary/head-amplifier switching output switching circuit for special playback 12-bit PWM Sync detection circuit (2) Error detectors Improved speed of carrier frequency Noise count, field discrimination, Hsync compensation, Hsync detection noise mask Frequency division circuit With CFG mask, no CFG for phase or CTL mask Drum speed error detector Lock detector function, pause at the counter overflow, R/W error latch register, limiter function Drum phase error detector Latch signal selectable, R/W error latch register Capstan speed error detector Capstan phase error detector Lock detector function, pause at the counter overflow, R/W error latch register, limiter function R/W error latch register X-value adjustment and (Separate setting available) tracking adjustment circuit (3) Phase and gain compensation Digital filter computation circuit Computations performed automatically by hardware Output gain variable: x2 to x64 (exponents of 2) -1 (Partial write in Z (high-order 8 bits) available) Duty discrimination circuit, CTL head R/W control, compatible with wide aspect (4) Other circuits Additional V signal circuit Valid when in special playback CTL circuit Rev.3.00 Jan. 10, 2007 page 606 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.1.2 Block Diagram Figure 28.1 shows a block diagram of the servo circuits. PPG0 to 7/ (P70 to 77) PPG0 to 7/ (P70 to 77) PR0 to 7/ (P60 to 67) PR0 to 7/ (P60 to 67) EXTTRG/(P80) Csync COMP(PS2) C.ROTARY(PS0) H.Amp SW(PS1) 4-head special playback controller Additional V pulse generator Sync detector OSCH VD System clock REC:ON Res Drum system reference signal XE:ON Capstan system reference signal Vpulse AUDIOFF VIDEOFF Head-switch timing generator ADTRIG (HSW) REF30P(PB:30 Hz, REC:1/2VD) DPG(PS3) DFG Noise Det. Phase error detector Ep Digital filter DRM PWM Speed error detector PWM Gain up. Digital filter Es + + A/D converter AN pins PWM Gain up. Frequency divider DVCFG + Es CFG Speed error detector DVCFG2 CREF CA P PWM Digital filter + Timer X1 Timer L Timer R REF30,REF30X,CREF, CTLMONI,DVCFG, DFG,DPG,DFG,etc DVCTL Internal signal monitor controller SV1(P82) ( ) SV2(P83) ( ) EXCTL(PS4) ) REC Phase error detector Ep Digital filter PB.ASM (NTSC) PB. ASM REC X-value adjustment (PAL) REF30X REC-CTL generator (Assemble recording) Frequency divider CTLFB PB.CTL CTL Amp +-+ Gain control by register setting VISS circuit (Duty deter- DutyI/O minator) CTL Head + CTL Head -+ REC-CTL EXCAP(P81) Figure 28.1 Block Diagram of Servo Circuits Rev.3.00 Jan. 10, 2007 page 607 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.2 28.2.1 Servo Port Overview This LSI is equipped with seventeen pins dedicated to servo module and twenty-five dual-purpose pins used also for general-purpose port. It has also built-in input amplifier to amplify CTL signals, CTL output amplifier, CTL Schmitt comparator, and CFG zero cross type comparator. The CTL input amplifier allows gain adjustment by software. DFG and DPG signals, which are the signals to control the drum, allow selection between separate or overlap input. SV1 and SV2 pins allow to output to monitor the inside signals of the servo section. The signals to be output can be selected out of eight kinds of signals. See section 28.2.5 (4), Servo Monitor Control Register (SVMCR). 28.2.2 Block Diagram (1) DFG and DPG Input Circuits The DFG and DPG input pins have on-chip Schmitt circuits. Figure 28.2 shows the input circuits of DFG and DPG. DPG SW DFG DFG DPG DPG RES+LPM DPG SW Figure 28.2 Input Circuits of DFG and DPG (2) CFG Input Circuit The CFG input pin has built-in an amplifier and a zero cross type comparator. Figure 28.3 shows the input circuit of CFG. Rev.3.00 Jan. 10, 2007 page 608 of 1038 REJ09B0328-0300 Section 28 Servo Circuits P250 BIAS + VREF REF M250 S O R stp F/F CFGCOMP CFGCOMP CFG + + CFG VREF - RES+ModuleSTOP Figure 28.3 CFG Input Circuit (3) CTL Input Circuit The CTL input pin has built-in an amplifier. Figure 28.4 shows the input circuit of CTL. AMPON (PB-CTL) AMPSHORT (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 -+ + - - + PB-CTL(+) PB-CTL(-) CTL(-) CTL(+) CTLREF CTLBias CTLFB CTLAmp(o) CTLSMT(i) Note Note: Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i) Figure 28.4 CTL Input Circuit Rev.3.00 Jan. 10, 2007 page 609 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.2.3 Pin Configuration Table 28.2 shows the pin configuration of the servo section. P6n, P7n, P80 to P83, and PS1 to PS4 are general-purpose ports. As for P6, P7, and P8, see section 11, I/O Port. Table 28.2 Pin Configuration Name Servo Vcc pin Servo Vss pin Audio head switching pin Video head switching pin Capstan mix pin Drum mix pin Additional V pulse pin Color rotary signal output pin Abbrev. SVCC SVSS Audio FF Video FF CAPPWM DRMPWM Vpulse I/O Input Input Output Output Output Output Output Function Power source pin for servo section Power source pin for servo section Audio head switching signal output Video head switching signal output 12-bit PWM square wave output 12-bit PWM square wave output Additional V signal output C.Rotary/PS0 Output, I/O Control signal output port for processing color signals/generalpurpose port H.Amp. SW/ PS1 COMP/PS2 CTL (+) CTL (-) CTLBias CTLAMP (O) CTLSMT (i) CTLFB CTLREF Output, I/O Pre-amplifier output selection signal output/general-purpose port Input, I/O I/O I/O Input Output Input Input Output Input Input Input, I/O Input, I/O Input Pre-amplifier output result signal input/general-purpose port CTL signal input/output CTL signal input/output CTL primary amplifier bias supply CTL amplifier output CTL Schmitt amplifier input CTL amplifier high-range characteristics control CTL amplifier reference voltage output CFG signal amplifier input DFG signal input DPG signal input/general-purpose port External CTL signal input/generalpurpose port Complex sync signal input Head amplifier switching pin Compare signal input pin CTL (+) I/O pin CTL (-) I/O pin CTL Bias input pin CTL Amp (O) output pin CTL SMT (i) input pin CTL FB input pin CTL REF output pin Capstan FG amplifier input pin CFG Drum FG input pin Drum PG input pin External CTL signal input pin DFG DPG/PS3 EXCTL/PS4 Complex sync signal input pin Csync Rev.3.00 Jan. 10, 2007 page 610 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Name Abbrev. I/O Function General-purpose port/external reference signal input General-purpose port/external capstan signal input External reference signal input P80/EXTTRG I/O, input pin External capstan signal input pin P81/EXCAP I/O, input Servo monitor signal output pin P82/SV1 1 Servo monitor signal output pin P83/SV2 2 PPG output pin RTP output pin P7n/PPGn P6n/RPn I/O, output General-purpose port/servo monitor signal output I/O, output General-purpose port/servo monitor signal output I/O, output General-purpose port/PPG output I/O, output General-purpose port/RTP output 28.2.4 Register Configuration Table 28.3 shows the register configuration of the servo port section. Table 28.3 Register Configuration Name Servo port mode register Servo control register Servo data register Servo monitor control register CTL gain control register Abbrev. SPMR SPCR SPDR SVMCR CTLGR R/W R/W W R/W R/W R/W Size Byte Byte Byte Byte Byte Initial Value Address H'40 H'E0 H'E0 H'C0 H'C0 H'FD0A0 H'FD0A1 H'FD0A2 H'FD0A3 H'FD0A4 Rev.3.00 Jan. 10, 2007 page 611 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.2.5 Register Descriptions (1) Servo Port Mode Register (SPMR) Bit : Initial value : R/W : 7 CTLSTOP 0 R/W 6 -- 1 -- 5 4 3 CFGCOMP EXCTLON DPGSW 0 R/W 0 R/W 0 R/W 2 COMP 0 R/W 1 H.Amp.SW 0 R/W 0 C.Rot 0 R/W A register to switch the servo port/general-purpose port, and the CFG input system. SPMR is an 8-bit read/write register. Bit 6 is reserved; writing in it is invalid. If read is attempted, an undetermined value is read out. It is initialized to H'40 by a reset or stand-by. Bit 7CTLSTOP Bit (CTLSTOP): Controls whether the CTL circuits are operated or stopped. Bit 7 CTLSTOP 0 1 Description CTL circuits operate CTL circuits stop operation (Initial value) Bit 6Reserved: This bit is reserved. It cannot be written or read. If read is attempted, an undetermined value is read out. Bit 5CFG Input System Switching Bit (CFGCOMP): Selects whether the CFG input signal system is set to the zero cross type comparator system or digital signal input system. Bit 5 CFGCOMP Description 0 1 CFG signal input system is set to the zero cross type comparator system (Initial value) CFG signal input system is set to the digital signal input system Bit 4EXCTL Pin Switching Bit (EXCTLON): Selects whether the EXCTL/PS4 pin is used as the EXCTL input pin or PS4 (general-purpose I/O pin). Bit 4 EXCTLON 0 1 Description EXCTL/PS4 pin functions as EXCTL input pin EXCTL/PS4 pin functions as PS4 I/O (Initial value) Rev.3.00 Jan. 10, 2007 page 612 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 3DPG Pin Switching Bit (DPGSW): Selects the drum control system input signals (DFG, DPG) as separate or overlapped inputs. Bit 3 DPGSW 0 1 Description Drum control system inputs are separate inputs (DPG/PS3 pin functions as DPG input pin) Drum control system inputs are overlapped inputs (DPG/PS3 pin functions as PS3 I/O pin) (Initial value) Bit 2COMP Pin Switching Pin (COMP): Selects whether the COMP/PS2 pin is used as the COMP input pin or PS2 (general-purpose I/O pin). Bit 2 COMP 0 1 Description COMP/PS2 pin functions as COMP input pin COMP/PS2 pin functions as PS2 I/O pin (Initial value) Bit 1H.Amp SW Pin Switching Bit (H.Amp.SW): Selects whether the H.Amp SW/PS1 pin is used as the H.Amp SW output pin or PS1 (general-purpose I/O pin). Bit 1 H.Amp.SW Description 0 1 H.Amp SW/PS1 pin functions as H.Amp SW output pin H.Amp SW/PS1 pin functions as PS1 I/O pin (Initial value) Bit 0C.Rotary Pin Switching Bit (C.Rot): Selects whether the C.Rotary/PS0 pin is used as the C.Rotary output pin or PS0 (general-purpose I/O pin). Bit 0 C.Rot 0 1 Description C.Rotary/PS0 pin functions as C.Rotary output pin C.Rotary/PS0 pin functions as PS0 I/O pin (Initial value) Rev.3.00 Jan. 10, 2007 page 613 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Servo Control Register (SPCR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SPCR4 0 W 3 SPCR3 0 W 2 SPCR2 0 W 1 SPCR1 0 W 0 SPCR0 0 W Controls input and output of each pin (PS4 to PS0) for each bit when the servo port/generalpurpose port dual-purpose pin is used as the general-purpose port. If SPCR is set to 1, the corresponding PS4 to PS0 pins function as output pins; if cleared to 0, they function as input pins. Settings of SPCR and SPDR are valid if the corresponding pins are set to general-purpose I/O by SPMR. SPCR is an 8-bit write-only register. If read is attempted, an undetermined value is read out. Bits 7 to 5 are reserved bits. Writes are disabled. SPCR is initialized to H'E0 by a reset or stand-by. Bit n SPCRn 0 1 Description PSn pin functions as input PSn pin functions as output (Initial value) (3) Servo Data Register (SPDR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SPDR4 0 R/W 3 SPDR3 0 R/W 2 SPDR2 0 R/W 1 SPDR1 0 R/W 0 SPDR0 0 R/W Stores the data of each pin (PS4 to PS0) when the servo port/general-purpose dual-purpose pin is used as general-purpose port. If the port is accessed for read when SPCR is 1 (output), the SPDRn value is read directly. Accordingly, this register is not affected by the state of the pin. If the port is accessed for read when SPCR is 0 (input), the state of the pin is read out. SPDR is an 8-bit read/write register. Bits 7 to 5 are reserved. No write in it is valid. If read is attempted, an undetermined value is read out. SPCR is initialized to H'E0 by reset or stand-by. Rev.3.00 Jan. 10, 2007 page 614 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (4) Servo Monitor Control Register (SVMCR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 4 3 2 1 0 SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Selects the monitor signal output to the SV1 and SV2 pins when the P82/SV1 pin is used as the SV1 monitor output pin or when the P83/SV2 pin is used as the SV2 monitor output pin. SVMCR is an 8-bit read/write register. Bits 7 and 6 are reserved. Writes are disabled. If read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset or stand-by. Bit 5 SVMCR5 0 Bit 4 SVMCR4 0 Bit 3 SVMCR3 0 1 1 0 1 1 0 0 1 1 0 1 Description Outputs REF30 signal to SV2 output pin (Initial value) Outputs CAPREF30 signal to SV2 output pin Outputs CREF signal to SV2 output pin Outputs CTLMONI signal to SV2 output pin Outputs DVCFG signal to SV2 output pin Outputs CFG signal to SV2 output pin Outputs DFG signal to SV2 output pin Outputs DPG signal to SV2 output pin Bit 2 SVMCR2 0 Bit 1 SVMCR1 0 Bit 0 SVMCR0 0 1 Description Outputs REF30 signal to SV1 output pin (Initial value) Outputs CAPREF30 signal to SV1 output pin Outputs CREF signal to SV1 output pin Outputs CTLMONI signal to SV1 output pin Outputs DVCFG signal to SV1 output pin Outputs CFG signal to SV1 output pin Outputs DFG signal to SV1 output pin Outputs DPG signal to SV1 output pin 1 0 1 1 0 0 1 1 0 1 Rev.3.00 Jan. 10, 2007 page 615 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (5) CTL Gain Control Register (CTLGR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 CTLE/A 0 R/W 4 CTLFB 0 R/W 3 CTLGR3 0 R/W 2 CTLGR2 0 R/W 1 CTLGR1 0 R/W 0 CTLGR0 0 R/W Sets the CTLFB switch in the CTL amplifier circuit to on/off and CTL amplifier gain. CTLGR is an 8-bit read/write register. Bits 7 and 6 are reserved. No write in it is valid. If read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset or stand-by. Bits 7 and 6Reserved: Reserved bits; writes are disabled. If read was attempted, an undetermined value is read out. Bit 5CTL Selection Bit (CTLE/A): Controls whether the amplifier output or EXCTL is used as the CTLP signal supplied to the CTL circuit. Bit 5 CTLE/A 0 1 Description AMP output EXCTL (Initial value) Bit 4SW Bit of the Feedback Section of CTL Amplifier (CTLFB): Turning on/off the SW of the feedback section allows adjustment of gain. See figure 28.4, CTL Input Circuit. Bit 4 CTLFB 0 1 Description Turns off CTLFB SW Turns on CTLFB SW (Initial value) Rev.3.00 Jan. 10, 2007 page 616 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 3 to 0CTL Amplifier Gain Setting Bits (CTLGR3 to 0): Set the output gain of the CTL amplifier. Bit 3 CTLGR3 0 Bit 2 CTLGR2 0 Bit 1 CTLGR1 0 Bit 0 CTLGR0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 CTL Output Gain 34.0 dB 36.5 dB 39.0 dB 41.5 dB 44.0 dB 46.5 dB 49.0 dB 51.5 dB 54.0 dB 56.5 dB 59.0 dB 61.5 dB 64.0 dB* 66.5 dB* 69.0 dB* 71.5 dB* (Initial value) With a setting of 64.0 dB or more, the CTLAMP is in a very sensitive status. When configuring the set board, be concerned about countermeasure against noise around the control head signal input port. Also, thoroughly set the filter between the CTLAMP and CTLSMT. Rev.3.00 Jan. 10, 2007 page 617 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.2.6 DFG/DPG Input Signals DFG and DPG signals allow either separate or overlapped input. If the latter was selected (DPGSW = 1), take care in the input levels of DFG and DPG. Figure 28.5 shows DFG/DPG input signals. DPG DPG Schmitt level 3.45/3.55 VIL/VIH DFG DFG Schmitt level 1.85/1.95 VIL/VIH (1) DPG/DFG separate input (DPGSW = 0) DFG/DPG DPG Schmitt level DFG Schmitt level (2) DPG/DFG overlapped input (DPGSW = 1) Figure 28.5 DFG/DPG Input Signals Rev.3.00 Jan. 10, 2007 page 618 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.3 28.3.1 Reference Signal Generators Overview The reference signal generators consist of REF30 signal generator and CREF signal generator, and they create the reference signals (REF30 and CREF signals) used in phase comparison, etc. The REF30 signal is used to control the phase of the drum and capstan. The CREF signal is used if the reference signal to control the phase of the capstan cannot be shared with the REF30 signal in REC mode. Each signal generator consists of a 16-bit counter which has the servo clock s/2 (or s/4) as its clock source, a reference period register and a comparator. The value set in the reference period register should be 1/2 of the desired reference signal period. 28.3.2 Block Diagram Figure 28.6 shows the block diagram of the REF30 signal generator. Figure 28.7 shows that of the CREF signal generator. Rev.3.00 Jan. 10, 2007 page 619 of 1038 REJ09B0328-0300 Internal bus R/W FDS OD/EV Edge detection , PB Counter (16 bit) Mask PBREC Field VD detection signal Video FF VST VEG W R/W W W W Section 28 Servo Circuits RCS REF30 counter register (16 bit) s/2 Edge detection Clear Toggle Rev.3.00 Jan. 10, 2007 page 620 of 1038 REJ09B0328-0300 REF30P Match External frequency signal (EXTTRG) REF30 ASM REC/PB V noise detection signal REX Dummy read W W Internal bus R/W W W TBC * VNA CVS s/4 Comparator (16 bit) Reference period register 1 (16 bit) Figure 28.6 REF30 Signal Generator Reference period buffer 1 (16 bit) s = fosc/2 Note: * The TBC bit is available only in the H8S/2194C Group. Section 28 Servo Circuits QS Counter clear s/2 PB(ASM) REC DVCFG2 R Counter (16 bit) s/4 Clear Comparator (16 bit) Match Toggle Edge detection CREF Reference period register 2 (16 bit) RCS W Reference period buffer 2 (16 bit) Dummy read CRD W W Internal bus s = fosc/2 Figure 28.7 Block Diagram of CREF Signal Generator 28.3.3 Register Configuration Table 28.4 shows the register configuration of the reference signal generators. Table 28.4 Register Configuration Name Reference period mode register Reference period register 1 Reference period register 2 REF30 counter register Reference period mode register 2 Abbrev. RFM RFD CRF RFC RFM2 R/W W W W R/W R/W Size Byte Word Word Word Byte Initial Value Address H'00 H'FFFF H'FFFF H'0000 H'FE H'FD096 H'FD090 H'FD092 H'FD094 H'FD097 Rev.3.00 Jan. 10, 2007 page 621 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.3.4 Register Descriptions (1) Reference Period Mode Register (RFM) Bit : Initial value : R/W : 7 RCS 0 W 6 VNA 0 W 5 CVS 0 W 4 REX 0 W 3 CRD 0 W 2 OD/EV 0 W 1 VST 0 W 0 VEG 0 W RFM is an 8-bit write-only register which determines the operational state of the reference signal generators. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. RFM is accessible by byte access only. If accessed by a word, its operation is not assured. Bit 7Clock Source Selection Bit (RCS): Selects the clock source supplied to the counter. (s = fosc/2) Bit 7 RCS 0 1 Description s/2 s/4 (Initial value) Bit 6Mode Selection Bit (VNA): Selects whether the transition to free-run operation when the REF30 signals are being generated in sync with the VD signals in REC mode is controlled automatically by the V noise detection signal, which has been detected by the sync signal detection circuit, or is controlled manually by software. Bit 6 VNA 0 1 Description Manual mode Auto mode (Initial value) Rev.3.00 Jan. 10, 2007 page 622 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 5Manual Selection Bit (CVS): Selects whether the REF30 signals are generated in sync with VD or operated free-run in manual mode (VNA = 0). (No selection is reflected in PB mode, except in TBC mode.) Bit 5 CVS 0 1 Description Sync with VD Free-run operation (Initial value) Bit 4External Signals Sync Selection Bit (REX): Selects whether the REF30 signals are generated in sync with VD or in free-run or in sync with the external signals. (Valid in both PB and REC modes.) Bit 4 REX 0 1 Description VD signals or free-run Sync with external signals (Initial value) Bit 3DVCFG2 Sync Selection Bit (CRD): Selects whether the reset timing in the CREF signals generation is immediately after switching from PB (ASM) mode to REC mode or is in sync with the DVCFG2 signals immediately after the switching. Bit 3 CRD 0 1 Description On switching modes In sync with DVCFG2 signals (Initial value) Bit 2ODD/EVEN Edge Switching Selection Bit (OD/EV): Selects whether REF30P signals are generated by ODD of the field signals or EVEN when in REC mode. Bit 2 OD/EV 0 1 Description Generated at the rising edge (EVEN) of the field signals Generated at the falling edge (ODD) of the field signals (Initial value) Rev.3.00 Jan. 10, 2007 page 623 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 1Video FF Counter Set (VST): Selects whether the REF30 counter register value is set on or off by the Video FF signal when the drum phase is in FIX on in PB mode. Bit 1 VST 0 1 Description Counter set off by Video FF signal Counter set on by Video FF signal (Initial value) Bit 0Video FF Edge Selection Bit (VEG): Selects the edge at which the REF30 counter is set (VST = 1) by the Video FF signal. Bit 0 VEG 0 1 Description Set at the rising edge of Video FF signal Set at the falling edge of Video FF signal (Initial value) (2) Reference Period Register 1 (RFD) Bit : 15 1 W 14 1 W 13 1 W 12 1 W 11 1 W 10 1 W 9 1 W 8 1 W 7 1 W 6 1 W 5 1 W 4 1 W 3 1 W 2 1 W 1 1 W 0 1 W REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 Initial value : R/W : The reference period register 1 (RFD) is a buffer register which generates the reference signals for playback (REF30), VD compensation for recording and the reference signals for free-running. It is a 16-bit write-only register accessible by a word only. If a read is attempted, an undetermined value is read out. The value set in RFD should be 1/2 of the desired reference signal period. Care is required when VD is unstable, such as when the field is weak (Synchronization with VD cannot be acquired if a value less than 1/2 is set when in REC). When data is written in RFD, it is stored in the buffer once, and then fetched into RFD by a match signal of the comparator. (The data which generates the reference signal is updated from time to time by the match signal.) An enforced write, such as initial setting, etc., should be done by a dummy read of RFD. If a byte-write in RFD is attempted, no operation is assured. RFD is initialized to H'FFFF by a reset, stand-by, or module stop. Use bit 7 (ASM) and bit 6 (REC/PB) in the CTL mode register (CTLM) in the CTL circuit to switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR) to switch between REF30 and CREF for capstan phase control. Rev.3.00 Jan. 10, 2007 page 624 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) Reference Period Register 2 (CRF) Bit : Initial value : R/W : 15 1 W 14 1 W 13 1 W 12 1 W 11 1 W 10 1 W 9 1 W 8 1 W 7 1 W 6 1 W 5 1 W 4 1 W 3 1 W 2 1 W 1 1 W 0 1 W CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0 The reference period register 2 (CRF) is a 16-bit write-only buffer register which generates the reference signals to control the capstan phase (CREF). CRF is accessibly by a word only. If a read is attempted, an undetermined value is read out. The value set in CRF should be 1/2 of the desired reference signal period. When data is written in CRF, it is stored in the buffer once, and then fetched into CRF by a match signal of the comparator. (The data which generates the reference signal is updated from time to time by the match signal.) An enforced write, such as initial setting, etc., should be done by a dummy read of CRF. If a byte-write in CRF is attempted, no operation is assured. CRF is initialized to H'FFFF by a reset, stand-by, or module stop. Use bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR) to switch between REF30 and CREF for capstan phase control. (See section 28.9, Capstan Phase Error Detector) (4) REF30 Counter Register (RFC) Bit : Initial value : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The REF30 counter register (RFC) is a register which determines the initial value of the free-run counter when it generates REF30 signals when in playback. When data is written in RFC, its value is written in the counter by a match signal of the comparator. If bit 1 (VST) in RFM is set to 1, the counter is set by the Video FF signal when the drum phase is in FIX ON. The counter setting by the Video FF signal should be done by setting RFM's bit 1 (VST) and bit 0 (VEG). Don't set the RFC value at a value greater than 1/2 of the reference period register 1 (RFD). RFC is a read/write register. If a read is attempted, the value of the counter is read out. If a byteaccess is attempted, no operation is assured. RFC is initialized to H'0000 by a reset, stand-by, or module stop. Rev.3.00 Jan. 10, 2007 page 625 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (5) Reference Period Mode Register 2 (RFM2) Bit : 7 (TBC) 6 -- 5 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 FDS 0 R/W Initial value : 1 1 1 -- -- (R/W)* R/W : Note: * Writable only in the H8S/2194C Group. RFM2 is an 8-bit read/write register which determines the operational state of the reference signal generators. Bits 6 to 1 are reserved. If a read is attempted, an undetermined value is read out. It is initialized to H'FE by a reset, stand-by or module stop. RFM2 is a byte access-only register; if accessed by a word, no operation is assured. Bit 7TBC Selection Bit (TBC): Selects whether the reference signals are generated by VD or in free-run in PB mode. Bit 7 TBC 0 1 Description Reference signals are generated by VD (This function is effective only in the H8S/2194C Group) Reference signals are generated in free-run (Initial value) Bits 6 to 1Reserved: No write is valid. If a read is attempted, an undetermined value is read out. Bit 0Field Selection Bit (FDS): Determines whether selection between ODD or EVEN is made for the field signals when PB mode was switched over to REC mode, or these signals are synchronized with VD signals within phase error of 90 immediately after the switching over. Bit 0 FDS 0 1 Description Generated by the VD signal of ODD or EVEN selected Generated by the VD signal within mode transition phase error of 90 (Initial value) Rev.3.00 Jan. 10, 2007 page 626 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.3.5 Description of Operation (1) Operation of REF30 Signal Generators The REF30 signal generators generate the reference signals required to control the phase of the drum and capstan. To generate REF30 signals, set the half-period value to the reference period register 1 (RFD) corresponding to the 50% duty cycle. When in playback, REF30 signals are generated by operating REF30 signal generator in free-run. The generator has the external signal synchronization function built-in, and if bit 4 (REX) of the reference period mode register (RFM) is set to 1, it generates REF30 signals from external signals (EXTTRG). In record mode, the reference signals are generated from the VD signal generated in the sync signal detection circuit. Any VD drop-out caused by weak field intensity, etc., is compensated by a set value of RFD. To cope with the VD noises, the generator performs automatically the VD masking for a time period about 75% of the RFD setting after REF30 signal was changed due to VD. In record mode, the generation of the reference signals either by VD or free-run operation can be controlled automatically or by software, using the V noise detection signal detected in the sync signal detection circuit. Select which is used by setting bit 6 (VNA) or 5 (CVS) of RFM. The phase of the toggle output of the REF30 signal is cleared to L level when the signal mode transits from PB to REC (ASM). Also the frame servo function can be set, allowing to control the phase of REF30 signals with the field signal detected in the sync signal detection circuit. Use bit 2 (OD/EV) of RFM for such control. See section 28.13.5(2), CTL Mode Register (CTLM), as for switching over between PB, ASM and REC. (2) Operation of the Mask Circuit The REF30 signal generators have a toggle mask circuit and counter mask (counter set signal mask) circuit built-in. Each mask circuit masks irregular VD signals which may occur when the VD signal is unstable because of weak field intensity, etc., in record mode. The toggle mask and counter mask circuits mask the VD automatically for about 75% of double the time period set in the reference period register 1 (RFD) after a VD signal was detected (see figure 28.9). If a VD signal dropped out and V was compensated, the toggle mask circuit begins masking. The counter mask circuit does not do so for about 25% of the time period. If a VD signal was detected during such time period, it does masking for about 75% of the time period. If not detected, it does for the same time period after V was compensated (see figures 28.10 and 28.11). Rev.3.00 Jan. 10, 2007 page 627 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) Timing of the REF30 Signal Generation Figures 28.8, 28.9, 28.10, 28.11, and 28.12 show the timing of the generation of REF30 and REF30P signals. Counter set Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) REF30 Counter set Counter set REF30P Figure 28.8 REF30 Signals in Playback Mode Rev.3.00 Jan. 10, 2007 page 628 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Field signal VD Selected VD (OD/EV = 0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (clear signal mask) Masking period Masking period About 75% REF30 REF30P HSW Drum phase counter Sampling T Sampling Sampling Figure 28.9 Generation of Reference Signal in Record Mode (Normal Operation) Rev.3.00 Jan. 10, 2007 page 629 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Field signal VD Selected VD (OD/EV = 0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Cleared Cleared Cleared Drop-out of V Masking period About 75% Counter mask (clear signal mask) Masking period About 75% About 75% About 75% About 25% REF30 REF30P HSW Drum phase counter Sampling T Sampling Sampling Figure 28.10 Generation of Reference Signal in Record Mode (V Dropped Out) Rev.3.00 Jan. 10, 2007 page 630 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Field signal Dislocation of V VD Selected VD (OD/EV = 0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Cleared Cleared Cleared Masking period About 75% Counter mask (clear signal mask) Masking period About 75% About 75% About 75% REF30 REF30P HSW Drum phase counter Sampling T Sampling Sampling Figure 28.11 Generation of Reference Signal in Record Mode (V DIslocated) Rev.3.00 Jan. 10, 2007 page 631 of 1038 REJ09B0328-0300 Section 28 Servo Circuits External sync signal Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Reset REF30 Cleared REF30P Figure 28.12 Generation of REF30 Signal by External Sync Signal (4) CREF Signal Generator The CREF signal generator generates a CREF signal which is the reference signal to control the phase of the capstan. To generate CREF signals, set the half-period value to the reference period register 2 (CRF). If the set value matches the counter value, a toggle waveform is generated corresponding to the 50% duty cycle, and a one-shot pulse signal is output at the rising edge of the waveform. The counter of the CREF signal generator is initialized to H'0000 and the phase of the toggle is cleared to L level at the mode transition of PB (ASM) to REC. The timing of clearing is selectable between immediately after the transition from PB (ASM) to REC and the timing of DVCFG2 after the transition. Use bit 3 (CRD) of the reference period mode register (RFM) for the selection. In the capstan phase error detection circuit, either the REF30 signal or CREF signal can be selected for the reference signal. Use either of them according to the use of the system. Use the CREF signal to control the phase of the capstan at a period which is different from the period used to control the phase of the drum. As for the switching between REF30 and CREF in the capstan phase control, see section 28.9.4 (3), Capstan Phase Error Detection Control Register (CPGCR). Rev.3.00 Jan. 10, 2007 page 632 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (5) Timing Chart of the CREF Signal Generation Figures 28.13, 28.14, and 28.15 show the generation of the CREF signal. Cleared Value set in reference period register 2 (CRF) Counter Cleared Cleared Toggle signal CREF Figure 28.13 Generation of CREF Signal Rev.3.00 Jan. 10, 2007 page 633 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Cleared Value set in reference period register 2 (CRF) Counter Cleared Cleared REC/PB Toggle signal Time period when CRF is set CREF PB(ASM) REC Figure 28.14 CREF Signal when PB Is Switched to REC (when CRD Bit = 0) Rev.3.00 Jan. 10, 2007 page 634 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Cleared Value set in reference period register 2 (CRF) Counter Cleared Cleared REC/PB DVCFG2 Toggle signal Time period when CRF is set CREF PB(ASM) REC Figure 28.15 CREF Signal when PB Is Switched to REC (when CRD Bit = 1) Rev.3.00 Jan. 10, 2007 page 635 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Figures 28.16 and 28.17 show REF30 (REF30P) when PB is switched to REC. PB Field signal VD (except in PB) Selected VD* (OD/EV = 0) REC/PB Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (Clear signal mask) Masking period Masking period About 75% Cleared Cleared Cleared Cleared Cleared REC(ASM) REF30 REF30P Note: * When in the field discrimination mode Figure 28.16 Generation of the Reference Signal when PB Is Switched to REC (1) Rev.3.00 Jan. 10, 2007 page 636 of 1038 REJ09B0328-0300 Section 28 Servo Circuits PB Field signal VD (except in PB) Selected VD (OD/EV = 0) REC/PB Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (Clear signal mask) Masking period Masking period About 50% Cleared REC(ASM) Cleared Cleared Cleared REF30 REF30P Figure 28.17 Generation of the Reference Signal when PB Is Switched to REC (2) Rev.3.00 Jan. 10, 2007 page 637 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Figures 28.18, 28.19, 28.20, and 28.21 show REF30 (REF30P) when PB is switched to REC (where FDS bit = 1). PB REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (Clear signal mask) Masking period REC(ASM) Cleared Cleared Cleared Masking period REF30 REF30P FDS bit = 1 Figure 28.18 Generation of the Reference Signal when PB Is Switched to REC where RFD Bit Is 1 (1) Rev.3.00 Jan. 10, 2007 page 638 of 1038 REJ09B0328-0300 Section 28 Servo Circuits PB REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (Clear signal mask) Masking period REC(ASM) Masking period 25% 25% 25% REF30 REF30P FDS bit = 1 Figure 28.19 Generation of the Reference Signal when PB Is Switched to REC where RFD Bit Is 1 (when VD Signal Is Not Detected) (2) Rev.3.00 Jan. 10, 2007 page 639 of 1038 REJ09B0328-0300 Section 28 Servo Circuits PB REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (Clear signal mask) Masking period REC(ASM) Cleared Cleared Masking period Max. 25% REF30 REF30P FDS bit = 1 Figure 28.20 Generation of the Reference Signal when PB Is Switched to REC where RFD Bit Is 1 (3) Rev.3.00 Jan. 10, 2007 page 640 of 1038 REJ09B0328-0300 Section 28 Servo Circuits PB REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Counter mask (Clear signal mask) Masking period REC(ASM) Cleared Cleared Masking period Max. 25% REF30 REF30P FDS bit = 1 Figure 28.21 Generation of the Reference Signal when PB Is Switched to REC where RFD Bit Is 1 (4) Rev.3.00 Jan. 10, 2007 page 641 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.4 28.4.1 HSW (Head-Switch) Timing Generator Overview The HSW timing generator consists of one 5-bit counter and one 16-bit counter, matching circuit, and two 31-bit 10-stage FIFOs. The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the timing to reset the 16-bit timer for each field. The matching circuit compares the timing data in the most significant 16 bits of FIFO with the 16-bit timer, and controls the output of pattern data set in the least significant 15 bits of FIFO. The 16-bit timer is a timer clocked by a s/4 clock source, and can be used as a PPG (Programmable Pattern Generator) as well as a free-running counter (FRC). If used as a free-running counter, it is cleared by overflow (FRCOVF) of the Prescaler unit. Accordingly, two free-running counter operate in sync. 28.4.2 Block Diagram Figure 28.22 shows a block diagram of the HSW timing generator. Rev.3.00 Jan. 10, 2007 page 642 of 1038 REJ09B0328-0300 Internal bus R * HSM1 HSM2 LOP SOFG OFG * FTPRA FIFO timing pattern register 1 FIFO output pattern register 1 R/W R/W R R/W R/W R/W R/W R * FPDRA WW W W W * FPDRB W FIFO output pattern register 2 * HSLP FLA,B EMPA,B OVWA,B CLRA,B * FTPRB FIFO timing pattern register 2 EDG HSW loop stage number setting register 16 bits 15 bits 16 bits 15 bits FIFO2 (31 bits x 10 stages) Control circuit FIFO 1 (31 bits x 10 stages) 16 bits * DFCRB DFG reference register 2 DFG reference register 1 15 bits * DFCRA FIFO output selector & output buffer P77 to 70 (PPG output) Comparator (5 bits) Comparator (5 bits) Compare circuit (16 bits) STRIG ADTRG Vpulse Mlevel NHSW HSW IRRHSW1 * DFCTR NCDFG Cleared Edge detector Counter (5 bits) VideoFF , FRCOVF CLK * DFCRA CCLR FGR20FF FRT * HSM2 * DFCRA CKSL s/8 s/4 R W R/W R/W W Internal bus Cleared Timer counter (16 bits) Capture IRRHSW2 AudioFF * HSM2 FTCTR (16 bits) VFF/NFF * HSM2 ISEL1 * DFCRA ISEL2 Figure 28.22 Composition of the HSW Timing Generator R VD PB R/W R/W W Section 28 Servo Circuits Rev.3.00 Jan. 10, 2007 page 643 of 1038 REJ09B0328-0300 DPG Section 28 Servo Circuits 28.4.3 Composition The HSW timing generator is composed of the elements shown in table 28.5. Table 28.5 Composition of the HSW Timing Generator Element HSW mode register 1 (HSM1) HSW mode register 2 (HSM2) HSW loop stage number setting register (HSLP) FIFO output pattern register 1 (FPDRA) FIFO output pattern register 2 (FPDRB) FIFO timing pattern register 1 (FTPRA) FIFO timing pattern register 2 (FTPRB) DFG reference register 1 (DFCRA) DFG reference register 2 (DFCRB) FIFO timer capture register (FTCTR) DFG reference count register (DFCTR) FIFO control circuit DFG count compare circuit (x2) 16-bit timer counter 31-bit x 20 stage FIFO 31-bit FIFO data buffer 16-bit compare circuit Function Confirmation/determination of this circuits' operating status Confirmation/determination of this circuits' operating status Setting of number of loop stages in loop mode Output pattern data register of FIFO1 Output pattern data register of FIFO2 Output timing register of FIFO1 Output timing register of FIFO2 Setting of reference DFG edge for FIFO1 Setting of reference DFG edge for FIFO2 Capture register of timer counter DFG edge count Controls FIFO status Detection of match between DFCR and DFG counters 16-bit free-run timer counter First In First Out data buffer Data storing buffer for the first stage of FIFO Detection of match between timer counter and FIFO data buffer FPDRA and FPDRB are intermediate buffers; an FTPRA and FTPRB write results in simultaneous writing of all 31 bits to the FIFO. The FIFO has two 31-bit x 10-stage data buffers, its operating status being controlled by HSM1 and HSM2. Data is stored in the 31-bit data buffer. The values of FTPRA, FTPRB and the timer counter are compared, and if they match, the 15-bit pattern data is output to each function. AudioFF, VideoFF and PPG (P70 to P77) are pin outputs, ADTRG is the A/D converter hardware start signal, Vpulse and Mlevel signals are the signals to generate the additional V pulses, and HSW and NHSW signals are the same with VideoFF signals used for the phase control of the drum. In free-run mode (when FRT bit of HSM2 = 1), the 16-bit Rev.3.00 Jan. 10, 2007 page 644 of 1038 REJ09B0328-0300 Section 28 Servo Circuits timer counter is initialized when the prescaler unit overflows, or by a signal indicating a match between DFCRA, DFCRB and the DFG counter in DFG reference mode. 28.4.4 Register Configuration Table 28.6 shows the register configuration of the HSW timing generator. Table 28.6 Register Configuration Name HSW mode register 1 HSW mode register 2 HSW loop stage number setting register FIFO output pattern register 1 FIFO timing pattern register 1* FIFO output pattern register 2 FIFO timing pattern register 2 DFG reference register 1* DFG reference register 2 FIFO timer capture register* DFG reference count register* Note: * Abbrev. HSM1 HSM2 HSLP FPDRA FTPRA FPDRB FTPRB DFCRA DFCRB FTCTR DFCTR R/W R/W R/W R/W W W W W W W R R Size Byte Byte Byte Word Word Word Word Byte Byte Word Byte Initial Value H'30 H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'0000 H'E0 Address H'FD060 H'FD061 H'FD062 H'FD064 H'FD066 H'FD068 H'FD06A H'FD06C H'FD06D H'FD066 H'FD06C FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same addresses. 28.4.5 Register Descriptions (1) HSW Mode Register 1 (HSM1) Bit : 7 FLB 6 FLA 5 EMPB 1 R 4 EMPA 1 R 3 OVWB 0 R/(W)* 2 OVWA 0 R/(W)* 1 CLRB 0 R/W 0 CLRA 0 R/W Initial value : 0 0 R/W : R R Note: * Only 0 can be written HSM1 is a register which confirms and determines the operational state of the HSW timing generator. HSM1 is an 8-bit register. Bits 7 to 4 are read-only bits, and write is disabled. All the other bits accept both read and write. It is initialized to H'30 by a reset or stand-by. Rev.3.00 Jan. 10, 2007 page 645 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 7FIFO2 Full Flag (FLB): When the FLB bit is 1, it indicates that the timing pattern data and the output pattern data of FIFO2 are full. If a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the OVWB flag (bit 3) is set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write again. Bit 7 FLB 0 1 Description FIFO2 is not full, and can accept data input FIFO2 is full (Initial value) Bit 6FIFO1 Full Flag (FLA): When the FLA bit is 1, it indicates that the timing pattern data and the output pattern data of FIFO1 are full. If a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the OVWA flag (bit 2) is set to 1, and the write data is lost. Wait until space becomes available in the FIFO1, then write again. Bit 6 FLA 0 1 Description FIFO1 is not full, and can accept data input FIFO1 is full (Initial value) Bit 5FIFO2 Empty Flag (EMPB): Indicates that FIFO2 has no data, or that all the data has been output in single mode. Bit 5 EMPB 0 1 Description FIFO2 contains data FIFO2 contains no data (Initial value) Bit 4FIFO1 Empty Flag (EMPA): Indicates that FIFO1 has no data, or that all the data has been output in single mode. Bit 4 EMPA 0 1 Description FIFO1 contains data FIFO1 contains no data (Initial value) Rev.3.00 Jan. 10, 2007 page 646 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 3FIFO2 Overwrite Flag (OVWB): If a write is attempted when the timing pattern data and the output pattern data of FIFO2 are full (FLB bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWB flag is set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write again. Write 0 to clear the OVWB flag, because it is not cleared automatically. Bit 3 OVWB 0 1 Description Normal operation (Initial value) Indicates that a write in FIFO2 was attempted when FIFO2 was full. Clear this flag by 0 writing Bit 2FIFO1 Overwrite Flag (OVWA): If a write is attempted when the timing pattern data and the output pattern data of FIFO1 are full (FLA bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWA flag is set to 1, and the write data is lost. Wait until space becomes available in the FIFO1, then write again. Write 0 to clear the OVWA flag, because it is not cleared automatically. Bit 2 OVWA 0 1 Description Normal operation (Initial value) Indicates that a write in FIFO1 was attempted when FIFO1 was full. Clear this flag by 0 writing Bit 1FIFO2 Pointer Clear (CLRB): Clears the FIFO2 write position pointer. After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect. Bit 1 CLRB 0 1 Description Normal operation Clears the FIFO2 pointer (Initial value) Rev.3.00 Jan. 10, 2007 page 647 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 0FIFO1 Pointer Clear (CLRA): Clears the FIFO1 write position pointer. After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect. Bit 0 CLRA 0 1 Description Normal operation Clears the FIFO1 pointer (Initial value) (2) HSW Mode Register 2 (HSM2) Bit : Initial value : R/W : 7 FRT 0 R/W 6 FGR20FF 0 R 5 LOP 0 R/W 4 EDG 0 R/W 3 ISEL1 0 R/W 2 SOFG 0 R/W 1 OFG 0 R 0 VFF/NFF 0 W HSM2 is a register which confirms and determines the operational state of the HSW timing generator. HSM2 is an 8-bit register. Bits 6 and 1 are read-only bits, and write is disabled. Bit 0 is a writeonly bit, and if a read is attempted, an undetermined value is read out. All the other bits accept both read and write. It is initialized to H'00 by a reset or stand-by. Bit 7Free-Run Bit (FRT): Selects whether timing is matched to the DPG counter and timer, or to free-running counter. Bit 7 FRT 0 1 Description 5-bit DFG counter + 16-bit timer counter 16-bit FRC (Initial value) Bit 6FRG2 Clear Stop Bit (FGR2OFF): Nullifies the clearing of the counter by the DFG reference register 2. The FIFO group, including both FIFO1 and FIFO2, is available. Bit 6 FGR2OFF 0 1 Description Validates the clearing of the 16-bit timer counter by DFG reference register 2 (Initial value) Nullifies the clearing of the 16-bit timer counter by DFG reference register 2 Rev.3.00 Jan. 10, 2007 page 648 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 5Mode Selection Bit (LOP): Selects the output mode of FIFO. If the loop mode is selected, LOB3 to LOB0 bits and LOA3 to LOA0 bits become valid. If the LOP bit is rewritten, the pointer which counts the writing position of FIFO is cleared. In this case, the ultimate output date is kept. Bit 5 LOP 0 1 Description Single mode Loop mode (Initial value) Bit 4DFG Edge Selection Bit (EDG): Selects the edge by which to count DFG. Bit 4 EDG 0 1 Description Counts by the rising edge of DFG Counts by the falling edge of DFG (Initial value) Bit 3Interrupt Selection Bit (ISEL1): Selects the factor which causes an interrupt. (IRRHSW1) Bit 3 ISEL1 0 1 Description Generates an interrupt request by the rising edge of the STRIG signal of FIFO (Initial value) Generates an interrupt request by the matching signal of FIFO Rev.3.00 Jan. 10, 2007 page 649 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 2FIFO Output Group Selection Bit (SOFG): Selects whether 20 stages of FIFO1 + FIFO2 or only 10 stages of FIFO1 are used. If 20-stage output mode is used in single mode, data write in FIFO1 and FIFO2 is required. Monitor the output FIFO group flag (OFG) and control it by software. Output all the data of FIFO2 after all the data of FIFO1 was output. Repeat this step again. If 10-stage output mode is used, the data of FIFO2 is not reflected. Rewriting the SOFG bit 0 1 0 initializes the control signal of the FIFO output stage to the FIFO1 side. Bit 2 SOFG 0 1 Description 20-stage output of FIFO1 + FIFO2 10-stage output of FIFO1 only (Initial value) Bit 1Output FIFO Group Flag (OFG): Indicates the FIFO group which is outputting. Bit 1 OFG 0 1 Description Pattern is being output by FIFO1 Pattern is being output by FIFO2 (Initial value) Bit 0Output Switching Bit between VideoFF and NarrowFF (VFF/NFF): Switches the signal output to the VideoFF pin. Bit 0 VFF/NFF 0 1 Description VideoFF output NarrowFF output (Initial value) Rev.3.00 Jan. 10, 2007 page 650 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) HSW Loop Stage Number Setting Register (HSLP) Bit : 7 LOB3 Initial value : R/W : * R/W 6 LOB2 * R/W 5 LOB1 * R/W 4 LOB0 * R/W 3 LOA3 * R/W 2 LOA2 * R/W 1 LOA1 * R/W 0 LOA0 * R/W Note: * Undetermined HSLP sets the number of the loop stages when the HSW timing generator is in loop mode. It is valid if bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number of FIFO2 stages. Bits 3 to 0 set the number of FIFO1 stages. HSLP is an 8-bit read/write register. It is not initialized by a reset, stand-by or module stop, accordingly be sure to set the number of the stages when the loop mode is used. Rev.3.00 Jan. 10, 2007 page 651 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 7 to 4FIFO2 Stage Number Setting Bits (LOB3 to LOB0): Set the number of FIFO2's stages in loop mode. They are valid only if the loop mode is set (LOP bit of HSM2 is 1). HSM2 Bit 5 LOP 0 1 HSLP Bit 7 LOB3 * 0 Bit 6 LOB2 * 0 Bit 5 LOB1 * 0 Bit 4 LOB0 * 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Legend: * Don't care. 0 1 Description Single mode Only 0th stage of FIFO2 is output 0th and 1st stages of FIFO2 are output 0th to 2nd stages of FIFO2 are output 0th to 3rd stages of FIFO2 are output 0th to 4th stages of FIFO2 are output 0th to 5th stages of FIFO2 are output 0th to 6th stages of FIFO2 are output 0th to 7th stages of FIFO2 are output 0th to 8th stages of FIFO2 are output 0th to 9th stages of FIFO2 are output Setting prohibited (Initial value) Rev.3.00 Jan. 10, 2007 page 652 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 3 to 0FIFO1 Stage Number Setting Bits (LOA3 to LOA0): Set the number of FIFO1's stages in loop mode. They are valid only if the loop mode is set (LOP bit of HSM2 is 1). HSM2 Bit 5 LOP 0 1 HSLP Bit 3 LOA3 * 0 Bit 2 LOA2 * 0 Bit 1 LOA1 * 0 Bit 0 LOA0 * 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Legend: * Don't care. 0 1 Description Single mode Only 0th stage of FIFO1 is output 0th and 1st stages of FIFO1 are output 0th to 2nd stages of FIFO1 are output 0th to 3rd stages of FIFO1 are output 0th to 4th stages of FIFO1 are output 0th to 5th stages of FIFO1 are output 0th to 6th stages of FIFO1 are output 0th to 7th stages of FIFO1 are output 0th to 8th stages of FIFO1 are output 0th to 9th stages of FIFO1 are output Setting prohibited (Initial value) Rev.3.00 Jan. 10, 2007 page 653 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (4) FIFO Output Pattern Register 1 (FPDRA) Bit : Initial value : R/W : Bit : Initial value : R/W : 15 -- 1 -- 7 PPGA7 * W 14 ADTRGA * W 6 PPGA6 * W 12 13 STRIGA NarrowFFA * W 5 PPGA5 * W * W 4 PPGA4 * W 11 VFFA * W 3 PPGA3 * W 10 AFFA * W 2 PPGA2 * W 9 VpulseA * W 1 PPGA1 * W 8 MlevelA * W 0 PPGA0 * W Note: * Undetermined FPDRA is a buffer register for the output pattern register of FIFO1. When the timing pattern is written in FTPRA the output pattern data written in FPDRA is written at the same time to the position pointed by the buffer pointer of FIFO1. Be sure to write the output pattern data in FPDRA before writing it in FTPRA. FPDRA is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Bit 15Reserved: It cannot be written in or read out. Bit 14A/D Trigger A Bit (ADTRGA): A signal for starting the A/D converter hardware. Bit 13S-TRIGA Bit (STRIGA): A signal for generating an interrupt by pattern data. When STRIGA is selected by ISEL, pattern data changes from 0 to 1, and thus generates an interrupt. Bit 12NarrowFFA Bit (NarrowFFA): Controls the Narrow Video Head. Bit 11VideoFFA Bit (VFFA): Controls the Video Head. Bit 10AudioFFA Bit (AFFA): Controls the Audio Head. Bit 9VpulseA Bit (VpulseA): Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information. Bit 8MlevelA Bit (MlevelA): Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information. Bits 7 to 0PPG Output Signal A Bits (PPGA7 to PPGA0): Used for timing control output of port 7 (PPG). Rev.3.00 Jan. 10, 2007 page 654 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (5) FIFO Output Pattern Register 2 (FPDRB) Bit : Initial value : R/W : Bit : Initial value : R/W : 15 -- 1 -- 14 ADTRGB * W 6 PPGB6 * W 13 12 STRIGB NarrowFFB * W 5 PPGB5 * W * W 4 PPGB4 * W 11 VFFB * W 3 PPGB3 * W 10 AFFB * W 2 PPGB2 * W 9 VpulseB * W 1 PPGB1 * W 8 MlevelB * W 0 PPGB0 * W 7 PPGB7 * W Note: * Undetermined FPDRB is a buffer register for the output pattern register of FIFO2. When the timing pattern is written in FTPRB the output pattern data written in FPDRB is written at the same time to the position pointed by the buffer pointer of FIFO2. Be sure to write the output pattern data in FPDRB before writing it in FTPRB. FPDRB is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Bit 15Reserved: It cannot be written in or read out. Bit 14A/D Trigger B Bit (ADTRGB): A signal for starting the A/D converter hardware. Bit 13S-TRIGB Bit (STRIGB): A signal for generating an interrupt by pattern data. When STRIGB is selected by ISEL, pattern data changes from 0 to 1, and thus generates an interrupt. Bit 12NarrowFFB Bit (NarrowFFB): Controls the Narrow Video Head. Bit 11VideoFFB Bit (VFFB): Controls the Video Head. Bit 10AudioFFB Bit (AFFB): Controls the Audio Head. Bit 9VpulseB Bit (VpulseB): Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information. Bit 8MlevelB Bit (MlevelB): Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information. Bits 7 to 0PPG Output Signal B Bits (PPGB7 to PPGB0): Used for timing control output of port 7 (PPG). Rev.3.00 Jan. 10, 2007 page 655 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (6) FIFO Timing Pattern Register 1 (FTPRA) Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Note: * Undetermined FTPRA is a register to write the timing pattern data of FIFO1. The timing data written in FTPRA is written at the same time to the position pointed by the buffer pointer of FIFO1 together with the buffer data of FPDRA. FTPRA is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Note: Its address is shared with the FIFO timer capture register (FTCTR). Accordingly, the value of FTCTR is read out if a read is attempted. (7) FIFO Timing Pattern Register 2 (FTPRB) Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8 FTPRB7 FTPRB6 FTPRB5 FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Note: * Undetermined FTPRB is a register to write the timing pattern data of FIFO2. The timing data written in FTPRB is written at the same time to the position pointed by the buffer pointer of FIFO2 together with the buffer data of FPDRB. FTPRB is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Rev.3.00 Jan. 10, 2007 page 656 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (8) DFG Reference Register 1 (DFCRA) Bit : Initial value : R/W : 7 ISEL2 6 CCLR 0 W 5 CKSL 0 W 4 DFCRA4 * W 3 DFCRA3 * W 2 DFCRA2 * W 1 DFCRA1 * W 0 DFCRA0 * W 0 W Note: * Undetermined DFCRA is a register which determines the operation of the HSW timing generator as well as the starting point of the timing of FIFO1. DFCRA is an 8-bit write-only register. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Note: Its address is shared with the DFG reference counter register (DFCTR). Accordingly, the value of DFCTR is read out in the low-order five bits if a read is attempted. Bit 7Interrupt Selection Bit (ISEL2): Selects the factor which causes an interrupt. (IRRHSW2) Bit 7 ISEL2 0 1 Description Generates an interrupt request by the clear signal of the 16-bit timer counter (Initial value) Generates an interrupt request by the VD signal in PB mode Bit 6DFG Counter Clear Bit (CCLR): Enforces clearing of the 5-bit counter which counts DFG by software. Writing 1 returns 0 immediately. Writing 0 causes no effect on operation. Bit 6 CCLR 0 1 Description Normal operation Clears the 5-bit DFG counter (Initial value) Bit 516-Bit Timer Counter Clock Source Selection Bit (CKSL): Selects the clock source of the 16-bit timer counter. Bit 5 CKSL 0 1 Description s/4 s/8 Rev.3.00 Jan. 10, 2007 page 657 of 1038 REJ09B0328-0300 (Initial value) Section 28 Servo Circuits Bits 4 to 0FIFO1 Output Timing Setting Bits (DFCRA4 to DFCRA0): Determine the starting point of the timing of FIFO1. The initial value is undetermined. Be sure to set a value after a reset or stand-by. It is valid only if bit 7 (FRT bit) of HSM2 is 0. (9) DFG Reference Register 2 (DFCRB) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 DFCRB4 * W 3 DFCRB3 * W 2 1 DFCRB2 DFCRB1 * W * W 0 DFCRB0 * W Note: * Undetermined DFCRB is a register which determines the starting point of the timing of FIFO2. DFCRB is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. Bits 7 to 5 are reserved. No write is valid. If a read is attempted, 1 is read out. It is not initialized by a reset or stand-by, accordingly be sure to write data before use. Bits 4 to 0FIFO2 Output Timing Setting Bits (DFCRB4 to DFCRB0): Determine the starting of the FIFO2 output. The initial values are undetermined, accordingly be sure to write values in the bits after a reset or stand-by. It is valid only if bit 7 (FRT bit) of HSM2 is 0. (10) FIFO Timer Capture Register (FTCTR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0 Initial value : R/W : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R FTCTR is a register to display the count of the 16-bit timer counter. FTCTR is a 16-bit read-only register. It stores the counter value if a VD signal was detected in PB mode. Only a word access is accepted. If a byte access is attempted, resulting operation is not assured. It is initialized to H'0000 by a reset or stand-by. Note: Its address is shared with the FIFO timing pattern register 1 (FTPRA). Accordingly, if a write is attempted, the value is written in FTPRA. Rev.3.00 Jan. 10, 2007 page 658 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (11) DFG Reference Count Register (DFCTR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 DFCTR4 0 R 3 DFCTR3 0 R 2 DFCTR2 0 R 1 DFCTR1 0 R 0 DFCTR0 0 R DFCTR is a register to count the DFG pulses. DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved. If a read is attempted, 1 is read out. It is initialized to H'E0 by a reset or stand-by. Note: Its address is shared with the DFG reference register 1 (DFCRA). Accordingly, if a write is attempted, the value is written in DFCRA. Bits 4 to 0DFG Pulse Count Bits (DFCTR4 to DFCTR0): Count the number of pulses of DFG. Rev.3.00 Jan. 10, 2007 page 659 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.4.6 Description of Operation 1. 5-Bit DFG counter The 5-bit DFG counter takes counts by the edges of DFG selected by the EDG bit of HSW mode register 2. The 5-bit DFG counter is cleared by the DPG's rise or when 1 was written in the CCLR bit of DFG reference register 1. 2. 16-Bit Timer Counter DFG reference mode or free-run mode can be selected for the 16-bit timer counter. DFG Reference Mode DFG reference mode is based on the DFG signal. When the DFG reference registers 1 and 2 and the 5-bit DFG counter value match, the 16-bit timer counter is initialized, and that point becomes the starting of the FIFO output. In DFG reference mode, the FGR2OFF bit of the HSW mode register 2 can be used to select between using only the DFG reference register 1 to set the starting of the FIFO output or using both DFG reference registers 1 and 2 to set the starting of the FIFO1 and FIFO2 outputs, respectively. When using only the DFG reference register 1 to set the starting, continuous values should be set as the timing patterns for FIFO1 and FIFO2. Free-Run Mode Free-run mode is to operate together with the prescaler unit. An overflow of the 18-bit freerunning counter in the prescaler unit initializes the 16-bit timer counter, and that point becomes the starting of the FIFO output. 3. Matching Circuit The matching circuit compares the timing pattern value of FIFO with the 16-bit timer counter value, and if they match, it generates a trigger signal to output the pattern data for the FIFO's next stage. 4. FIFO FIFO generates the head-switching signal used in the VCR and the pattern data necessary for servo control. Data is set in FIFO by the FIFO timing pattern registers 1 and 2 and the FIFO output pattern registers 1 and 2. FIFO has two modes, i.e. single mode and loop mode. In either mode, output of 20 stages of FIFO1 + FIFO2 or output of only 10 stages of FIFO1 can be selected. Single Mode In single mode, the output pattern data is output each time the timing data matches. The data, once output, is lost, and the internal pointer is decremented by 1. When the last data was output, it stops operation until data is written again. When it is used in the 20-stage output mode, writing in FIFO1 and FIFO2 has to be controlled by software. Rev.3.00 Jan. 10, 2007 page 660 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Loop Mode In loop mode, the output pattern cycles repeatedly from stage 0 through the final stage selected in the HSW loop number setting register. As in single mode, the output pattern data is output each time the timing data matches. In loop mode, the FIFO data is retained. When loop mode is active, data can be rewritten for each FIFO group. After confirming with the OFG bit of the HSW mode register 2 which FIFO group is outputting, clear the FIFO group which is not outputting and write data for the entire FIFO group. Writing has to be completed before the rewritten FIFO group starts operation. Partial rewriting in the FIFO is not possible, because the write pointer is outside the loop stages. Figures 28.23 and 28.24 show examples of the timing waveform and its operation of the HSW timing generator. Rev.3.00 Jan. 10, 2007 page 661 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 10 11 0 1 2 tA1 8 tA3 tB1 9 Figure 28.23 Example of Timing Waveform of HSW (when DFG Is 12 Shots) Rev.3.00 Jan. 10, 2007 page 662 of 1038 REJ09B0328-0300 Example of setting: DFCRA=H'02, DFCRB=H'08, HSLP=H'21, DFG falling edge 4 5 6 7 0 1 2 tA1 tA2 3 Clear A Clear B DPG V.FF A.FF DFG Section 28 Servo Circuits Internal bus W W FPDRA W W FPDRB FTPRA tA0 PA9 FTPRB tB0 PB9 FIFO1 tA5 tA4 tA3 tA2 tA1 PA4 PA3 PA2 PA1 PA0 tB5 tB4 tB3 tB2 tB1 PB4 PB3 PB2 PB1 PB0 FIFO2 Output select buffer Output select buffer Comparator s/4 Timer counter Output pattern data Figure 28.24 Example of Operation of the HSW Timing Generator Rev.3.00 Jan. 10, 2007 page 663 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (1) Example of operation in single mode (20 stages of FIFO used) (a) Set to single mode (LOP = 0) (b) Write the output pattern data (PA0) to FPDRA. (c) Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This initializes the output pattern data to PA0. (d) Repeat the steps in the same way, until PA1, PA2, etc., are set. (e) Write the output pattern data (PB0) to FPDRB. (f) Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This initializes the output pattern data to PB0. (g) Repeat these steps in the same way, until PB1, PB2, etc., are set. From (c), the pattern data of PA0 is output. If tA1 matches with the timer counter, the pattern data of PA1 is output. If tA2 matches with the timer counter, the pattern data of PA2 is output. . . . Rev.3.00 Jan. 10, 2007 page 664 of 1038 REJ09B0328-0300 Section 28 Servo Circuits After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of FIFO2 is output. After the pattern data is output, the pointer is decremented by 1. Care is required, however, because matching of tA0 is not detected until data is written in FIFO2. Matching of tB0 also is not detected until data is written in FIFO1 again. (2) Example of operation in loop mode (a) Set the number of loop stages in the HSLP register (e.g. HSLP = H'44) (b) Write the output pattern data (PA0) to FPDRA. (c) Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This initializes the output pattern data to PA0. (d) Repeat the steps in the same way, until PA1, PA2, etc., are set. (e) Write the output pattern data (PB0) to FPDRB. (f) Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This initializes the output pattern data to PB0. (g) Repeat the steps in the same way, until PB1, PB2, etc., are set. From (c), the pattern data PA0 is output. If tA1 matches the timer counter, the pattern data PA1 is output. If tA2 matches the timer counter, the pattern data PA2 is output. . . . If tA4 matches the timer counter, the pattern data PA4 is output. If tA5 matches the timer counter, the pattern data PB0 is output. If tB1 matches the timer counter, the pattern data PB1 is output. . . . If tB4 matches the timer counter, the pattern data PB4 is output. If tB5 matches the timer counter, the pattern data PA0 is output. . . . Rev.3.00 Jan. 10, 2007 page 665 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.4.7 Interrupt The HSW timing generator generates an interrupt under the following conditions. (1) IRRHSW1 occurred when pattern data was written (OVWA, OVWB = 1) and FIFO was full (FULL). (2) IRRHSW1 occurred when matching was detected and the STRIG bit of FIFO was 1. (3) IRRHSW1 occurred when the values of the 16-bit timer counter and 16-bit timing pattern register matched. (4) IRRHSW2 occurred when the 16-bit timer counter was cleared. (5) IRRHSW2 occurred when a VD signal (capture signal of the timer capture register) was received in PB mode. (2) and (3), as well as (4) and (5), are switched over by ISEL1 and ISEL2. Rev.3.00 Jan. 10, 2007 page 666 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.4.8 Cautions (1) When both the 5-bit DFG counter and 16-bit timer counter are operating, the latter is not cleared if input of DPG and DFG signals is stopped. This leads to free-running of the 16-bit timer counter, and periodical detection of matching by the 16-bit timer counter. In such a case, the period of the output from the HSW timing generator is independent from DPG or DFG. (2) Specify the mode setting bit (LOP) of the HSW mode register 2 (HSM2) immediately before writing the FIFO data. (3) Input the rising edge of DPG and DFG count edge at different timings. If the same timing was input, counting up of DFG and clearing of the 5-bit DFG counter occurs simultaneously. In this case, the latter will take precedence. This leads to the 5-bit DFG counter's lag by 1. Figure 28.25 shows the input timing of DPG and DFG. (4) If stop of the drum system is required when FIFO output is being used in the 20-stage output mode, rewrite the SOFG bit of HSM2 register 0 1 0 by software, and initialize the FIFO output stage to the FIFO1 side without fail. Also clear and rewrite the data of FIFO1 and FIFO2. I TP * FG I > (1 state) DPG DFG TP * FG Note: When the DFG counter takes count at the rising edges of DFG Figure 28.25 Input Timing of DPG and DFG Rev.3.00 Jan. 10, 2007 page 667 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.5 28.5.1 Four-Head High-Speed Switching Circuit for Special Playback Overview This four-head high-speed switching circuit generates a color rotary signal (C.Rotary) and headamplifier switching signal (H.Amp SW) for use in four-head special playback. A pre-amplifier output comparison result signal is input from the COMP pin. The signal output at the C.Rotary pin is a Chroma signal processing control signal. The signal output at the H.Amp SW pin is a pre-amplifier output select signal. To reduce the width of noise bars, the C.Rotary and H.Amp SW signals are synchronized to the horizontal sync signal (OSCH). OSCH is made by adding supplemented H, which has been separated from the Csync signal in the sync signal detector circuit. For more details of OSCH, see section 28.15, Sync Signal Detector. If the C.Rotary, H.Amp SW or COMP pin does not require this circuit to configure a VCR system, it can be used as an I/O port. 28.5.2 Block Diagram Figure 28.26 shows the block diagram of this circuit. Rev.3.00 Jan. 10, 2007 page 668 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Internal bus W * CHCR SIG3 to 0 W CRH W * CHCR HAH OSCH (Synchronization) Synchronization control C.Rotary Decoding circuit COMP H.Amp SW Narrow.FF Video.FF V/N * CHCR HSWPOL * CHCR RTP0 W Internal bus W Figure 28.26 Four-Head High-Speed Switching Circuit for Special Playback 28.5.3 Pin Configuration Table 28.7 summarizes the pin configuration of the high-speed switching circuit used in four-head special playback. They can also be used as I/O ports when not in use. See section 28.2, Servo Port. Table 28.7 Pin Configuration Name Compare input pin Color rotary signal output pin Head-amplifier switching pin Abbrev. COMP C.Rotary H.Amp SW I/O Input Output Output Function Input of pre-amplifier output result signal Output of chroma processing control signal Output of pre-amplifier output select signal Rev.3.00 Jan. 10, 2007 page 669 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.5.4 Register Description (1) Register Configuration Table 28.8 shows the register configuration of the high-speed switching circuit used in four-head special playback. Table 28.8 Register Configuration Name Special playback control register Abbrev. CHCR R/W W Size Byte Initial Value Address H'00 H'FD06E (2) Special Playback Control Register (CHCR) Bit : Initial value : R/W : 7 V/N 0 W 6 HSWPOL 0 W 5 CRH 0 W 4 HAH 0 W 3 SIG3 0 W 2 SIG2 0 W 1 SIG1 0 W 0 SIG0 0 W The special playback control register (CHCR) is an 8-bit write-only register. It cannot be read. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. Bit 7HSW Signal Selection Bit (V/N): Selects the HSW signal to be used at special playback. Bit 7 V/N 0 1 Description Video FF signal output Narrow FF signal output (Initial value) Bit 6COMP Polarity Selection Bit (HSWPOL): Selects the polarity of the COMP signal. Bit 6 HSWPOL 0 1 Description Positive Negative (Initial value) Rev.3.00 Jan. 10, 2007 page 670 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 5C.Rotary Synchronization Control Bit (CRH): Synchronizes the C.Rotary signal with the OSCH signal. Bit 5 CRH 0 1 Description Synchronous Asynchronous (Initial value) Bit 4H.Amp SW Synchronization Control Bit (HAH): Synchronizes the H.Amp SW signal with the OSCH signal. Bit 4 HAH 0 1 Description Synchronous Asynchronous (Initial value) Bits 3 to 0Signal Control Bits (SIG3 to SIG0): These bits, combined with the state of the COMP input pin, control the outputs at the C.Rotary and H.Amp SW pins. Bit 3 SIG3 0 Bit 2 SIG2 0 1 Bit 1 SIG1 * 0 Bit 0 SIG0 * 0 1 1 0 1 1 0 0 1 1 Legend: * Don't care. 0 1 * Output Pins C.Rotary L HSW HSW L H H.Amp SW L L H HSW HSW (Initial value) HSW EX-OR COMP COMP HSW EX-NOR COMP COMP HSW E-OR RTP0 RTP0 HSW EX-NOR RTP0 RTP0 Rev.3.00 Jan. 10, 2007 page 671 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.6 28.6.1 Drum Speed Error Detector Overview Drum speed error control operates so as to hold the drum at a constant revolution speed by measuring the period of the DFG signal. A digital counter detects the speed deviation from a preset value. The speed error data is processed and added to phase error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase of the drum. The DFG input signal is reshaped into a square wave by a reshaping circuit, and sent to the speed error detector as the DFG signal. The speed error detector uses the system clock to measure the period of the DFG signal, and detects the deviation from a preset data value. The preset data is the value that would result from measuring the DFG signal period with the clock signal if the drum motor was running at the correct speed. The error detector operates by latching a counter value when it detects an edge of the DFG signal. The latched count provides 16 bits of speed error data for the digital filter to operate on. The digital filter processes and adds the speed error data to phase error data from the drum phase control system, then sends the result to the pulse-width modulator as drum error data. 28.6.2 Block Diagram Figure 28.27 shows a block diagram of the drum speed error detector. Rev.3.00 Jan. 10, 2007 page 672 of 1038 REJ09B0328-0300 Internal bus W * DFVCR * DFRVCR DFRCS1, 0 DFOVF S F/F QR * DFRUDR Lock range data 2 (16 bits) R/W W (R)/W R * DFVCR DF-R/UNR R/W * DFVCR DFCS1, 0 Preset R F/F QS Counter (16 bits) OVF Rock 1 up * DFPR Preset data (16 bits) IRRDRM1 s s/2 s/4 s/8 S R Clear Lock range detector Rock 2 up Q F/F , * DFER Error data (16 bits) Lock range data 1 (16 bits) Error data limitter control circuit * FGCR DRF DFESS * DFUCR * DFVCR DFEFON Latch NCDFG * DFRLOR Edge detector Lock counter (2 bits) IRRDRM2 UDF ADDFGN Error data (16 bits) To DFU * DFVCR DPCNT To DROCKON DFU W R/W R/W R/W Internal bus Figure 28.27 Block Diagram of the Drum Speed Error Detector W R/W Section 28 Servo Circuits Rev.3.00 Jan. 10, 2007 page 673 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.6.3 Register Configuration Table 28.9 shows the register configuration of the drum speed error detector. Table 28.9 Register Configuration Name Abbrev. R/W W R/W W W R/W Size Word Word Word Word Byte Initial Value H'0000 H'0000 H'7FFF H'8000 H'00 Address H'FD030 H'FD032 H'FD034 H'FD036 H'FD038 Specified DFG speed presetDFPR data register DFG speed error data register DFG lock UPPER data register DFG lock LOWER data register DFER DFRUDR DFRLDR Drum speed error detection DFVCR control register Rev.3.00 Jan. 10, 2007 page 674 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.6.4 Register Descriptions (1) Specified DFG Speed Preset Data Register (DFPR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The specified DFG speed preset data is set in DFPR. When the data is written, a 16-bit preset data is sent to the preset circuit. The preset data is referenced to H'8000*, and can be calculated from the following equation. Specified DFG speed preset data = H'8000 - ( s/n - 2) DFG frequency s: Servo clock frequency (fosc/2) in Hz DFG frequency: In Hz The constant 2 is the presetting interval (see figure 28.28). s/n Clock source of selected counter DFPR is a 16-bit write-only register, and is accessible by word access only. Byte access gives unassured results. Reads are disabled. DFPR is initialized to H'0000 by a reset, and in standby mode and module stop mode. Note: * The preset data value is calculated so that the counter will reach H'8000 when the error is zero. When the counter value is latched as error data in the DFG speed error data register (DFER), however, it is converted to a value referenced to H'0000. Rev.3.00 Jan. 10, 2007 page 675 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) DFG Speed Error Data Register (DFER) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. DFER is a register that stores 16-bit DFG speed error data. When the drum motor speed is correct, the data latched in DFER is H'0000. Negative data will be latched if the speed is too fast, and positive data if the speed is too slow. The DFER value is sent to the digital filter either automatically or by software. DFER is a 16-bit readable/writable register. DFER is accessible by word access only. Byte access gives unassured results. DFER is initialized to H'0000 by a reset, and in standby mode and module stop mode. Refer to the note in 28.6.4 (1), Specified DFG Speed Preset Data Register (DFPR). (3) DFG Lock UPPER Data Register (DFRUDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W DFRUDR is a register used to set the lock range on the UPPER side when drum speed lock is detected, and to set the limit value on the UPPER side when the limiter function is in use. Set a signed data to DFRUDR (bit 15 is a sign-setting bit). When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by DFRCS 1 and 0 bits of the DFVCR register counts down. If the set value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG speed error data is beyond the DFRUDR value while the limiter function is in use, the DFRUDR value can be used as the data for computation by the digital filter. DFRUDR is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF by a reset, stand-by or module-stop. Rev.3.00 Jan. 10, 2007 page 676 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (4) DFG Lock LOWER Data Register (DFRLDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W DFRLDR is a register used to set the lock range on the LOWER side when drum speed lock is detected, and to set the limit value on LOWER side when the limiter function is in use. Set a signed data to DFRLDR (bit 15 is a sign-setting bit). When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by the DFRCS1 and DFRCS0 bits of the DFVCR register counts down. If the set value of DFRCS1 and DFRCS0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG speed error data is under the DFRLDR value when the limiter function is in use, the DFRLDR value can be used as the data for computation by the digital filter. DFRLDR is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop. (5) Drum Speed Error Detection Control Register (DFVCR) Bit : Initial value : R/W : 7 DFCS1 0 R/W 6 DFCS0 0 R/W 5 DFOVF 0 R/(W)*1 4 3 DFRFON DF-R/UNR 0 R/W 0 R 2 DPCNT 0 R/W 1 DFRCS1 0 (R)*2/W 0 DFRCS0 0 (R)*2/W Notes: 1. Only 0 can be written. 2. If read-accessed, the counter value is read out. DFVCR controls the operation of drum speed error detection. DFVCR is an 8-bit readable/writable register. Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop. Rev.3.00 Jan. 10, 2007 page 677 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 7 and 6Clock Source Selection Bits (DFCS1, DFCS0): DFCS1 and DFCS0 select the clock to be supplied to the counter. (s = fosc/2) Bit 7 DFCS1 0 Bit 6 DFCS0 0 1 1 0 1 Description s s/2 s/4 s/8 (Initial value) Bit 5Counter Overflow Flag (DFOVF): The DFOVF flag indicates the overflow of the 16-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 DFOVF 0 1 Description Normal state Indicates that overflow has occurred in the counter (Initial value) Bit 4Error Data Limit Function Selection Bit (DFRFON): Makes the error data limit function valid. (Limit values are the values set in the lock range data register (DFRUDR, DFRLDR)). Bit 4 DFRFON 0 1 Description Limit function off Limit function on (Initial value) Bit 3Drum Lock Flag (DF-R/UNR): Sets a flag if an underflow occurred in the drum lock counter. Bit 3 DF-R/UNR 0 1 Description Indicates that the drum speed system is not locked Indicates that the drum speed system is locked (Initial value) Rev.3.00 Jan. 10, 2007 page 678 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 2Drum Phase System Filter Computation Automatic Start Bit (DPCNT): Sets on the filter computation of the phase system if an underflow occurred in the drum lock counter. Bit 2 DPCNT 0 1 Description Does not perform the filter computation by detection of the drum lock (Initial value) Sets on the filter computation of the phase system when drum lock is detected Bits 1 and 0Drum Lock Counter Setting Bits (DFRCS1, DFRCS0): Set the number of times where drum lock has been determined (DFG has been detected in the range set by the lock range data register). It sets the drum lock flag if it detected the set number of times of occurrence of drum lock. If an NCDFG signal is detected outside the lock range after data is written in DFRCS1 and 0, data is stored in the lock counter. Note: If DFRCS1 or DFRCS0 is read-accessed, the counter value is read out. If bit 3 (drum lock flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed system is locked. The drum look counter stops until lock is released after underflow. Bit 1 DFRCS1 0 Bit 0 DFRCS0 0 1 1 0 1 Description Underflow after lock was detected once Underflow after lock was detected twice Underflow after lock was detected three times Underflow after lock was detected four times (Initial value) Rev.3.00 Jan. 10, 2007 page 679 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.6.5 Description of Operation The drum speed error detector detects the speed error based on the reference value set in the DFG specified speed preset register (DFPR). The reference value set in DFPR is preset in the counter by the NCDFG signal, and counts down by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of the NCDFG signal. See section 28.14.4, DFG Noise Removal Circuit. The error data detected is sent to the digital filter circuit. The error data is signed binaries. It takes a positive number (+) if the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it correct (revolving at the specified speed). Figure 28.28 shows an example of operation to detect the drum speed. Setting the Error Data Limit: A limit can be set to the error data sent to the digital filter circuit using the DFG lock data register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the lower limit in DFRLDR, and write 1 in the DFRFON bit. If the error data is beyond the limit range, the DFRLDR value is sent if a negative number is latched, or the DFRUDR value is sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting (DFRFON = 0) when you set the limit value. If the limit was set with the limit setting on (DFRFON = 1), result of computation is not assured. Lock Detection: If an error data was detected within the lock range set in the lock data register, the drum lock flag (DF-R/UNR) is set by the number of the times of occurrence of locking set by the DFRCS1 and DFRCS0 bits, and an interrupt is requested (IRRDRM2) at the same time. The number of the occurrence of locking (once to 4 times) can be specified when setting the flag. Use the DFRCS1 and DFRCS0 bits for this purpose. Also, if bit 5 (DPHA bit) of the drum system digital filter control register (DFIC) is 0 (phased system digital filter computation off) and the DPCNT bit is 1, turning on/off of the phase system digital filter computation can be controlled automatically by the status of lock detection. Drum System sSpeed Error Detection Counter: The drum system speed error detection counter stops the counter and sets the overflow flag (DFOVF) when the overflow occurred. At the same time, it generates an interrupt request (IRRDRM1). Clear DFOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. Interrupt Request: IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection counter. IRRDRM2 is generated by detection of lock (after the detection of the number of times of setting). Rev.3.00 Jan. 10, 2007 page 680 of 1038 REJ09B0328-0300 Section 28 Servo Circuits NCDFG signal Error data latch signal (DFG ) Preset data load Preset period (2 counts) Specified speed value Counter Preset value -value+value Latch data 0 (no error) Figure 28.28 Example of the Operation of the Drum Speed Error Detection (Selection of the RIsing Edge of DFG) Rev.3.00 Jan. 10, 2007 page 681 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.6.6 fH Correction in Trick Play Mode In trick play mode, the tape speed changes relative to the video head. This change alters the horizontal sync signal (fH), causing skew. To correct the skew, the drum motor speed must be shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync frequency. To shift the drum motor speed, software should modify the value written in the DFG preset data register in the speed error detector. This fH correction can be expressed in terms of the basic frequency fF of the drum as follows. fF = N0 xf N0 + H (1 - n) F0 Legend: n: H: N0: fF0: Speed multiplier (FWD = positive, REV = negative) H alignment (1.5 H in standard mode, 0.75 H in 2x mode, and 0.5 H in 3x mode for VHS and systems; 1 H for an 8-mm VCR) Standard H numbers within field Field frequency NTSC: N0 = 262.5, fF0 = 59.94 PAL: N0 = 312.5, fF0 = 50.00 Rev.3.00 Jan. 10, 2007 page 682 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.7 28.7.1 Drum Phase Error Detector Overview Drum phase control must start operating after the drum motor is brought to the correct revolution speed by the speed control system. Drum phase control works as follows in record and playback. Record: Phase is controlled so that the vertical blanking intervals of the recorded video signal will line up along the bottom edge of the tape. Playback: Phase is controlled so as to trace the recorded tracks accurately. A digital counter detects the phase deviation from a preset value. The phase error data is processed and added to speed error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the rotational phase and speed of the drum. The DPG signal from the drum motor is reshaped into a rectangular pulse waveform by a reshaping circuit, and sent to the phase error detector. The phase error detector compares the phase of the DPG pulse (tackle pulse), which contains video head phase information, with a reference signal. In the actual circuit, the comparison is carried out by comparing the head-switching (HSW) signal, which is delayed by a counter that is reset by DPG, with a reference signal value. The reference signal is the REF30 signal, which differs between record and playback as follows. Record: Vsync signal extracted from the video signal to be recorded (frame rate signal, actually 1/2 Vsync) Playback: 30 Hz or 25 Hz signal divided from the system clock 28.7.2 Block Diagram Figure 28.29 shows a block diagram of the drum phase error detector. Rev.3.00 Jan. 10, 2007 page 683 of 1038 REJ09B0328-0300 Internal bus R/W * DPGCR * DPPR1 Preset data Preset data * DPPR2 * DPGCR W W R/(W) DPCS1,0 (4 bits) MSB Preset DPOVF LSB Section 28 Servo Circuits (16 bits) Rev.3.00 Jan. 10, 2007 page 684 of 1038 REJ09B0328-0300 S F/F QR Counter (20 bits) s s/2 s/4 s/8 Sequence controller Latch REF30P OVF HSW (Video FF) , Edge detector IRRDRM3 NHSW (Narrow FF) * DPER1 * DPGCR * DPGCR * DFUCR N/V HSWES Error data (4 bits) MSB * DPER2 Error data (16 bits) DFEPS LSB Error data (20 bits) To DFU Figure 28.29 Block Diagram of Drum Phase Error Detector R/W R/W R/W Internal bus R/W R/W s = fosc/2 Section 28 Servo Circuits 28.7.3 Register Configuration Table 28.10 shows the register configuration of the drum phase error detector. Table 28.10 Register Configuration Name Drum phase preset data register 1 Drum phase preset data register 2 Drum phase error data register 1 Drum phase error data register 2 Abbrev. DPPR1 DPPR2 DPER1 DPER2 R/W W W R/W R/W R/W Size Byte Word Byte Word Byte Initial Value H'F0 H'0000 H'F0 H'0000 H'07 Address H'FD03C H'FD03A H'FD03D H'FD03E H'FD039 Drum phase error detection DPGCR control register Rev.3.00 Jan. 10, 2007 page 685 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.7.4 Register Descriptions (1) Drum Phase Preset Data Registers (DPPR1, DPPR2) DPPR1 Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 W 2 0 W 1 0 W 0 0 W DPPR2 Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The 20-bit preset data that defines the specified drum phase is set in DPPR1 and DPPR2. The 20 bits are weighted as follows. Bit 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB. When data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded into the preset circuit. Write to DPPR1 first, and DPPR2 next. The preset data is referenced to H'80000*, and can be calculated from the following equation. Target phase difference = (reference signal frequency/2) - 6.5 H Drum phase preset data = H'80000 - (s/n x target phase difference) s: s/n: Servo clock frequency in Hz (fosc/2) Clock source of selected counter DPPR2 is accessible by word access only. Byte access gives unassured results. Reads are disabled. DPPR1 and DPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. Note: * The preset data value is calculated so that the counter will reach H'80000 when the error value is zero. When the counter value is latched as error data in the drum phase error data registers (DPER1 and DPER2), however, it is converted to a value referenced to H'00000. Rev.3.00 Jan. 10, 2007 page 686 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Drum Phase Error Data Registers (DPER1, DPER2) DPER1 Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R*/W 2 0 R*/W 1 0 R*/W 0 0 R*/W DPER2 Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. DPER1 and DPER2 consist of a 20-bit DPG phase error data register. The 20 bits are weighted as follows. Bit 3 of DPER1 is the MSB, and bit 0 of DPER2 is the LSB. When the rotational phase is correct, the data H'00000 is latched. Negative data will be latched if the drum leads the correct phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the digital filter circuit. DPER1 and DPER2 are 20-bit readable/writable registers. When writing data to DPER1 and DPER2, write to DPER1 first, and then write to DPER2. DPER2 is accessible by word access only. Byte access gives unassured results. DPER1 and DPER2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. See the note on the drum phase preset data registers (DPPR1 and DPPR2) in section 28.7.4 (1), Drum Phase Present Data Register (DPPR1, DPPR2). (3) Drum Phase Error Detection Control Register (DPGCR) Bit : 7 DPCS1 6 DPCS0 5 DPOVF 0 R/(W)* 4 N/V 0 R/W 3 HSWES 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : 0 0 R/W R/W R/W : Note: * Only 0 can be written. DPGCR controls the operation of drum phase error detection. DPGCR is an 8-bit readable/writable register. Bits 2 to 0 are reserved, bit 5 accepts only read and 0 write. It is initialized to H'07 by a reset or stand-by. Rev.3.00 Jan. 10, 2007 page 687 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 7 and 6Clock Source Selection Bits (DPCS1, DPCS0): Select the clock supplied to the counter. (s = fosc/2) Bit 7 DPCS1 0 Bit 6 DPCS0 0 1 1 0 1 Description s s/2 s/3 s/4 (Initial value) Bit 5Counter Overflow Flag (DPOVF): The DPOVF flag indicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 DPOVF 0 1 Description Normal state Indicates that an overflow has occurred in the counter (Initial value) Bit 4Error Data Latch Signal Selection Bit (N/V): Selects the latch signal of error data. Bit 4 N/V 0 1 Description HSW (VideoFF) signal NHSW (NarrowFF) signal (Initial value) Bit 3Edge Selection Bit (HSWES): Selects the edge of the error data latch signal (HSW or NHSW). Bit 3 HSWES 0 1 Description Latches at the rising edge Latches at the falling edge (Initial value) Bits 2 to 0Reserved: No read or write is valid. Rev.3.00 Jan. 10, 2007 page 688 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.7.5 Description of Operation The drum phase error detector detects the phase error based on the reference value set in the drum phase preset data register 1 and 2 (DPPR1, DPPR2). The reference values set in DPPR1 and DPPR2 are preset in the counter by the REF30P signal, and counted up by the clock selected. The latch of the error data can be selected between the rising or falling edge of HSW (NHSW). The error data detected in the error data automatic transmission mode (DFEPS bit of DFUCR = 0) is sent to the digital filter circuit automatically. In software transmission mode (DFEPS bit of DFUCR = 1), the data written in DPER1 and DPER2 is sent to the digital filter circuit. The error data is signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the specified phase). Figures 28.30 and 28.31 show examples of operation to detect a drum phase error. Drum Phase Error Detection Counter: The drum phase error detection counter stops the counter when overflow or latch occurred. At the same time, it generates an interrupt request (IRRDRM3), setting the overflow flag (DPOVF) if overflow occurred. Clear DPOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. Interrupt Request: IRRDRM3 is generated by the HSW (NHSW) signal latch and the overflow of the error detection counter. REF30P HSW (NHSW)* Preset Counter Preset value Note: * Edge selectable Latch Preset Latch Preset value Figure 28.30 Drum Phase Control in Playback Mode (HSW Rising Edge Selected) Rev.3.00 Jan. 10, 2007 page 689 of 1038 REJ09B0328-0300 Section 28 Servo Circuits VD Reset REF30P Reset HSW (NHSW)* Preset Counter Preset value Preset Latch Preset value Latch Note: * Edge selectable Figure 28.31 Drum Phase Control in Record Mode (HSW RIsing Edge Selected) 28.7.6 Phase Comparison The phase comparison circuit takes measures of the difference of time between the reference signal and the comparing signal with a digital counter. The REF30 signal is used for the reference signal, and the HSW signal (VideoFF) or HHSW signal (NarrowFF) from the HSW timing generator is used for the comparing signal. In record mode, however, the phase of the REF30 signal is the same as that of the vertical sync signal (Vsync) because the reference signal generator (REF30 generator) is reset by the vertical sync signal (Vsync) in the video signals. The error detection counter performs the data latching operation at the rising or falling edge of the HSW signal. The digital filter circuit performs computation using this data as 20-bit phase error data. After processing and adding the phase error data and the speed error data from the drum speed control system, the digital filter circuit sends the data as the error data of the drum system to the PWM modulation circuit. Rev.3.00 Jan. 10, 2007 page 690 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.8 28.8.1 Capstan Speed Error Detector Overview Capstan speed control operates so as to hold the capstan motor at a constant revolution speed, by measuring the period of the CFG signal. A digital counter detects the speed deviation from a preset value. The speed error data is added to phase error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase of the capstan motor. The CFG input signal is downloaded by the comparator circuit, then reshaped into a square wave by a reshaping circuit, divided by the CFG divider, and sent to the speed error detector as the DVCFG signal. The speed error detector uses the system clock to measure the period of the DVCFG signal, and detects the deviation from a preset data value. The preset data is the value that would result from measuring the DVCFG signal period with the clock signal if the capstan motor was running at the correct speed. The error detector operates by latching a counter value when it detects an edge of the DVCFG signal. The latched count provides 16 bits of speed error data for the digital filter to operate on. The digital filter adds the speed error data to phase error data from the capstan phase control system, then sends the result to the pulse-width modulator as capstan error data. 28.8.2 Block Diagram Figure 28.32 shows a block diagram of the capstan speed error detector. Rev.3.00 Jan. 10, 2007 page 691 of 1038 REJ09B0328-0300 Internal bus W * CFPR * CFRUDR Lock range data 2 (16 bits) R/W * CFVCR * CFRVCR CFRCS1,0 CFOVF S F/F QR R/W W (R)/W R * CFVCR CF-R/UNR * CFVCR Preset data (16 bits) Preset Section 28 Servo Circuits CFCS1, 0 R F/F QS Counter (16 bits) OVF Lock 1 up Rev.3.00 Jan. 10, 2007 page 692 of 1038 REJ09B0328-0300 IRRCAP1 S R Clear Lock counter (2 bits) s s/2 s/4 s/8 Lock range detector Lock 2 up Latch Q F/F DVCFG * CFER Error data (16 bits) * CFRLDR Lock range data 1 (16 bits) IRRCAP2 UDF Error data (16 bits) To DFU * CFUCR CFESS * CFVCR CFRFON Error data limitter control circuit * CFVCR CPCNT CROCKON To DFU R/W R/W R/W Internal bus W R/W Figure 28.32 Block Diagram of Capstan Speed Error Detector Section 28 Servo Circuits 28.8.3 Register Configuration Table 28.11 shows the register configuration of the capstan speed error detector. Table 28.11 Register Configuration Name CFG speed preset data register CFG speed error data register CFG lock UPPER data register CFG lock LOWER data register Capstan speed error detection control register Abbrev. CFPR CFER CFRUDR CFRLDR CFVCR R/W W R/W W W R/W Size Word Word Word Word Byte Initial Value H'0000 H'0000 H'7FFF H'8000 H'00 Address H'FD050 H'FD052 H'FD054 H'FD056 H'FD058 28.8.4 Register Descriptions (1) CFG Speed Preset Data Register (CFPR) Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The 16-bit preset data that defines the specified CFG speed is set in CFPR. The preset data is referenced to H'8000*, and can be calculated from the following equation. CFG speed preset data = H'8000 - ( s/n DVCFG frequency - 2) s: Servo clock frequency in Hz (fOSC/2) DVCFG frequency: In Hz The constant 2 is the preset interval (see figure 28.33). s/n: Clock source of the selected counter Rev.3.00 Jan. 10, 2007 page 693 of 1038 REJ09B0328-0300 Section 28 Servo Circuits CFPR is a 16-bit write-only register. CFPR is accessible by word access only. Byte access gives unassured results. No read is valid. If a read is attempted, an undetermined value is read out. CFPR is initialized to H'0000 by a reset, stand-by or module stop. Note: * The preset data value is calculated so that the counter will reach H'8000 when the error is zero. When the counter value is latched as error data in the CFG speed error data register (CFER), however, it is converted to a value referenced to H'0000. (2) CFG Speed Error Data Register (CFER) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. CFER is a 16-bit data register. When the speed of the capstan motor is correct, the data latched in CFER is H'0000. Negative data will be latched if the speed is too fast, and positive data if the speed is too slow. The CFER value is sent to the digital filter either automatically or by software. CFER is a 16-bit readable/writable register. CFER is accessible by word access only. Byte access gives unassured results. CFER is initialized to H'0000 by a reset, and in module stop mode and standby mode. See the note on the CFG speed preset data register (CFPR) in section 28.8.4 (1), CFG Speed Present Data Register (CFPR). (3) CFG Lock UPPER Data Register (CFRUDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W CFRUDR is a register used to set the lock range on the UPPER side when capstan speed lock is detected, and to set the limit value on the UPPER side when the limiter function is in use. When lock is being detected, if the capstan speed is detected within the lock range, the lock counter which has been set by the CFRCS1 and CFRCS0 bits of the CFVCR register counts down. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of locking, the computation of the digital filter in the capstan phase system can be controlled automatically. Also, if the CFG speed error data is beyond the CFRUDR value when the limiter function is in use, the CFRUDR value can be used as the data for computation by the digital filter. CFRUDR is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. A read is invalid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF by a reset, stand-by or module-stop. Rev.3.00 Jan. 10, 2007 page 694 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (4) CFG Lock LOWER Data Register (CFRLDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W CFRLDR is a register used to set the lock range on the LOWER side when capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is in use. When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by the CFRCS1 and CFRCS0 bits of the CFVCR register counts down. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. Also, if the CFG speed error data is under the CFRLDR value when the limiter function is in use, the CFRLDR value can be used as the data for computation by the digital filter. CFRLDR is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop. (5) Capstan Speed Error Detection Control Register (CFVCR) Bit : 7 CFCS1 6 CFCS0 5 CFOVF 4 3 2 CFRFON CF-R/UNR CPCNT 0 R 0 R/W 1 CFRCS1 0 (R)*2/W 0 CFRCS0 0 (R)*2/W Initial value : 0 0 0 0 R/W : R/W R/(W)*1 R/W R/W Notes: 1. Only 0 can be written. 2. If read-accessed, the counter value is read out. CFVCR controls the operation of capstan speed error detection. CFVCR is an 8-bit readable/writable register. Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop. Bits 7 and 6Clock Source Selection Bits (CFCS1, CFCS0): CFCS1 and CFCS0 select the clock to be supplied to the counter. (s = fosc/2) Bit 7 CFCS1 0 Bit 6 CFCS0 0 1 1 0 1 Description s s/2 s/4 s/8 (Initial value) Rev.3.00 Jan. 10, 2007 page 695 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 5Counter Overflow Flag (CFOVF): The CFOVF flag indicates overflow of the 16-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 CFOVF 0 1 Description Normal state Indicates that an overflow has occurred in the counter (Initial value) Bit 4Error Data Limit Function Selection Bit (CFRFON): Makes the error data limit function valid. (Limit values are the values set in the lock range data register (CFRUDR, CFRLDR)). Bit 4 CFRFON 0 1 Description Limit function off Limit function on (Initial value) Bit 3Capstan Lock Flag (CF-R/UNR): Sets a flag if an underflow occurred in the capstan lock counter. Bit 3 CF-R/UNR 0 1 Description Indicates that the capstan speed system is not locked Indicates that the capstan speed system is locked (Initial value) Bit 2Capstan Phase System Filter Computation Automatic Start Bit (CPCNT): Sets on the filter computation of the phase system if an underflow occurred in the capstan lock counter. Bit 2 CPCNT 0 1 Description Does not perform the filter computation by detection of the capstan lock (Initial value) Set on the filter computation of the phase system when capstan lock is detected Rev.3.00 Jan. 10, 2007 page 696 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 1 and 0Capstan Lock Counter Setting Bits (CFRCS1, CFRCS0): Sets the number of times where drum lock has been determined (DVCFG has been detected in the range set by the lock range data register). It sets the capstan lock flag if it detected the set number of times of occurrence of capstan lock. If a DVCFG signal is detected outside the lock range after data is written in CFRCS1 and CFRCS0, data is stored in the lock counter. Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan lock flag) is 1 and the capstan lock counter's value is 3, it indicates that the capstan speed system is locked. The capstan look counter stops until lock is released after underflow. Bit 1 CFRCS1 0 Bit 0 CFRCS0 0 1 1 0 1 Description Underflow after lock was detected once Underflow after lock was detected twice Underflow after lock was detected three times Underflow after lock was detected four times (Initial value) 28.8.5 Description of Operation The capstan speed error detector detects the speed error based on the reference value set in the CFG speed preset register (CFPR). The reference value set in CFPR is preset in the counter by the DVCFG signal, and counts down by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of the DVCFG signal. See description of DVCFG control register (CDVC), in section 28.14.3, CFG Frequency Divider. The error data detected is sent to the digital filter circuit. The error data is signed binaries. It takes a positive number (+) if the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified speed). Figure 28.33 shows an example of operation to detect the capstan speed. Setting the Error Data Limit: A limit can be set to the error data sent to the digital filter circuit using the CFG lock data register (CFRUDR, CFRLDR). Set the upper limit of the error data in CFRUDR and the lower limit in CFRLDR, and write 1 in the CFRFON bit. If the error data is beyond the limit range, the CFRLDR value is sent if a negative number is latched, or the CFRUDR value is sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting (CFRFON = 0) when you set the limit value. If the limit was set with the limit setting on (CFRFON = 1), result of computation is not assured. Rev.3.00 Jan. 10, 2007 page 697 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Lock Detection: If error data was detected within the lock range set in the lock data register, the capstan lock flag (CF-R/UNR) is set by the number of the times of occurrence of locking set by the CFRCS1 and CFRCS0 bits, and an interrupt is requested (IRRCAP2) at the same time. The number of the occurrence of locking (once to 4 times) can be specified when setting the flag. Use the CFRCS1 and CFRCS0 bits for this purpose. Also, if bit 5 (CPHA bit) of the capstan system digital filter control register (CFIC) is 0 (phased system digital filter computation off) and the DPCNT bit is 1, turning on/off of the phase system digital filter computation can be controlled automatically by the status of lock detection. Capstan System sSpeed Error Detection Counter: The capstan system speed error detection counter stops the counter and sets the overflow flag (CFOVF) when overflow occurred. At the same time, it generates an interrupt request (IRRCAP1). Clear CFOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. Interrupt Request: IRRCAP1 is generated by the DVCFG signal latch and the overflow of the error detection counter. IRRCAP2 is generated by detection of lock (after the detection of the number of times of setting). Error data latch signal (DVCFG) Preset data load Preset period (2 counts) Specified speed value Counter -value +value Preset value Latch data 0 (no error) Figure 28.33 Example of the Operation of the Capstan Speed Error Detection Rev.3.00 Jan. 10, 2007 page 698 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.9 28.9.1 Capstan Phase Error Detector Overview The capstan phase control system is required to start operation after the capstan motor has arrived at the specified speed under the control of the speed control system. The capstan phase control system operates in the following way in record/playback mode. In record mode: Controls the tape running so that it may run at a specified speed together with the speed control system. In playback mode: Controls the tape running so that the recorded track may be traced correctly. Any error deviated from the reference phase is detected by the digital counter. This phase error data and the speed error data is processed and added by the digital filter circuit to control the PWM output. The phase and speed of the capstan, in turn, is controlled by this PWM output. The control signal of the capstan phase control in REC mode differs from that in PB mode. In REC mode, the control is performed by the DVCFG2 signal which is generated by dividing the frequencies of the reference signal (REF30P or CREF) and the CFG signal. In PB mode, it is performed by divided rising signal (DVCTL) of the reference signal (CAPREF30) and the playback control pulse (PB-CTL). The reference signal in record and playback modes are as follows. In record mode: 1/2 Vsync signal extracted from the video signal to be recorded In playback mode: Signal generated by dividing the PB-CTL signal (DVCTL) at its rising edge 28.9.2 Block Diagram Figure 28.34 shows the block diagram of the capstan phase error detector. Rev.3.00 Jan. 10, 2007 page 699 of 1038 REJ09B0328-0300 Internal bus R/W * CPGCR * CPPR1 Preset data R/W * CPGCR CPOVF W W R/(W) Section 28 Servo Circuits CR/RF CPCS1,0 (4 bits) MSB Preset * CPPR2 Preset data (16 bits) LSB CREF REF30P CAPREF30 S F/F QR Counter (20 bits) Rev.3.00 Jan. 10, 2007 page 700 of 1038 REJ09B0328-0300 Preset PB: X value + TRK value = CAPREF30 REC: REF30P or CREF Latch PB : DVCTL REC : DVCFG2E OVF Sequence controller Latch RECREF s s/2 s/4 s/8 DVCFG2 DVCTL IRRCAP3 * CPGCR R/P ASM * CTLM * CPER1 Error data (4 bits) MSB * DFUCR CFEPS LSB Error data (20 bits) To DFU SELCFG2 * CPER2 Error data (16 bits) Figure 28.34 Block Diagram of Capstan Phase Error Detector R/W Internal bus R/W R/W R/W R/W R/W s = fosc/2 Section 28 Servo Circuits 28.9.3 Register Configuration Table 28.12 shows the register configuration of the capstan phase error detector. Table 28.12 Register Configuration Name Abbrev. R/W W W R/W R/W R/W Size Byte Word Byte Word Byte Initial Value H'F0 H'0000 H'F0 H'0000 H'07 Address H'FD05C H'FD05A H'FD05D H'FD05E H'FD059 Capstan phase preset data CPPR1 register 1 Capstan phase preset data CPPR2 register 2 Capstan phase error data register 1 Capstan phase error data register 2 Capstan phase error detection control register CPER1 CPER2 CPGCR Rev.3.00 Jan. 10, 2007 page 701 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.9.4 Register Descriptions (1) Capstan Phase Preset Data Registers (CPPR1, CPPR2) CPPR1 Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 W 2 0 W 1 0 W 0 0 W CPPR2 Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The 20-bit preset data that defines the specified capstan phase is set in CPPR1 and CPPR2. The 20 bits are weighted as follows. Bit 3 of CPPR1 is the MSB. Bit 0 of CPPR2 is the LSB. When CPPR2 is written to, the 20-bit preset data, including CPPR1, is loaded into the preset circuit. Write to CPPR1 first, and CPPR2 next. The preset data is referenced to H'80000*, and can be calculated from the following equation. Target phase difference = Rreference signal frequency/2 Capstan phase preset data = H'80000 - (s/n x target phase difference) s: s/n: Servo clock frequency in Hz (fosc/2) Clock source of selected counter CPPR2 is accessible by word access only. Byte access gives unassured results. Reads are disabled. If read is attempted to CPPR1 or CPPR2, an undetermined value is read out. CPPR1 and CPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. Note: * The preset data value is calculated so that the counter will reach H'80000 when the error is zero. When the counter value is latched as error data in the capstan phase error data registers (CPER1 and CPER2), however, it is converted to a value referenced to H'00000. Rev.3.00 Jan. 10, 2007 page 702 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Capstan Phase Error Data Registers (CPER1, CPER2) Bit : Initial value : R/W : Bit : 15 7 -- 1 -- 14 13 6 -- 1 -- 12 11 5 -- 1 -- 10 9 4 -- 1 -- 8 3 0 R*/W 7 6 2 0 R*/W 5 4 1 0 R*/W 3 2 0 0 R*/W 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. CPER1 and CPER2 constitute a 20-bit capstan phase error data register. The 20 bits are weighted as follows. Bit 3 of CPER1 is the MSB. Bit 0 of CPER2 is the LSB. When the rotational phase is correct, the data H'00000 is latched. Negative data will be latched if the phase leads the correct phase, and positive data if it lags. Values in CPER1 and CPER 2 are transferred to the digital filter circuit. CPER1 and CPER are 20-bit readable/writable registers. When writing data to CPER1 and CPER2, write to CPER1 first, and then write to CPER2. CPER2 is accessible by word access only. Byte access gives unassured results. CPER1 and CPER2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. See the note on the capstan phase preset data registers (CPPR1 and CPPR2) in section 28.9.4 (1), Capstan Phase Present Data Registers (CPPR1, CPPR2). (3) Capstan Phase Error Detection Control Register (CPGCR) Bit : 7 CPCS1 6 CPCS0 5 CPOVF 0 R/(W)* 4 CR/RF 0 R/W 3 SELCFG2 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : 0 0 R/W R/W R/W : Note: * Only 0 can be written CPGCR controls the operation of capstan phase error detection. CPGCR is an 8-bit readable/writable register. Bits 2 to 0 are reserved, bit 5 accepts only read and 0 write. It is initialized to H'07 by a reset or stand-by. Rev.3.00 Jan. 10, 2007 page 703 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 7 and 6Clock Source Selection Bits (CPCS1, CPCS0): Select the clock supplied to the counter. (s = fosc/2) Bit 7 CPCS1 0 Bit 6 CPCS0 0 1 1 0 1 Description s s/2 s/4 s/8 (Initial value) Bit 5Counter Overflow Flag (CPOVF): CPOVF flag indicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 CPOVF 0 1 Description Normal state Indicates that an overflow has occurred in the counter (Initial value) Bit 4Preset Signal Selection Bit (CR/RF): Selects the preset signal. Bit 4 CR/RF 0 1 Description Presets REF30P signal Presets CREF signal (Initial value) Bit 3Preset and Latch Signal Selection Bit (SELCFG2): Selects the counter preset signal and the error data latch signal data in PB (ASM) mode. Bit 3 SELCFG2 0 1 Description Presets CAPREF30 signal; latches DVCTL signal Presets REF30P (CREF) signal; latches DVCFG2 signal (Initial value) Bits 2 to 0Reserved: No read or write is valid. Rev.3.00 Jan. 10, 2007 page 704 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.9.5 Description of Operation The capstan phase error detector detects the phase error based on the reference value set in the capstan specified phase preset data register 1 and 2 (CPPR1, CPPR2). The reference values set in CPPR1 and CPPR2 are preset in the counter by the REF30P (CREF) signal or CAPREF30 signal, and counted up by the clock selected. The latching of the error data is performed by DVCTL or DVCFG2. The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR = 0) is sent to the digital filter circuit automatically. In software transmission mode (CFEPS bit of DFUCR = 1), the data written in CPER1 and CPER2 is sent to the digital filter circuit. The error data is signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the specified phase). Figures 28.35 and 28.36 show examples of operation to detect a capstan phase error. Capstan Phase Error Detection Counter: The capstan phase error detection counter stops the counter when overflow or latch occurred. At the same time, it generates an interrupt request (IRRCAP3), setting the overflow flag (CPOVF) if overflow occurred. Clear CPOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. Interrupt Request: IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the overflow of the error detection counter. CAPREF30 PB-CTL DVCTL or DVCFG2 Preset Counter Latch Preset value Latch Preset Figure 28.35 Capstan Phase Control in Playback Mode Rev.3.00 Jan. 10, 2007 page 705 of 1038 REJ09B0328-0300 Section 28 Servo Circuits REF30P or CREF DVCFG2 Preset Counter Preset value Preset Latch Latch Figure 28.36 Capstan Phase Control in Record Mode Rev.3.00 Jan. 10, 2007 page 706 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.10 X-Value and Tracking Adjustment Circuit 28.10.1 Overview To maintain compatibility with other VCRs, an on-chip adjustment circuit adjusts the phase of the reference signal (internal reference signal (REF30) or external reference signal (EXCAP)) during playback. Because of manufacturing tolerances, the physical distance between the video head and control head (the X-value: 79.244 mm) may vary from set to set, so when a tape that was recorded on a different set is played back, the phase of the reference signal may need to be adjusted. The adjustment can be made by a register setting. The same setting can adjust the rotational phase of the capstan motor to maintain positional alignment (tracking alignment) of the video head with the recorded tracks in autotracking, or when tracks that were recorded with an EP head are traced by a wider head. These tracking adjustments can be made by acquisition of the envelope signal by the A/D converter. 28.10.2 Block Diagram The adjustment circuit consists of a 10-bit counter clocked by the servo clock (s or s/2), and two down-counters with load register. Individual setting of X-value adjustment can be made by the Xvalue data register (XDR) and tracking adjustment by the TRK data register (TRDR). The reference signal clears the 10-bit counter and sets the load register value in the down-counter with two load registers. After the adjusted reference signal is generated, clock supply stops and the circuit halts until the next reference signal is input. The REF30 signal can be divided (by 2 to 4) as necessary. Figure 28.37 shows a block diagram. Rev.3.00 Jan. 10, 2007 page 707 of 1038 REJ09B0328-0300 Internal bus W W * TRDR TRK value data register W W * XTCR * XTCR * XTCR (12 bits) AT/MU TRK/X Section 28 Servo Circuits XCS ASM Counter (10 bits) REC/PB Down counter s s /2 CAPREF30 (12 bits) Rev.3.00 Jan. 10, 2007 page 708 of 1038 REJ09B0328-0300 R QS Down counter REF30X (12 bits) R SQ EXCAP Edge selection REF30P Down counter (2 bits) CAPRF * XTCR EXC/REF X-value data register * XTCR (12 bits) W Internal bus W * XDR DVREF1, 0 Figure 28.37 Block Diagram of X-Value Adjustment Circuit W R*/W Notes: * When DVREF1 and DVREF0 are read, values in the down counter (2 bits) are read out. s = fosc/2 Section 28 Servo Circuits 28.10.3 Register Descriptions (1) Register Configuration Table 28.13 shows the register configuration of X-value adjustment and tracking adjustment circuits. Table 28.13 Register Configuration Name X-value and TRK-value control register X-value data register TRK-value data register Abbrev. XTCR XDR TRDR R/W R/W W W Size Byte Word Word Initial Value H'80 H'F000 H'F000 Address H'FD074 H'FD070 H'FD072 (2) X-value and TRK-value Control Register (XTCR) Bit : Initial value : R/W : 7 -- 1 -- 6 CAPRF 0 W 5 AT/MU 0 W 4 TRK/X 0 W 3 EXC/REF 0 W 2 XCS 0 W 1 DVREF1 0 R/W 0 DVREF0 0 R/W XTCR is an 8-bit register to determine the X-value and TRK-value adjustment circuits. Bits 6 to 2 are write-only bits. No read is valid. If a read is attempted, an undetermined value is read out. Bits 1 and 0 are readable/writable bits. XTCR accepts only a byte access. If a word access is attempted, operation is unassured. It is initialized to H'80 by a reset, stand-by or module stop. Bit 7Reserved: No write is valid. If a read is attempted, an undetermined value is read out. Bit 6External Sync Signal Edge Selection Bit (CAPRF): Selects the EXCAP edge when a selection is made to generate external sync signals. Bit 6 CAPRF 0 1 Description Signal generated at the rising edge of EXCAP Signal generated at both edges of EXCAP (Initial value) Rev.3.00 Jan. 10, 2007 page 709 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 5Capstan Phase Correction Auto/Manual Selection Bit (AT/MU): Selects whether the generation of the correction reference signal (CAPREF30) for capstan phase control is controlled automatically or manually depending on the status of the ASM and REC/PB bits of the CTL mode register. Bit 5 AT/MU 0 1 Description Manual mode Auto mode (Initial value) Bit 4Capstan Phase Correction Register Selection Bit (TRK/X): Determines the method to generate the CAPREF30 signal when the AT/MU bit is 0. Bit 4 TRK/X 0 1 Description Generates CAPREF30 only by the set value of XDR Generates CAPREF30 by the set values of XDR and TRDR (Initial value) Bit 3Reference Signal Selection Bit (EXC/REF): Selects the reference signal to generate the correction reference signal (CAPREF30). Bit 3 EXC/REF 0 1 Description Generates the signal based on REF30P Generates the signal based on the external reference signal (Initial value) Bit 2Clock Source Selection Bit (XCS): Selects the clock source to be supplied to the 10-bit counter. Bit 2 XCS 0 1 Description s s/2 (Initial value) Rev.3.00 Jan. 10, 2007 page 710 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 1 and 0REF30P Division Ratio Selection Bits (DVREF1, DVREF0): Select the division value of REF30P. If it is read-accessed, the counter value is read out. (The selected division value is set by the UDF of the counter.) Bit 1 DVREF1 0 Bit 0 DVREF0 0 1 1 0 1 Description Division in 1 Division in 2 Division in 3 Division in 4 (Initial value) (3) X-Value Data Register (XDR) Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The X-value data register (XDR) is a 16-bit write-only register. No read is valid. If a read is attempted, an undefined value is read out. XDR accepts only a word-access. If a byte access is attempted, operation is not assured. Set X-value correction data to XDR, except a value which is beyond the cycle of the CTL pulse. If AT/MU = 0, TRK/X = 0 was set, CAPREF30 can be generated only by the setting of XDR. Set an X-value and TRK correction value in PB mode, and an X-value in REC mode. It is initialized to H'F000 by a reset, stand-by or module stop. (4) TRK-Value Data Register (TRDR) Bit : 15 -- Initial value : 1 R/W : -- 14 -- 1 -- 13 -- 1 -- 12 11 10 9 8 7 6 5 4 3 2 1 0 -- TRD11 TRD10 TRD9 TRD8 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The TRK-value data register (TRDR) is a 16-bit write-only register. No read is valid. If a read is attempted, an undefined value is read out. TRDR accepts only a word-access. If a byte access is attempted, operation is not assured. Set a TRK-value correction data to TRDR, except a value which is beyond the cycle of the CTL pulse. It is initialized to H'F000 by a reset, stand-by or module stop. Rev.3.00 Jan. 10, 2007 page 711 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.11 Digital Filters 28.11.1 Overview The digital filters required in servo control make extensive use of multiply-accumulate operations on signed integers (error data) and coefficients. A filter computation circuit (digital filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to improve processing efficiency. Figure 28.38 shows a block diagram of the digital filter computation circuit configuration. The filter computation circuit includes a high-speed 24-bit x 16-bit multiplier-accumulator, an arithmetic buffer, and an I/O processor. The digital filter computations are carried out by the highspeed multiplier-accumulator. The arithmetic buffer stores coefficients and gain constants needed in the filter computations, which are referenced by the high-speed multiplier-accumulator. The I/O processor is activated by a frequency generator signal, and determines what operation is carried out. When activated, it reads the speed error and phase error from the speed and phase error detectors and sends them to the accumulator. When the filter computation is completed, the I/O processor reads the result from the accumulator and sends it to a 12-bit PWM. At this time, the accumulation result gain can be controlled. Rev.3.00 Jan. 10, 2007 page 712 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.11.2 Block Diagram Error latch signal Accumulator Error check Accumulation controller End Start Accumulation sequence circuit Buffer/ register select & R/W A, B, G, etc. Accumulator UA (32 bits), upper accumulator Sign controller Write-only MD (32 bits), multiplied data Read-only Error data (from the error detector) Figure 28.38 Block Diagram of Digital Filter Circuit Rev.3.00 Jan. 10, 2007 page 713 of 1038 REJ09B0328-0300 Calculation buffer Coefficient register Constant register Buffer circuit Motor control data (to PWM circuit) Data bus LA (16 bits), lower accumulator Data shifter Address bus * Add the same 8-bit value as MSB * Add 0s to 8 bits after the decimal point 8 + 24 + GS + 8 8 DGKs15 to 0 CGKs15 to 0 Digital filter control register DFIC CFIC Es XSn 8+ KS Ws 24 24 8 8 VSn DFUout 24 24 PWM Section 28 Servo Circuits Speed system + Usn-1 24 GKs 16 Ofs 14 24 As 16 XAs 24 Y 24 8 8 8 DBs15 to 0 CBs15 to 0 DAs15 to 0 CAs15 to 0 DOfs15 to 0 COfs15 to 0 Es Right-bit shift of the decimal point along with Go 12 PWM Go 16 Z -1 CZs11 to 0 DFER15 to 0 CFER15 to 0 Note: Go = x64, x32 are optional. Go = x64, x32, x16, x8,x4, x2 * DZs11 to 0 4 8 Bs 16 Error detector Usn + Rev.3.00 Jan. 10, 2007 page 714 of 1038 REJ09B0328-0300 * DFUCR PTON CP/DP VBs 24 PWM Note 2 12 PWM Phase direct test output * OPTION Phase system GP + Upn-1 24 8 DGKp15 to 0 CGKp15 to 0 Ep KP Tp 24 8 GKp 16 * Add the same 8-bit value as MSB * Add 0s to 8 bits after the decimal point Ep VPn 24 24 8 + 8 + 20 Z -1 CZp11 to 0 DPER19 to 0 CPER19 to 0 * DZp11 to 0 24 8 BP OfP 16 Error detector Upn AP XAp 24 8 8 VBp 24 16 DBp15 to 0 CBp15 to 0 Figure 28.39 Digital Filter Representation DOfp15 to 0 COfp15 to 0 + 16 DAp15 to 0 CAp15 to 0 Notes: 1. Overflows during accumulation are ignored, and values below the decimal point are always omitted. 2. Gain control is disabled during phase output. * : See figure 28.42, Z-1 Initialization Circuit. Section 28 Servo Circuits 28.11.3 Arithmetic Buffer This buffer stores computational data used in the digital filters. See table 28.14. Write access is -1 limited to the gain and coefficient data (Z ). Other data is used by hardware. None of the data can be read. Table 28.14 Arithmetic Buffer Register Configuration Buffer Data Length Arithmetic Data Phase system Ep Upn Upn-1 (Zp-1) Vpn Tp Y Ap Bp GKp Ofp Ap x Epn Bp x Vpn Gain or Processing 16 bits Coefficient Data 16 bits 16 bits Speed system Es Xsn Usn Usn-1 (Z-1s) Vsn Ws As Bs GKs Ofs As x Xsn Bs x Vsn Error output Legend: PWM Valid bits Non-existent bits Decimal point Rev.3.00 Jan. 10, 2007 page 715 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.11.4 Register Configuration Table 28.15 shows the register configuration of the digital filter computation circuit. Table 28.15 Register Configuration Name Capstan phase gain constant Capstan speed gain constant Capstan phase coefficient A Capstan phase coefficient B Capstan speed coefficient A Capstan speed coefficient B Capstan phase offset Capstan speed offset Drum phase gain constant Drum speed gain constant Drum phase coefficient A Drum phase coefficient B Drum speed coefficient A Drum speed coefficient B Drum phase offset Drum speed offset Drum system speed delay initialization register Drum system phase delay initialization register Capstan system speed delay initialization register Capstan system phase delay initialization register Drum system digital filter control register Capstan system digital filter control register Digital filter control register Abbrev. CGKp CGKs CAp CBp CAs CBs COfp COfs DGKp DGKs DAp DBp DAs DBs DOfp DOfs DZs DZp CZs CZp DFIC CFIC DFUCR R/W W W W W W W W W W W W W W W W W W W W W R/W R/W R/W Size Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Byte Byte Byte Initial Value Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'F000 H'F000 H'F000 H'F000 H'80 H'80 H'C0 Address H'FD010 H'FD012 H'FD014 H'FD016 H'FD018 H'FD01A H'FD01C H'FD01E H'FD000 H'FD002 H'FD004 H'FD006 H'FD008 H'FD00A H'FD00C H'FD00E H'FD020 H'FD022 H'FD024 H'FD026 H'FD028 H'FD029 H'FD02A Rev.3.00 Jan. 10, 2007 page 716 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.11.5 Register Descriptions (1) Gain Constants (DGKp, DGKs, CGKp, CGKs) Bit : Initial value : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * W * W * W * W * W * W * W * W * W * W * W * W W W W R/W : W Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set accumulation gain of the digital filter. They cannot be read. They can be accessed by word access only. Accumulation gain can be set to gain 1 value as the maximum value. Byte access gives unassured results. If read is attempted, an undetermined value is read out. These registers are not initialized by a reset or in standby mode. Be sure to write data in them before processing starts. In the digital filter, output gain and accumulation gain can be adjusted separately. Take output gain into account when setting accumulation gain. (2) Coefficients (DAp, DBp, DAs, DBs, CAp, CBp, CAs, CBs) Bit : 15 Initial value : * 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * W * W * W * W * W * W * W * W * W * W * W * W W W W R/W : W Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that determine the cutoff frequency f1 and f2. They cannot be read. They can be accessed by word access only. Byte access gives unassured results. If read is attempted, an undetermined value is read out. These registers are not initialized by a reset or in standby mode. Be sure to write data in them before processing starts. In the digital filter, output gain and accumulation gain can be adjusted separately. Take output gain into account when setting accumulation gain. Rev.3.00 Jan. 10, 2007 page 717 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) Offsets (DOfp, DOfs, COfp, COfs) Bit : Initial value : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * W * W * W * W * W * W * W * W * W * W * W * W R/W : W W W W Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set the offset level of digital filter output. They cannot be read. They can be accessed by word access only. Byte access gives unassured results. If read is attempted, an undetermined value is read out. These registers are not initialized by a reset or in standby mode. Be sure to write data in them before processing starts. In this digital filter, output gain adjustment (x1, 2, 4, 8 ,16, 32, 64) after offset adding is enabled. Take output gain into account when setting accumulation gain. (4) Delay Initialization Registers (CZp, CZs, DZp, DZs) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The delay initialization register is a 16-bit write-only register. It accepts only a word-access. If a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits 12 to 15 are reserved, and no write in them is valid. It is initialized to H'F000 by a reset, stand-by or module stop. The MSB of 12-bit data (bit 11) is a sign bit. -1 Loading to Z is performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZSON, -1 DZPON, DZSON). Writing in register is always available, but loading in Z is not possible when the digital filter is performing calculation processing in relation to such register. In such a case, -1 loading to Z will be done the next time computation begins. Rev.3.00 Jan. 10, 2007 page 718 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (5) Drum System Digital Filter Control Register (DFIC) Bit : 7 -- 6 DROV 5 DPHA 0 R/(W) 4 DZPON 0 R/W 3 DZSON 0 R/W 2 DSG2 0 R/W 1 DSG1 0 R/W 0 DSG0 0 R/W 1 0 Initial value : R/(W)* -- R/W : Note: * Only 0 can be written DFIC is an 8-bit readable/writable register that controls the status of the drum system digital filter and operating mode. It can be accessed by byte access only. Word access gives unassured results. Bit 7 is a reserved bit. Writes are disabled. If read is attempted, an undetermined value is read out. DFIC is initialized to H'80 by a reset, and in standby mode and module stop mode. Bit 7Reserved: Reads and writes are both disabled. Bit 6Drum System Range Over Flag (DROV): This flag is set to 1 when the result of a drum system filter computation exceeds 12 bits in width. To clear this flag, write 0. Bit 6 DROV 0 1 Description Indicates that the filter computation result did not exceed 12 bits Indicates that the filter computation result exceeded 12 bits (Initial value) Bit 5Drum Phase System Filter Computation Start Bit (DPHA): Starts or stops filter processing for the drum phase system. Bit 5 DPHA 0 1 Description Phase system filter computations are disabled Phase computation result (Y) is not added to Es (see figure 28.39) Phase system filter computations are enabled -1 -1 (Initial value) Bit 4Drum Phase System Z Initialization Bit (DZPON): Reflects the DZp value on Z of the phase system when computation processing of the drum phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp. Bit 4 DZPON 0 1 Description DZp value is not reflected on Z of the phase system DZp value is reflected on Z of the phase system Rev.3.00 Jan. 10, 2007 page 719 of 1038 REJ09B0328-0300 -1 -1 (Initial value) Section 28 Servo Circuits Bit 3Drum Speed System Z Initialization Bit (DZSON): Reflects the DZs value on Z of the speed system when computation processing of the drum speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to DZs. Bit 3 DZSON 0 1 Description DZs value is not reflected on Z of the speed system DZs value is reflected on Z of the speed system -1 -1 -1 -1 (Initial value) Bits 2 to 0Drum System Output Gain Control Bits (DSG2, DSG1, DSG0): Control the gain output to DRMPWM. Bit 2 DSG2 0 Bit 1 DSG1 0 Bit 0 DSG0 0 1 1 0 1 1 0 0 1 1 Note: * Setting optional 0 1 Description x1 x2 x4 x8 x16 (x32)* (x64)* Invalid (Do not set) (Initial value) Rev.3.00 Jan. 10, 2007 page 720 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (6) Capstan System Digital Filter Control Register (CFIC) Bit : 7 -- 6 CROV 5 CPHA 0 R/(W) 4 CZPON 0 R/W 3 CZSON 0 R/W 2 CSG2 0 R/W 1 CSG1 0 R/W 0 CSG0 0 R/W Initial value : 1 0 -- R/W : R/(W)* Note: * Only 0 can be written. CFIC is an 8-bit readable/writable register that controls the status of the capstan system digital filter and operating mode. It can be accessed by byte access only. Word access gives unassured results. Bit 7 is a reserved bit. Writes are disabled. If read is attempted, an undetermined value is read out. CFIC is initialized to H'80 by a reset, and in standby mode and module stop mode. Bit 7Reserved: Reads and writes are both disabled. Bit 6Capstan System Range Over Flag (CROV): This flag is set to 1 when the result of a capstan system filter computation exceeds 12 bits in width. To clear this flag, write 0. Bit 6 CROV 0 1 Description Indicates that the filter computation result did not exceed 12 bits Indicates that the filter computation result exceeded 12 bits (Initial value) Bit 5Capstan Phase System Filter Start Bit (CPHA): Starts or stops filter processing for the capstan phase system. Bit 5 CPHA 0 1 Description Phase filter computations are disabled Phase computation result (Y) is not added to Es (see figure 28.39) Phase filter computations are enabled (Initial value) Rev.3.00 Jan. 10, 2007 page 721 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 4Capstan Phase System Z Initialization Bit (CZPON): Reflects the CZp value on Z of the capstan phase system when computation processing of the phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZp. Bit 4 CZPON 0 1 Description CZp value is not reflected on Z of the phase system CZp value is reflected on Z of the phase system -1 -1 -1 -1 -1 -1 (Initial value) Bit 3Capstan Speed System Z Initialization Bit (CZSON): Reflects the CZs value on Z of the capstan speed system when computation processing of the speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZs. Bit 3 CZSON 0 1 Description CZs value is not reflected on Z of the speed system CZs value is reflected on Z of the speed system -1 -1 (Initial value) Bits 2 to 0Capstan System Gain Control Bits (CSG2, CSG1, CSG0): Control the gain output to CAPPWM. Bit 1 CSG2 0 Bit 2 CSG1 0 Bit 0 CSG0 0 1 1 0 1 1 0 0 1 1 Note: * Setting optional 0 1 Description x1 x2 x4 x8 x16 (x32)* (x64)* Invalid (Do not set) (Initial value) Rev.3.00 Jan. 10, 2007 page 722 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (7) Digital Filter Control Register (DFUCR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 PTON 0 R/W 4 CP/DP 0 R/W 3 CFEPS 0 R/W 2 DFEPS 0 R/W 1 CFESS 0 R/W 0 DFESS 0 R/W DFUCR is an 8-bit readable/writable register which controls the operation of the digital filter. It accepts a byte-access only. If it was word-accessed, operation is not assured. Bits 7 and 6 are reserved. No write in them is valid. It is initialized to H'00 by a reset, stand-by or module stop. Bits 7 and 6Reserved: No read or write is valid. If a read is attempted, an undefined value is read out. Bit 5Phase System Computation Result PWM Output Bit (PTON): Outputs the computation results of only the phase system to PWM. (The computation results of the drum phase system is output to the CAPPWM pin, and that of the capstan phase system is output to the DRMPWM pin.) Bit 5 PTON 0 1 Description Outputs the results of ordinary computation of the filter to PWM pin Outputs the computation results of only the phase system to PWM pin (Initial value) Bit 4PWM Output Selection Bit (CP/DP): Selects whether the phase system computation results when PTON was set to 1 is output to the drum or capstan. The PWM of the selected side outputs ordinary filter computation results (speed system of MIX). Bit 4 CP/DP 0 1 Description Outputs the drum phase system computation results (CAPPWM) Outputs the capstan phase system computation results (DRMPWM) (Initial value) Rev.3.00 Jan. 10, 2007 page 723 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 3Capstan Phase System Error Data Transfer Bit (CFEPS): Transfers the capstan phase system error data to the digital filter when the data write is enforced. Bit 3 CFEPS 0 1 Description Error data is transferred by DVCFG2 signal latching Error data is transferred when the data is written (Initial value) Bit 2Drum Phase System Error Data Transfer Bit (DFEPS): Transfers the drum phase system error data to the digital filter when the data write is enforced. Bit 2 DFEPS 0 1 Description Error data is transferred by HSW (NHSW) signal latching Error data is transferred when the data is written (Initial value) Bit 1Capstan Speed System Error Data Transfer Bit (CFESS): Transfers the capstan speed system error data to the digital filter when the data write is enforced. Bit 1 CFESS 0 1 Description Error data is transferred by DVCFG signal latching Error data is transferred when the data is written (Initial value) Bit 0Drum Speed System Error Data Transfer Bit (DFESS): Transfers the drum speed system error data to the digital filter when the data write is enforced. Bit 0 DFESS 0 1 Description Error data is transferred by NCDFG signal latching Error data is transferred when the data is written (Initial value) Rev.3.00 Jan. 10, 2007 page 724 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.11.6 Filter Characteristics (1) Lag-Lead Filter A filter required for a servo loop is built in the hardware. This filter uses an IIR (Infinite Impulse Response) type digital filter (another type of the digital filter is FIR, i.e. Finite Impulse Response type). This digital filter circuit implements a lag-lead filter, as shown in figure 28.40. R1 INPUT OUTPUT R2 + C Figure 28.40 Lag-Lead Filter The transfer function G (S) is expressed by the following equation. S 2f2 Transfer function G (S) = S 1+ 2f1 1+ f1 = 1/2C (R1 + R2) f2 = 1/2CR2 Rev.3.00 Jan. 10, 2007 page 725 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Frequency Characteristics The computation circuit repeats computation of the function, which is obtained by s-z conversion according to bi-linear approximation of the transfer function on the s-plane. Figure 28.41 shows the frequency characteristics of the lag-lead filter. 20log (f1/f2) gain (dB) f1 f2 Frequency (Hz) phase (deg) 0 Figure 28.41 Frequency CharacterIstics of the Lag-Lead Filter The pulse transfer function G(Z) is obtained by the bi-linear approximation of the transfer function G (S). In the transfer G (S), S= 1 - Z-1 2 * Ts 1 + Z-1 -1 Where, assumed that Z = e-jTs, G (Z) = G * 2 1 + AZ-1 * Ts 1 + BZ-1 1 f2 A= 1 Ts + f2 Ts - 1 f1 B= 1 Ts + f1 Ts - G (Z) = 1 f2 1 Ts + f1 Ts + Ts: Sampling cycle (sec) Rev.3.00 Jan. 10, 2007 page 726 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.11.7 Operations in Case of Transient Response In case of transient response when the motor is activated, the digital filter computation circuit must prevent computation due to a large error. The convergence of the computations becomes slow and servo retraction becomes deteriorating if a large error is input to the filter circuit when it is performing repeated computations. To prevent them from occurring, operate the filter (set -1 constants A and B) after pulling in the speed and phase within a certain range of error, initialize Z -1 (set initial values in CZp, CZs, DZp, DZs) (see section 28.11.8, Initialization of Z ), or use the error data limit function (see section regarding the error detector). 28.11.8 Initialization of Z -1 -1 Z can be initialized by its delay initialization register (CZp, CZs, DZp, DZs). Loading to Z is performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZSON, DZPON, -1 DZSON). Writing in register is always available, but loading in Z is not possible when the digital -1 filter is performing calculation processing in relation to such register. In such a case, loading to Z -1 will be done the next time computation begins. Figure 28.42 shows the initialization circuit of Z . -1 The delay initialization register sets 12-bit data. The MSB (bit 11) is a signed bit. Z has 24 bits for integers and 8 bits for decimals. Accordingly, the same value as the signed bits should be set in -1 the 13 bits on the MSB side of Z , and 0 in the entire decimal section. Example: Value set for the delay initialization register MSB 100000000000 -1 Value set for Z -1 MSB 111111111111100000000000 Set here the value in the signed bits 00000000 Fixed Rev.3.00 Jan. 10, 2007 page 727 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Xn + + Usn - 1 24 8 DZs11 to 0 DZp11 to 0 CZs11 to 0 CZp11 to 0 Vn Res Z USn - -1 Delay initialization register 12 + B Z -1initialization bit DZSON DZPON CZSON CZSON DBs15 to 0 DBp15 to 0 CBs15 to 0 CBp15 to 0 A DAs15 to 0 DAp15 to 0 CAs15 to 0 CAp15 to 0 16 16 W W Internal bus W W Note: MSB of 12-bit data to be written in the delay initialization register is a sign bit. Figure 28.42 Z Initialization Circuit -1 Rev.3.00 Jan. 10, 2007 page 728 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.12 Additional V Signal Generator 28.12.1 Overview The circuit described in this section outputs an additional vertical sync signal to take the place of Vsync in special playback. It is activated at both edges of the HSW signal output by the headswitch timing generator. The head-switch timing generator also outputs a Vpulse signal containing the additional vertical sync pulse itself, and an Mlevel signal that defines the width of the additional vertical sync signal including the equalizing pulses. The additional V signal is output at a three-level output pin (Vpulse). Figure 28.43 shows the additional V signal control circuit. HSW timing generator Csync Vpulse signal Mlevel signal Sync detector OSCH Additional V pulse generator Additional V pulse Figure 28.43 Additional V Pulse Control Circuit HSW Timing Generator: This circuit generates signals that are synchronized with head switching. It should be programmed to generate the Mlevel and Vpulse signals at edges of the HSW signal (VideoFF). For details, see section 28.4, HSW (Head-switch) Timing Generator. Sync Detector: This circuit detects pulses of the width specified by VTR or HTR from the signal input at the Csync pin and generates an internal horizontal sync signal (OSCH). The sync detector has an interpolation function, so OSCH has a regular period even if there are horizontal sync dropouts in the signal received at the pin. For details, see section 28.15, Sync Signal Detector. Rev.3.00 Jan. 10, 2007 page 729 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.12.2 Pin Configuration Table 28.16 summarizes the pin configuration of the additional V signal. Table 28.16 Pin Configuration Name Additional V pulse pin Abbrev. Vpulse I/O Output Function Output of additional V signal synchronized to VideoFF 28.12.3 Register Configuration Table 28.17 summarizes the register that controls the additional V signal. Table 28.17 Register Configuration Name Additional V control register Abbrev. ADDVR R/W R/W Size Byte Initial Value H'E0 Address H'FD06F 28.12.4 Register Description Additional V Control Register (ADDVR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 HMSK 0 R/W 3 Hi-Z 0 R/W 2 CUT 0 R/W 1 VPON 0 R/W 0 POL 0 R/W ADDVR is an 8-bit readable/writable register. It is initialized to H'E0 by a reset, and in standby mode. Bits 7 to 5Reserved: Writes are disabled. If a read is attempted, an undefined value is read out. Bit 4OSCH Mask Bit (HMSK): Masks the OSCH signal in the additional V pulse. Bit 4 HMSK 0 1 Description OSCH is added in OSCH is not added in (Initial value) Rev.3.00 Jan. 10, 2007 page 730 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 3High Impedance Bit (Hi-Z): Set to 1 when the intermediate level is generated by an external circuit. Bit 3 Hi-Z 0 1 Description Vpulse is a three-level output pin Vpulse is a three-state output pin (high, low, or high-impedance) (Initial value) Bits 2 to 0Additional V Output Control Bit (CUT, VPON, POL): These bits control the output at the additional V pin. Bit 2 CUT 0 Bit 1 VPON 0 1 Bit 0 POL * 0 1 1 * 0 1 Legend: * Don't care. Description Low level Negative polarity (see figure 28.46) Positive polarity (see figure 28.45) Intermediate level (high impedance if Hi-Z bit = 1) High level (Initial value) Rev.3.00 Jan. 10, 2007 page 731 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.12.5 Additional V Pulse Signal Figure 28.44 shows the additional V pulse signal. The Mlevel and Vpulse signals are generated by the head-switch timing generator. The OSCH signal is combined with these to produce equalizing pulses. The polarity can be selected by the POL bit in the additional V register (ADDVR). The Vpulse pin outputs a low level by a reset, and in standby mode and module stop mode. Internal bus R/W * ADDVR VPON CUT HMSK R/W R/W R/W POL R/W * ADDVR Hi-Z STBY VCC VCC OSCH Vpulse Rs Vpulse pin Rs Mlevel Legend: STBY: Power-down mode signal Vpulse, Mlevel: Signal from the HSW timing generator Rs: Voltage division resistance (20 k: Reference value) VSS VSS Figure 28.44 Additional V Pin Additional V Pulses when Sync Signal Is Not Detected: With additional V pulses, the pulse signal (OSCH) detected by the sync detector is superimposed on the Vpulse and Mlevel signals generated by the head-switch timing generator. If there is a lot of noise in the input sync signal (Csync), or a pulse is missing, OSCH will be a complementary pulse, and therefore an H pulse of the period set in HRTR and HPWR will be superimposed. In this case, there may be slight timing drift compared with the normal sync signal, depending on the HRTR and HPWR setting, with resultant discontinuity. If no sync signal is input, the additional V pulse is generated as a complementary pulse. Set the sync detector registers and activate the sync detector by manipulating the SYCT bit in the sync signal control register (SYNCR). See section 28.15.7, Sync Signal Detector Activation. Rev.3.00 Jan. 10, 2007 page 732 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Figures 28.45 and 28.46 show the additional V pulse timing charts. HSW signal edge Mlevel signal Vpulse signal OSCH Additional V pulse VPON = 1, CU T= 0, POL = 1 Figure 28.45 Additional V Pulse when Positive Polarity Is Specified Rev.3.00 Jan. 10, 2007 page 733 of 1038 REJ09B0328-0300 Section 28 Servo Circuits HSW signal edge Mlevel signal Vpulse signal OSCH Additional V pulse VPON = 1, CUT = 0, POL = 0 Figure 28.46 Additional V Pulse when Negative Polarity Is Specified Rev.3.00 Jan. 10, 2007 page 734 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13 CTL Circuit 28.13.1 Overview The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then outputs it as the PB-CTL signal to the servo, linear time counter, and other circuits. The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and records VISS, ASM, and VASS marks. A REC-CTL amplifier is included in the record circuits. Detection and recording whether the CTL pulse pattern is long or short can also be enabled to correspond to the wide-aspect. The following operating modes can be selected by settings in the CTL mode register: * Duty discrimination VISS detect, ASM detect, VASS detect, L/S bit pattern detect * CTL record VISS record, ASM record, VASS record, L/S bit pattern detect * Rewrite Trapezoid waveform generator Rev.3.00 Jan. 10, 2007 page 735 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.2 Block Diagram Figure 28.47 shows a block diagram of the CTL circuit. PB-CTL CTL mode IRRCTL FW/RV CTL detector Duty descriminator VISS detect VISS control circuit Bit pattern register VISS write REF30X Schmitt amplifier Write control circuit Duty I/O flag Internal bus +- RECCTL amplifier CTL(+) CTL(-) Figure 28.47 Block Diagram of CTL Circuit Rev.3.00 Jan. 10, 2007 page 736 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.3 Pin Configuration Table 28.18 summarizes the pin configuration of the CTL circuit. Table 28.18 Pin Configuration Name CTL (+) I/O pin CTL (-) I/O pin CTL Bias input pin CTL Amp (O) output pin CTL SMT (i) input pin CTL FB input pin CTL REF output pin Abbrev. CTL (+) CTL (-) CTL Bias CTLAmp (O) CTLSMT (i) CTL FB CTL REF I/O I/O I/O Input Output Input Input Output Function CTL signal input/output CTL signal input/output CTL primary amplifier bias supply CTL amplifier output CTL Schmitt amplifier input CTL amplifier high-range characteristics control CTL amplifier reference voltage output 28.13.4 Register Configuration Table 28.19 shows the register configuration of the CTL circuit. Table 28.19 Register Configuration Name CTL control register CTL mode register Abbrev. CTCR CTLM R/W R/W R/W W W W W W R/W R/W Size Byte Byte Word Word Word Word Word Byte Byte Initial Value H'30 H'00 H'F000 H'F000 H'F000 H'F000 H'F000 H'F1 H'FF Address H'FD080 H'FD081 H'FD082 H'FD084 H'FD086 H'FD088 H'FD08A H'FD08C H'FD08D REC-CTL duty data register RCDR1 1 REC-CTL duty data register RCDR2 2 REC-CTL duty data register RCDR3 3 REC-CTL duty data register RCDR4 4 REC-CTL duty data register RCDR5 5 Duty I/O register Bit pattern register DI/O BTPR Rev.3.00 Jan. 10, 2007 page 737 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.5 Register Descriptions (1) CTL Control Register (CTCR) Bit : 7 NT/PL Initial value : R/W : 0 W 6 FSLC 0 W 5 FSLB 1 W 4 FSLA 1 W 3 CCS 0 W 2 LCTL 0 W 1 UNCTL 0 R 0 SLWM 0 W The CTL control register (CTCR) controls PB-CTL rewrite and sets the slow mode. When a CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register (CTLGR) in the PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared to 0 when a CTL pulse is detected. CTCR is an 8-bit readable/writable register. However, bit 1 is read-only, and the rest is write-only. CTCR is initialized to H'30 by a reset, and in standby and module stop mode. Bit 7NTSC/PAL Selection Bit (NT/PL): Selects the period of the rewrite circuit. Bit 7 NT/PL 0 1 Description NTSC mode (frame rate: 30 Hz) PAL mode (frame rate: 25 Hz) (Initial value) Bits 6 to 4Frequency Selection Bits (FSLA, FSLB, FSLC): These bits select the operating frequency of the CTL rewrite circuit. They should be set according to fosc. Bit 6 FSLC 0 Bit 5 FSLB 0 Bit 4 FSLA 0 1 1 0 1 1 * * Legend: * Don't care. Description Reserved (do not set) Reserved (do not set) fosc = 8 MHz fosc = 10 MHz Reserved (do not set) (Initial value) Rev.3.00 Jan. 10, 2007 page 738 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 3Clock Source Selection Bit (CCS): Selects clock source of CTL. Bit 3 CCS 0 1 Description s s/2 (Initial value) Bit 2Long CTL Bit (LCTL): Sets the long CTL detection mode. Bit 2 LCTL 0 1 Description Clock source (CCS) operates at the setting value (Initial value) Clock source (CCS) operates for further 8-division after operating at the setting value Bit 1CTL Undetected Bit (UNCTL): Indicates the CTL pulse detection status at the CTL input amplifier sensitivity set at the CTL gain control register (CTLGR). Bit 1 UNCTL 0 1 Description Detected Undetected (Initial value) Bit 0Mode Selection Bit (SLWM): Selects CTL mode. Bit 0 SLWM 0 1 Description Normal mode Slow mode (Initial value) Rev.3.00 Jan. 10, 2007 page 739 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) CTL Mode Register (CTLM) Bit : 7 ASM Initial value : R/W : 0 R/W 6 REC/PB 0 R/W 5 FW/RV 0 R/W 4 MD4 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W The CTL mode register (CTLM) is an 8-bit readable/writable register that controls the operating state of the CTL circuit. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle () later. CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode. When CTL is being stopped, only bits 7, 6, and 5 operate. Note: Do not set any value other than the setting value for each mode (see table 28.20). Bits 7 and 6Record/Playback Mode Bits (ASM, REC/PB): These bits switch between record and playback. Combined with bits 4 to 0 (MD4 to MD0), they support the VISS, VASS, and ASM mark functions. Bit 7 ASM 0 Bit 6 REC/PB 0 1 1 0 1 Description Playback mode Record mode Assemble mode Invalid (do not set) (Initial value) Bit 5Direction Bit (FW/RV): Selects the direction in playback. Clear this bit to 0 during record. Figure 28.48 shows the PB-CTL signal in forward and reverse. Bit 5 FW/RV 0 1 Description FORWARD REVERSE (Initial value) Rev.3.00 Jan. 10, 2007 page 740 of 1038 REJ09B0328-0300 Section 28 Servo Circuits CTL input FWD PB-CTL REV Figure 28.48 Internal PB-CTL Signal in Forward and Reverse Bits 4 to 0CTL Mode Selection Bits (MD4 to MD0): These bits select the detect, record, and rewrite modes for VISS, VASS, and ASM marks. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle () later. The 5 bits from MD4 to MD0 are used in combination with bits 7 and 6 (ASM and REC/PB). Table 28.20 describes the modes. Table 28.20 CTL Mode Functions Bit ASM 0 REC/ PB 0 FW/ RV 0/1 MD4 0 MD3 0 MD2 0 MD1 0 MD0 0 Mode VASS detect (duty detect) Description PB-CTL duty discrimination (Initial value) * Duty I/O flag is set to 1 if duty 44% is detected * Duty I/O flag is cleared to 0 if duty < 44% is detected * Interrupt request is generated when one CTL pulse has been detected 0 1 0 0 0 0 0 0 VASS record * If 0 is written in the duty I/O flag, REC-CTL is generated and recorded with the duty cycle set by register RCDR2 or RCDR3 * If 1 is written in the duty I/O flag, REC-CTL is generated and recorded with the duty cycle set by register RCDR4 or RCDR5 0 0 0 1 0 0 1 0 VASS rewrite Same as above (VASS record; trapezoid waveform circuit operation) Rev.3.00 Jan. 10, 2007 page 741 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit ASM 0 REC/ PB 0 FW/RV MD4 0/1 0 MD3 1 MD2 0 MD1 0 MD0 1 Mode VISS detect (index detect) Description The duty I/O flag is set to 1 at the point of write access to register CTLM * The 1 pulses recognized by the duty discrimination circuit are counted in the VISS control circuit * The duty I/O flag is cleared to 0, indicating VISS detection, when the value set at VCTR register is repeatedly detected * An interrupt request is generated when VISS is detected 0 1 0 0 0 1 0 1 VISS record (index record) * 64 pulse data with 0 pulse data at both edges are written (index record) * The index bit string is written through the duty I/O flag * An interrupt request is generated at the end of VISS recording 0 0 1 0 0 0 0 0 0/1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 VISS rewrite VISS initialize Same as above (VISS record; trapezoid waveform circuit operation) VISS write is forcibly aborted ASM mark ASM mark detection detect * The duty I/O flag is cleared to 0 when PB-CTL duty 66% is detected * An interrupt request is generated when an ASM mark is detected 0 1 0 1 0 0 0 0 ASM mark * An ASM mark is recorded by writing record 0 in the duty I/O flag * An interrupt is requested for every one CTL pulse * REC-CTL is generated and recorded with the duty cycle set by register RCDR3 Rev.3.00 Jan. 10, 2007 page 742 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) REC-CTL Duty Data Register 1 (RCDR1) Bit : 15 -- Initial value : R/W : 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W RCDR1 is a register that sets the REC-CTL rising timing. This setting is valid only for recording and rewriting, and is not used in detection. RCDR1 is a 12-bit write-only register, and can be accessed by word access only. Byte access gives unassured results. If read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not affected by write access. RCDR1 is initialized to H'F000 by a reset, and in standby mode, module stop mode and CTL stop mode. The value to set in RCDR1 can be calculated from the transition timing T1 and the servo clock frequency s by the equation given below. See figure 28.60. Any transition timing can be set. However, the timing should be selected with attention to playback tracking compensation and the latch timing for phase control. RCDR1 = T1 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T1 is the set timing (s). Note: 0 cannot be set to RCDR1. Set a value 1 or above. (4) REC-CTL Duty Data Register 2 (RCDR2) Bit : 15 -- Initial value : R/W : 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W RCDR2 is a register that sets 1 pulse (short) falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting. RCDR2 is a 12-bit write-only register, and can be accessed by word access only. Byte access gives unassured results. If read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not affected by write access. RCDR2 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL stop mode. At recording, the value to set in RCDR2 can be calculated from the transition timing T2 and the servo clock frequency s by the equation given below, and the set value should be 25% of the duty obtained by the equation. See figure 28.60. Rev.3.00 Jan. 10, 2007 page 743 of 1038 REJ09B0328-0300 Section 28 Servo Circuits RCDR2 = T2 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T2 is the set timing (s). At bit pattern detection, set the 1 pulse long/short threshold value at FWD. See figure 28.56. RCDR2 = T2' x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T2' is the 1 pulse long/short threshold value at FWD (s). (5) REC-CTL Duty Data Register 3 (RCDR3) Bit : 15 -- Initial value : 1 R/W : -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W RCDR3 is a register that sets 1 pulse (long) and assemble mark falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting. RCDR3 is a 12-bit write-only register, and can be accessed by word access only. Byte access gives unassured results. If read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not affected by write access. RCDR3 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL stop mode. At recording, the value to set in RCDR3 can be calculated from the transition timing T3 and the servo clock frequency s by the equation given below. The set value should be 30% of the duty when the RCDR3 is used for REC-CTL 1 pulse (long), and 67% to 70% when used for assemble mark. The set value must not exceed the value of REF30X. See figure 28.60. RCDR3 = T3 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T3 is the set timing (s). At bit pattern detection, set the 0 pulse long/short threshold value at FWD. See figure 28.56. RCDR3 = T3' x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T3' is the 0 pulse long/short threshold value at FWD (s). Rev.3.00 Jan. 10, 2007 page 744 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (6) REC-CTL Duty Data Register 4 (RCDR4) Bit : 15 -- Initial value : 1 R/W : -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W RCDR4 sets the timing of falling edge of the 0 pulse (short) of REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse. RCDR4 is a 12-bit write-only register. It accepts only a word-access. If a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits 15 to 12 are reserved, and no write in them is valid. It is initialized to H'F000 by a reset, stand-by, module stop or CTL stop. In record mode, set a value with the 57.5% duty cycle obtained from the transition timing T4 corresponding to the servo clock frequency s according to the following equation. See figure 28.60. RCDR4 = T4 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T4 is the set timing (s). At bit pattern detection, set the 0 pulse long/short threshold value at REV. See figure 28.56. RCDR4 = H'FFF - (T4' x s/80) s is the servo clock frequency (= fOSC/2) in Hz, and T4' is the 0 pulse long/short threshold value at REV (s). (7) REC-CTL Duty Data Register 5 (RCDR5) Bit : Initial value : 15 -- 1 R/W : -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W RCDR5 sets the timing of falling edge of the 0 pulse (long) of REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse. RCDR5 is a 12-bit write-only register. It accepts only a word-access. If a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits 15 to 12 are reserved, and no write in them is valid. It is initialized to H'F000 by a reset, stand-by, module stop or CTL stop. In record mode, set a value with the 62.5% duty cycle obtained from the transition timing T5 corresponding to the servo clock frequency s according to the following equation. See figure 28.60. Rev.3.00 Jan. 10, 2007 page 745 of 1038 REJ09B0328-0300 Section 28 Servo Circuits RCDR5 = T5 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T5 is the set timing (s). At bit pattern detection, set the 1 pulse long/short threshold value at REV. See figure 28.56. RCDR5 = H'FFF - (T5' x s/80) s is the servo clock frequency (= fOSC/2) in Hz, and T5' is the 1 pulse long/short threshold value at REV (s). (8) Duty I/O Register (DI/O) Bit : 7 VCTR2 6 VCTR1 5 VCTR0 1 W 4 -- 1 -- 3 BPON 0 W 2 BPS 0 W 1 BPF 0 R/(W)* 0 DI/O 1 R/W Initial value : 1 1 W W R/W : Note: * Only 0 can be written. The duty I/O register is an 8-bit register that confirms and determines the operating status of the CTL circuit. It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode. Bits 7, 6, and 5VISS Interrupt Setting Bits (VCTR2, VCTR1, VCTR0): Combination of VCTR2, VCTR1, and VCTR0 sets number of 1 pulse detection in VISS detection mode. Detecting the set number of pulse detection is considered as VISS detection, and an interrupt request is generated. Note: When changing the detection pulse number during VISS detection, initialize VISS first, then resume the VISS detection setting. Bit 7 VCTR2 0 Bit 6 VCTR1 0 Bit 5 VCTR0 0 1 1 0 1 1 0 0 1 1 0 1 Number of 1-Pulse for Detection 2 4 (SYNC mark) 6 8 (mark A, short) 12 (mark A, long) 16 24 (mark B) 32 Rev.3.00 Jan. 10, 2007 page 746 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 4Reserved: Writes are disabled. When read, undefined values are obtained. Bit 3Bit Pattern Detection ON/OFF Bit (BPON): Determines ON or OFF of bit pattern detection. Note: When writing 1 to the BPON bit, be sure to set appropriate data to RCDR2 to RCDR5 beforehand. Bit 3 BPON 0 1 Description Bit pattern detection OFF Bit pattern detection ON (Initial value) Bit 2Bit Pattern Detection Start Bit (BPS): Starts 8-bit bit pattern detection. When 1 is written to this bit, it returns to 0 after one cycle. Writing 0 to this bit does not affect operation. Bit 2 BPS 0 1 Description Normal status Starts 8-bit bit pattern detection (Initial value) Bit 1Bit Pattern Detection Flag (BPF): Sets the flag every time 8-bit PB-CTL is detected in PB or ASM mode. To clear the flag, write 0 after reading 1. Bit 1 BPF 0 1 Description Bit pattern (8-bit) is not detected Bit pattern (8-bit) is detected (Initial value) Bit 0Duty I/O Register (DI/O): This flag has different functions for record and playback. In VISS detect mode, VASS detect mode, and ASM mark detect mode, this flag indicates the detection result. In VISS record or rewrite mode, this flag controls the write control circuit so as to write an index code, operating according to a control signal from the VISS control circuit. In VISS record or rewrite mode and ASM mark record mode, this flag is used for write control, one CTL pulse at a time. This bit can always be written to, but this does not affect the write control circuit in modes other than VISS record or rewrite, and ASM record. Rev.3.00 Jan. 10, 2007 page 747 of 1038 REJ09B0328-0300 Section 28 Servo Circuits VISS Detect Mode and VASS Detect Mode: The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is equal to or above 44% (a 0 pulse in the CTL signal). The duty I/O flag is 0 when the duty cycle of the PB-CTL signal is below 43% (a 1 pulse in the CTL signal). ASM Mark Detect Mode: The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 0 when the duty cycle of the PB-CTL signal is equal to or above 66% (when an ASM mark is detected). The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is below 65% (when an ASM mark is not detected). VISS Record Mode and VISS Rewrite Mode: The duty I/O flag operates according to a control signal from the VISS control circuit, and controls the write control circuit so as to write an index code. The write timing is set in the REC-CTL duty data registers (RCDR1 to RCDR5). For VISS recording, registers RCDR1 to RCDR5 are set with reference to REF30X. For VISS rewrite, registers RCDR2 to RCDR5 are set with reference to the low-to-high transition of the previously recorded CTL signal, and the write is carried out through the trapezoid waveform generator. Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0 pulse (short) in RCDR4, and for a 0 pulse (long) in RCDR5. While an index code is being written, the value of the bit being written can be read by reading the duty I/O flag. If the CTL signal currently being written is a 0 pulse, the duty I/O flag will read 1. If the CTL signal currently being written is a 1 pulse, the duty I/O flag will read 0. VASS Record Mode and VASS Rewrite Mode: The duty I/O flag is used for write control, one CTL pulse at a time. The write timing is set in the REC-CTL duty data registers (RCDR1 to RCDR5). For VASS recording, registers RCDR1 to RCDR5 are set with reference to REF30X. For VASS rewrite, registers RCDR2 to RCDR5 are set with reference to the low-to-high transition of the previously recorded CTL signal, and the write is carried out through the trapezoid waveform generator. Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0 pulse (short) in RCDR4, and for a 0 pulse (long) in RCDR5. If 0 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR2 and RCDR3, referenced to the immediately following REF30X. If 1 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR4 and RCDR5, referenced to the immediately following REF30X. ASM Record Mode: The duty I/O flag is used for write control, one CTL pulse at a time. The write timing is set in the REC-CTL duty data registers (RCDR1 and RCDR3). If 0 is written in the duty I/O flag, a CTL Rev.3.00 Jan. 10, 2007 page 748 of 1038 REJ09B0328-0300 Section 28 Servo Circuits pulse will be written with a duty cycle of 67% to 70% as set in RCDR3, referenced to the immediately following REF30X. (9) Bit Pattern Register (BTPR) Bit : 7 LSP7 6 LSP6 5 LSP5 4 LSP4 3 LSP3 2 LSP2 1 R/W* 1 LSP1 1 R/W* 0 LSP0 1 R/W* Initial value : 1 1 1 1 1 R/W : R/W* R/W* R/W* R/W* R/W* Note: * Write is prohibited when bit pattern detection is selected. The bit pattern register (BTPR) is an 8-bit shift register which detects and records the bit pattern of the CTL pulses. If a CTL pulse is detected in PB or ASM mode, the register is shifted leftward at the rising edge of PB-CTL, and reflects the determined result of long/short on bit 0 (long pulse = 1, short pulse = 0). If the BPON bit is set to 1 in PB mode, the register starts detection of bit pattern immediately after the CTL pulse. To exit the bit pattern detection, set the BPON bit at 0. If 1 was written in the BPS bit when the bit pattern is being detected, the BPF bit is set at 1 when an 8-bit bit pattern was detected. If continuous detection of 8-bits is required, write 0 in the BPF bit, and then write 1 in the BPS bit. At the time of VISS detection, the bit pattern detection is disabled. Set the BPON bit to 0 at the time of VISS detection. In REC mode, the register records the long/short in the bit pattern set in BTPR. The pulse in record mode is determined always by bit 7 (LSP7) of BTPR. BTPR records one pulse, shifts leftward, and stores the data of bit 7 to bit 0. BTPR is initialized to H'FF by a reset, stand-by, module stop, or CTL stop. Rev.3.00 Jan. 10, 2007 page 749 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.6 Operation CTL Circuit Operation: As shown in figure 28.49, the CTL discrimination/record circuit is composed of a 16-bit up/down counter and 12-bit registers (x5). In playback (PB) mode, the 16-bit up/down counter counts on a s/4 clock when the PB-CTL pulse is high, and on a s/5 clock when low. In record (REC) or slow mode, this counter counts up on a s/8 clock when the pulse is high, and on a s/4 clock when low. This counter always counts up in record and slow modes. In playback or slow mode, it is cleared on the rise of a PB-CTL signal. In record mode, it is cleared on the rise of an REF30X signal. UP/DOWN control signal REC: UP PB, ASM: UP when PB-CTL is high Down when PB-CTL is low Counter clear signal REF30X (REC) PB-CTL (PB, ASM) UP s/4 (s/8) s/5 (s/4) UP/DOWN counter (16 bits) DOWN RCDR1 RCDR2 RCDR3 RCDR4 UDF: Underflows when PB-CTL duty is 43% or less RCDR5 12-bit register UDF Duty detection Upper 12 bits Match detection Match detection Match detection Match detection Match detection REC-CTL REC-CTL(S1) REC-CTL(L1and ASM) REC-CTL(S0) REC-CTL(L0) Figure 28.49 CTL DIscrimination/Record Circuit CTL Mode Register (CTLM) Switchover Timing: CTLM is enabled immediately after data is written to the register. Care must be taken with changes in the operating state. Capstan phase control is performed by the VD sync REF30X (X-value + tracking value) and PBCTL in ASM mode, and by the REF30X or CREF and CFG division signal (DVCFG2) in REC Rev.3.00 Jan. 10, 2007 page 750 of 1038 REJ09B0328-0300 Section 28 Servo Circuits mode. If the CAPREF30 signal to be used for capstan phase control is always generated by XDR, the value of XDR must be overwritten when switching between PB and REC modes. Figures 28.50 and 28.51 show examples of switchover timing of CTLM and XDR. The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle VD REF30P HSW X-value after change Tx Latch Preset X-value Capstan phase control ASM mode, PB mode : REF30X-PB-CTL REC mode : REF30P-DVCFG2 REF30X PB-CTL REC-CTL CTL Ta Tb 16-bit UP/DOWN counter /4 /5 /4 RCDR1 UDF 0 pulse 1 pulse RCDR3 RCDR1 RCDR2 1 pulse 0 pulse DVCFG2 CDIVR2 Register write Ta is the interval calculated from RCDR3. Tb is the interval in which switchover is performed from ASM mode to REC mode. Tx is the cycle in which the REF30X period is shortened due to the change of XDR. Figure 28.50 Example of CTLM Switchover Timing (when Phase Control Is Performed by REF30P and DVCFG2 in REC Mode) Rev.3.00 Jan. 10, 2007 page 751 of 1038 REJ09B0328-0300 Section 28 Servo Circuits The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle VD REF30P HSW X value X-value after change Tx Capstan phase control ASM mode, PB mode: REF30X-PB-CTL REF30X PB-CTL CTL Ta Tb REC-CTL 16-bit UP/DOWN counter /4 /5 /4 RCDR1 UDF RCDR3 RCDR1 RCDR2 0 pulse 1 pulse 0 pulse 1 pulse DVCFG2 CDIVR2 Register write CREF ASM-REC switchover Capstan phase control REC mode : REF30P-DVCFG2 Latch Preset Ta is the interval calculated from RCDR3. Tb is the interval in which switchover is performed from ASM mode to REC mode. Tx is the cycle in which the REF30X period is shortened due to the change of XDR. With CREF and DVCFG2 phase alignment, the frequency need not be 25 Hz or 30 Hz. Figure 28.51 Example of CTLM Switchover Timing (when Phase Control Is Performed by CREF and DVCFG2 in REC Mode) Rev.3.00 Jan. 10, 2007 page 752 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.7 CTL Input Section The CTL input section consists of an input amplifier whose gain can be controlled by register setting and a Schmitt amplifier. Figure 28.52 shows a block diagram of the CTL input section. A trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier, reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits and timer L as the PB-CTL signal. Control the CTL input amplifier gain by bits 3 to 0 in the CTL gain control register (CTLGR) of the servo port. AMPON (PB-CTL) AMPSHORT (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 -+ + - - + PB-CTL(+) PB-CTL(-) CTL(-) CTL(+) CTLREF CTLBias CTLFB CTLAmp(o) CTLSMT(i) Note Note : Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i). Figure 28.52 Block Diagram of CTL Input Section Rev.3.00 Jan. 10, 2007 page 753 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (1) CTL Detector If the CTL detector fails to detect a CTL pulse, it sets bit 1 of the CTL control register (CTCR) to high indicating that the pulse has not been detected. If a CTL pulse is detected after that, the bit is automatically cleared to 0. Duration used for determining detection or non-detection of the pulse depends on magnitude of phase shift of the last detected pulse from the reference phase (phase difference between REF30 and CTL signal). Typically, detection or non-detection is determined within 3 to 4 cycles of the reference period. If settings of the CTL gain control register are maintained in a table format, you can refer to it when the CTL detector failed to detect CTL pulses. From the table, you can control input sensitivity of the CTL according to the state of the UNCTL bit, thereby selecting an optimum CTL amplifier gain depending on the state of the pulse recorded. Figure 28.53 illustrates the concept of gain control for detecting the CTL input pulse. * V+TH (fixed) V-TH (fixed) * Note: * CTL input sensitivity is variable depending on CTL gain control register (CTLGR) setting. Figure 28.53 CTL Input Pulse Gain Control Rev.3.00 Jan. 10, 2007 page 754 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) PB-CTL Waveform Shaper in Slow Mode Operation If bit 0 in the CTL control register (CTCR) is set to slow mode, slow reset function is activated. In slow mode, if the falling edge is not detected within the specified time from rising edge detection, PB-CTL is forcibly shut down (slow reset). The time TFS (s) until the signal falls is the following interval after the rising edge of the internal CTL signal is detected: TFS = 16384 x 4 s (s = fOSC/2) When fOSC = 10 MHz, TFS = 13.1 ms. Figure 28.54 shows the PB-CTL waveform in slow mode. 1 frame 1 frame 1 frame CTL waveform Slow reset Internal CTL signal CTLP Acceleration Deceleration Acceleration CTLP Deceleration Acceleration CTLP Slow tracking delay Stop Slow tracking delay Stop Slow tracking delay Figure 28.54 PB-CTL Waveform in Slow Mode Operation Rev.3.00 Jan. 10, 2007 page 755 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.8 Duty Discriminator The duty discriminator circuit measures the period of the control signal recorded on the tape (PBCTL signal) and discriminates its duty cycle. In VISS or VASS detection, the duty I/O flag is set or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when the duty cycle of the PB-CTL signal is equal to or above 44%, and is cleared to 0 when the duty cycle is below 43%. In ASM detection, an ASM mark is recognized (and the duty I/O flag is cleared to 0) when the duty cycle is equal to or above 66%. When the duty cycle is below 65%, no ASM mark is recognized and the duty I/O flag is set to 1. The detection direction can be switched between forward and reverse by bit 5 (FW/RV) in the CTL mode register. A long or short pulse can be detected by comparing the REC-CTL duty data register (RCDR2 to RCDR5) and UP/DOWN counter. Long or short pulse is discriminated at PB-CTL signal falling. Discrimination result is stored in bit 0 (LSP0) of the bit pattern register (BTPR). At the same time, BTPR is shifted to the left. LSP0 indicates 0 when a short pulse is detected, and 1 when a long pulse is detected. Set the threshold value of a long/short pulse in RCDR2 to RCDR5. See (4), Detection of the Long/Short Pulse. Figure 28.55 shows the duty cycle of the PB-CTL signal. Rev.3.00 Jan. 10, 2007 page 756 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Input signal Short 1 pulse PB-CTL 25 0.5% Input signal Long 1 pulse PB-CTL 30 0.5% Input signal Short 0 pulse PB-CTL 57.5 0.5% Input signal Long 0 pulse PB-CTL 62.5 0.5% Input signal ASM Mark PB-CTL 67 to 70% Figure 28.55 PB-CTL Signal Duty Cycle Rev.3.00 Jan. 10, 2007 page 757 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Figure 28.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by counting with the 16-bit up/down counter, using a s/4 clock for the up-count and a s/5 clock for the down-count. An up-count is performed when the PB-CTL signal is high, and a down-count when low. Long or short pulse is discriminated by comparing with RCDR2 to RCDR5. PB-CTL s/4 s/5 Comparison of upper 12-bit * RCDR2or4 (12 bits) * RCDR3or5 (12 bits) * FWD : Discriminated by RCDR2 and RCDR3 REV : Discriminated by RCDR4 and RCDR5 s/4 Counter s/5 S R Clear PB-CTL Q L/S discrimination UP/DOWN UP/DOWN counter (16 bits) UDF 0/1 discrimination PB-CTL 1 pulse s/5 Counter s/4 PB-CTL 0 pulse RCDR3 Counter 0 pulse L/S threshold value s/5 1 pulse L/S threshold value s/4 FWD RCDR2 PB-CTL Short pulse (0 pulse) s/5 REV RCDR4 Counter RCDR5 PB-CTL Long pulse (1 pulse) s/4 0 pulse L/S threshold value 1 pulse L/S threshold value Figure 28.56 Duty DIscriminator Rev.3.00 Jan. 10, 2007 page 758 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (1) VISS (Index) Detect/Record Mode VISS detection is carried out by the VISS control circuit, which counts 1 pulses in the PB-CTL signal. If the pulse count detects any value set in the VISS interrupt setting bits (bits 5, 6, and 7 in the duty I/O register), an interrupt request is generated and the duty I/O flag is cleared to 0. At VISS record or rewrite, INDEX code is automatically written. INDEX code is composed of continuous 62-bit data with 0 pulse data at both edges. Examples of bit strings and the duty I/O flag at VISS detection/record are illustrated in figure 28.57. IRRCTL Thirty-two 1 pulses detected Tape direction 01111 1 1 1 1 0 613 bits 633 bits Start Duty I/O flag (a) VISS detection (INDEX: Thirty-two 1 pulse setting) IRRCTL 123 Tape direction 01111 1 1 62 63 64 1 1 0 62 bits 64 bits Start Duty I/O flag (b) VISS record Figure 28.57 Examples of VISS Bit Strings and Duty I/O Flag Rev.3.00 Jan. 10, 2007 page 759 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) VASS Detect Mode VASS detection is carried out by the duty discriminator. Software can detect index sequences by reading the duty I/O flag at each CTL pulse. At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty I/O flag, and simultaneously generates an interrupt request. The duty I/O flag is cleared to 0 if the CTL pulse is a 1 (duty cycle below 43%), and is set to 1 if the CTL pulse is a 0 (duty cycle equal to or above 44%). The duty I/O flag is modified at each CTL pulse. It should be read by the interrupt-handling routine within the period of the PB-CTL signal. The VASS detection format is illustrated in figure 28.58. Tape direction Written three times 11111111111S Header (11 bits) M B LM SS BB LM SS BB LM SS BB L S B Thousands Hundreds Tens Ones Data (16 bits: 4 digits of 4-bit BCD) Figure 28.58 VASS (Index) Format (3) Assemble (ASM) Mark Detect Mode ASM mark detection is carried out by the duty discriminator. If the duty discriminator detects that the duty cycle of the PB-CTL signal is 66% or higher, it generates an interrupt request, and simultaneously clears the duty I/O flag to 0. The duty I/O flag is updated at every CTL pulse. It should be read by the interrupt-handling routine within the period of the PB-CTL signal. Rev.3.00 Jan. 10, 2007 page 760 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (4) Detection of the Long/Short Pulse The Long/Short pulse is detected in PB mode by the L/S determination based on the comparison of the REC-CTL duty registers (RCDR2 to RCDR5) with the up/down counter and the results of the duty I/O flag. The results of the determination are stored in bit 0 (LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting BTPR leftward at the same time. RCDR2 to RCDR5 set the L/S thresholds for each of FWD/REV. Set to RCDR2 a threshold of 1 pulse L/S for FWD, to RCDR3 a threshold of 0 pulse L/S for FWD, to RCDR4 a threshold of 0 pulse L/S for REV, and to RCDR5 a threshold of 1 pulse L/S for REV. Figure 28.59 shows the detection of the Long/Short pulse. Also, the bit pattern of eight bits can be detected by BTPR. Check that an 8-bit detection has been done by bit 1 (BPF bit) of the duty I/O register, and then read BTPR. Internal bus R BTPR Shift leftward Bit pattern register (8 bits) LSB RCDR2 (12 bits) RCDR3 (12 bits) S R Q RCDR4 (12 bits) RCDR5 (12 bits) S R Q FW/RV DI/O High-order 12-bit data s/4 UP/DOWN counter (16 bits) L/S is determined at the rising edge of PB-CTL. After the determination, the bit pattern register is shifted leftward, and the results of the determination are stored in the LSB. Figure 28.59 Detection of Long/Short Pulse Rev.3.00 Jan. 10, 2007 page 761 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.9 CTL Output Section An on-chip control head amplifier is provided for writing the REC-CTL signal generated by the write control circuit onto the tape. The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS and VASS sequences and ASM marks and the rewriting of VISS and VASS sequences. The duty cycle of the REC-CTL signal is set in REC-CTL duty data registers 1 to 5 (RCDR1 to RCDR5). Times calculated in terms of s (= fOSC/2) should be converted to appropriate data to be set in these registers. In VISS or VASS mode, set RCDR2 for a duty cycle of 25% 0.5%, RCDR3 for a duty cycle of 30% 0.5%, RCDR4 for a duty cycle of 57.5 0.5%, and RCDR5 for a duty cycle of 62.5 0.5%. When 1 is written in the duty I/O flag, the REC-CTL signal will be written on the tape with a 25% 0.5% duty cycle when 0 is written in bit 7 (LSP7) in the bit pattern register (BTPR) and with a 30 0.5% duty cycle when 1 is written. Table 28.21 shows the relationship between the REC-CTL duty register and CTL outputs. In ASM mark write mode, set RCDR3 for a duty cycle of 67% to 70%. An ASM mark will be written when 0 is written in the duty I/O flag. An interrupt request is generated at the rise of the reference signal after one CTL pulse has been written. The reference signal is derived from the output signal (REF30X) of the X-value adjustment circuit, and has a period of one frame. Figure 28.60 shows the timings that generate the REC-CTL signal. Table 28.21 REC-CTL Duty Register and CTL Outputs MODE VISS and VASS modes D/IO 0 LSP7 0 1 1 0 1 ASM mode Legend: * Don't care. 0 * Pulse S1 L1 S0 L0 RCDR RCDR2 RCDR3 RCDR4 RCDR5 RCDR3 Duty 25 0.5% 30 0.5% 57.5 0.5% 62.5 0.5% 67 to 70% Rev.3.00 Jan. 10, 2007 page 762 of 1038 REJ09B0328-0300 Section 28 Servo Circuits RESET REF30X Clear s/4 UP/DOWN counter (12 bits) Upper 12 bits Internal bus W W W RCDR1 (12 bits) RCDR2or4 (12 bits) RCDR3or5 (12 bits) Compare Compare Compare REC-CTL rise timing REC-CTL 1 pulse, ASM fall timing REC-CTL 0 pulse fall timing End of writing of one CTL pulse (except VISS) IRRCTL REF30X Counter reset Match detection Counter Match detection REC-CTL RCDR1 RCDR2 (VISS/VASS S1 pulse) RCDR3 (VISS/VASS L1 pulse, or ASM) RCDR4 (VISS/VASS S0 pulse) RCDR5 (VISS/VASS L0 pulse) Figure 28.60 REC-CTL Signal Generation Timing Rev.3.00 Jan. 10, 2007 page 763 of 1038 REJ09B0328-0300 Section 28 Servo Circuits The 16-bit counter in the REC-CTL circuit continues counting on a clock derived by dividing the system clock s (= fOSC/2) by 4. The counter is cleared on the rise of REF30X in record mode, and on the rise of PB-CTL in rewrite mode. The REC-CTL match detection is carried out by comparing the counter value with each RCDR value. RCDR1 to RCDR5 can be written to by software at all times. If RCDR is changed before the respective match detection is performed, match detection is performed using the new value. The value changed after match detection becomes valid on the rise of REF30X following the change. Figure 28.61 shows an example of RCDR change timing. REF30X RCDR4 Counter RCDR2 RCDR1 REC-CTL RCDR1 RCDR2 RCDR1 RCDR4 RCDR1 RCDR4 RCDR4 Interval in which RCDR4 can be written to Rewritten 0 pulse (Short) RCDR1 1 pulse (Short) 0 pulse (Short) Figure 28.61 Example of RCDR Change Timing (Example Showing RCDR4) Rev.3.00 Jan. 10, 2007 page 764 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.10 Trapezoid Waveform Circuit In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PBCTL signal intact, but changes the duty cycle. In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5). Time values T2 to T5 are referenced to the rise of PB-CTL. Figure 28.62 shows the rewrite waveform. RESET PB-CTL W Clear s/4 UP/DOWN counter (16 bits) RCDR2or4 (12 bits) RCDR3or5 (12 bits) RCDR1 (12 bits) Not used when rewriting Upper 12 bits Internal bus W W Compare Compare REC-CTL 1 pulse fall timing REC-CTL 0 pulse fall timing End of writing of one CTL pulse (except VISS) IRRCTL PB-CTL Eliminated pulse High-impedance interval New pulse REC-CTL when rewriting T2 to T5 RCDR2 (VISS/VASS S1 pulse) RCDR3 (VISS/VASS L1 pulse) RCDR4 (VISS/VASS S0 pulse) RCDR5 (VISS/VASS L0 pulse) Figure 28.62 Relationship between REC-CTL and RCDR2 to RCDR5 when Rewriting Rev.3.00 Jan. 10, 2007 page 765 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.13.11 Note on CTL Interrupt Following a reset, the CTL circuit is in the VASS detect (duty detect) mode. Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an interrupt request generated. If the interrupt request will be enabled, first clear the CTL interrupt request flag. 28.14 Frequency Dividers 28.14.1 Overview On-chip frequency dividers are provided for the pulse signal picked up from the control track during playback (PB-CTL signal), and the pulse signal received from the capstan motor (CFG signal). An on-chip noise canceller is provided for the drum motor pulse signal (DFG signal). The CTL frequency divider generates a CTL divided control signal (DVCTL) from the PB-CTL signal, for use in capstan phase control during high-speed search, for example. The CFG frequency divider generates two divided signals (DVCFG for speed control and DVCFG2 for phase control) from the CFG signal. The DFG noise canceller is a circuit which considers a signal less than 2 as noise and masks it. 28.14.2 CTL Frequency Divider (1) Block Diagram Figure 28.63 shows a block diagram of the CTL frequency divider. Internal bus R/W * CTVC CEG R/W * CTVC CEX W * CTLR CTL division register (8 bits) EXCTL PB-CTL Edge detector , Down counter (8 bits) UDF DVCTL Figure 28.63 CTL Frequency Divider Rev.3.00 Jan. 10, 2007 page 766 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Register Configuration Register Configuration Table 28.22 shows the register configuration of the CTL dividers. Table 28.22 Register Configuration Name DVCTL control register CTL division register Abbrev. CTVC CTLR R/W R/W W Size Byte Byte Initial Value Undefined H'00 Address H'FD098 H'FD099 DVCTL Control Register (CTVC) Bit : 7 CEX 6 CEG 0 W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 CFG * R 1 HSW * R 0 CTL * R Initial value : 0 W R/W : Note: * Undefined. The DVCTL control register (CTVC) is a register consisting of the external input signal selection bit and the flags which show the CFG, HSW, and CTL levels. Note: It has an undetermined value by a reset or stand-by. Bit 7DVCTL Signal Generation Selection Bit (CEX): Selects whether the PB-CTL signal or the external input signal is used to generate the DVCTL signal. Bit 7 CEX 0 1 Description Generates DVCTL signal with PB-CTL signal Generates DVCTL signal with external input signal (Initial value) Bit 6External Sync Signal Edge Selection Bit (CEG): Selects the edge of the external signal at which the frequency division is made when the external signal was selected to generate the DVCTL signal. Bit 6 CEG 0 1 Description Rising edge Falling edge Rev.3.00 Jan. 10, 2007 page 767 of 1038 REJ09B0328-0300 (Initial value) Section 28 Servo Circuits Bits 5 to 3Reserved: No write in them is valid. If a read is attempted, an undetermined value is read out. Bit 2CFG Flag (CFG): Shows the CFG level. Bit 2 CFG 0 1 Description CFG is at Low level CFG is at High level (Initial value) Bit 1HSW Flag (HSW): Shows the level of the HSW signal selected by the VFF/NFF bit of the HSW mode register 2 (HSM2). Bit 1 HSW 0 1 Description HSW is at Low level HSW is at High level (Initial value) Bit 0CTL Flag (CTL): Shows the CTL level. Bit 0 CTL 0 1 Description REC or PB-CTL is at Low level REC or PB-CTL is at High level (Initial value) CTL Frequency Division Register (CTLR) Bit : Initial value : R/W : 7 CTL7 0 W 6 CTL6 0 W 5 CTL5 0 W 4 CTL4 0 W 3 CTL3 0 W 2 CTL2 0 W 1 CTL1 0 W 0 CTL0 0 W The CTL frequency division register (CTLR) is an 8-bit write-only register to set the frequency dividing value (N-1 if divided by N) for PB-CTL. If a read is attempted, an undetermined value is read out. PB-CTL is divided by N at its rising edge. If the register value was 0, no division operation is performed, and the DVCTL signal with the same cycle with PB-CTL is output. It is initialized to H'00 by a reset or stand-by. Rev.3.00 Jan. 10, 2007 page 768 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) Operation During playback, control pulses recorded on the tape are picked up by the control head and input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier, reshaped, then input to the CTL frequency divider as the PB-CTL signal. This circuit is employed when the control pulse (PB-CTL signal) is used for phase control of the capstan motor. The divided signal is sent as the DVCTL signal to the capstan phase system in the servo circuits, and the Timer R. The CTL frequency divider is an 8-bit reload timer consisting of a reload register and a downcounter. Frequency division is obtained by setting frequency-division data in bits 7 to 0 in the CTL frequency division register (CTLR), which is the reload register. When a frequency-division value is written in this reload register, it is also written into the down-counter. The down-counter is decremented on rising edges of the PB-CTL signal. Figure 28.64 shows examples of the PB-CTL signal and DVCTL waveforms. CTL input signal PB-CTL or external sync signal CTLR = 00 CTLR = 01 CTLR = 02 Legend: CTLR : CTL frequency division register Figure 28.64 CTL Frequency DivIsion Waveforms Rev.3.00 Jan. 10, 2007 page 769 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.14.3 CFG Frequency Divider (1) Block Diagram Figure 28.65 shows a block diagram of the 7-bit CFG frequency divider and its mask timer. Internal bus R/W * CDVC CRF CDIVR (7 bits) W R/W W * CDVC MCGin Edge select , * CDVC CMN CFG Down counter (7 bits) UDF DVCFG UDF Down counter (7 bits) S CMK R DVCFG2 PB(ASM)REC * CDVC CDIVR2 (7 bits) s/1024 s/512 s/256 s/128 DVTRG Down counter (6 bits) UDF * CDVC CFG clock select CTMR (6 bits) W R/W W W Internal bus R s = fosc/2 Figure 28.65 CFG Frequency Divider Rev.3.00 Jan. 10, 2007 page 770 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Register Descriptions Register configuration Table 28.23 shows the register configuration of the CFG frequency divider. Table 28.23 Register Configuration Name DVCFG control register CFG frequency division register 1 CFG frequency division register 2 DVCFG mask period register Abbrev. CDVC CDIVR1 CDIVR2 CTMR R/W R/W W W W Size Byte Byte Byte Byte Initial Value H'60 H'80 H'80 H'FF Address F'FD09A H'FD09B H'FD09C H'FD09D DVCFG Control Register (CDVC) Bit : 7 MCGin 6 -- 5 CMK 1 R 4 CMN 0 W 3 DVTRG 0 W 2 CRF 0 W 1 CPS1 0 W 0 CPS0 0 W Initial value : 0 1 -- R/W* R/W : Note: * Only 0 can be written. CDVC is an 8-bit register to control the capstan frequency division circuit. It is initialized to H'60 by a reset, stand-by or module stop. Bit 7Mask CFG Flag (MCGin): MCGin is a flag to indicate occurrence of a frequency division signal during the mask timer's mask period. To clear it, write 0. To clear it by software, write 0 after reading 1. Also, setting has the highest priority in this flag. If a condition setting the flag and 0 write occurs simultaneously, the latter is nullified. Bit 7 MCGin 0 1 Description CFG is in normal operation Shows that DVCFG was detected during masking (runaway detected) (Initial value) Bit 6Reserved: No write in it is valid. If a read is attempted, 1 is read out. Rev.3.00 Jan. 10, 2007 page 771 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 5CFG Mask Status Bit (CMK): Indicates the status of the mask. It is initialized to 1 by a reset, stand-by or module stop. Bit 5 CMK 0 1 Description Indicates that the capstan mask timer has released masking Indicates that the capstan mask timer is currently masking (Initial value) Bit 4CFG Mask Selection Bit (CMN): Selects the turning ON/OFF of the mask function. Bit 4 CMN 0 1 Description Capstan mask timer function ON Capstan mask timer function OFF (Initial value) Bit 3PB (ASM) REC Transition Timing Sync ON/OFF Selection Bit (DVTRG): Selects the ON/OFF of the timing sync of the transition from PB (ASM) to REC when the DVCFG2 signal is generated. Bit 3 DVTRG 0 1 Description PB (ASM) REC transition timing sync ON PB (ASM) REC transition timing sync OFF (Initial value) Bit 2CFG Frequency Division Edge Selection Bit (CRF): Selects the edge of the CFG signal to be divided. Bit 2 CRF 0 1 Description Performs frequency division at the rising edge of CFG Performs frequency division at both edges of CFG (Initial value) Rev.3.00 Jan. 10, 2007 page 772 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bits 1 and 0CFG Mask Timer Clock Selection Bits (CPS1, CPS0): Selects the clock source for the CFG mask timer. (s = fosc/2) Bit 1 CPS1 0 Bit 0 CPS0 0 1 1 0 1 Description s/1024 s/512 s/256 s/128 (Initial value) CFG Frequency Division Register 1 (CDIVR1) Bit : Initial value : R/W : 7 -- 1 -- 6 CDV16 0 W 5 CDV15 0 W 4 CDV14 0 W 3 CDV13 0 W 2 CDV12 0 W 1 CDV11 0 W 0 CDV10 0 W The CFG frequency division register 1 (CDIVR1) is an 8-bit write-only register to set the CFG division value (N-1 for N division). If a read is attempted, an undetermined value is read out. Bit 7 is reserved. The frequency division value is written in the reload register and the down counter at the same time. CFG's frequency is divided by N at its rising edge or both edges. If the register value was 0, no division operation is performed, and the DVCFG signal with the same input cycle with the CFG signal is output. The DVCFG signal is sent to the capstan speed error detector. It is initialized to H'80 by a reset or stand-by together with the capstan frequency division register and the down counter. CFG Frequency Division Register 2 (CDIVR2) Bit : Initial value : R/W : 7 -- 1 -- 6 CDV26 0 W 5 CDV25 0 W 4 CDV24 0 W 3 CDV23 0 W 2 CDV22 0 W 1 CDV21 0 W 0 CDV20 0 W The CFG frequency division register 2 (CDIVR2) is an 8-bit write-only register to set the CFG division value (N-1 for N division). If a read is attempted, an undetermined value is read out. Bit 7 is reserved. The frequency division value is written in the reload register and the down counter at the same time. Rev.3.00 Jan. 10, 2007 page 773 of 1038 REJ09B0328-0300 Section 28 Servo Circuits CFG's frequency is divided by N at its rising edge or both edges. If the register value was 0, no division operation is performed, and the DVCFG signal with the same input cycle with the CFG signal is output. The DVCFG2 signal is sent to the capstan speed error detector and the Timer L. The DVCFG2 circuit has no mask timer function. The frequency division counter for the DVCFG2 signal starts its division operation at the point data was written in CDIVR2. If synchronization is required for phase matching, for example, do it by writing in CDIVR2. If the DVTRG bit of the CDVC register was 0, the register synchronizes with the switching timing from PB (ASM) to REC. It is initialized to H'80 by a reset or stand-by together with the capstan frequency division register and the down counter. DVCFG mask period register (CTMR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 CPM5 1 W 4 CPM4 1 W 3 CPM3 1 W 2 CPM2 1 W 1 CPM1 1 W 0 CPM0 1 W The DVCFG mask period register (CTMR) is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. CTMR is a reload register for the mask timer (down counter). Set in it the mask period of CFG. The mask period is determined by the clock specified by bits 1 and 0 of CDVC and the set value (N-1). If data is written in CTMR, it is written also in the mask timer at the same time. It is initialized to H'FF by a reset, stand-by or module stop. Mask period = N x clock cycle Rev.3.00 Jan. 10, 2007 page 774 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) Operation Frequency divider The CFG pulses output from the capstan motor are sent to internal circuitry as the CFG signal via the zero-cross type comparator. The CFG signal, shaped into a rectangular waveform by a reshaping circuit, is divided by the CFG frequency dividers, and used in servo control. The rising edge or both edges of the CFG signal can be selected for the frequency divider. The CFG frequency dividers comprises a 7-bit frequency divider with a mask timer for capstan speed control (DVCFG signal generator) and a 7-bit frequency divider for capstan phase control (DVCFG2 signal generator). The DVCFG signal generator consists of a 7-bit reload register (CFG frequency division register1: CDIVR1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask interval). Frequency division is performed by setting the frequency-division value in 7-bit CDIVR1. When the frequency-division value is written in CDIVR1, it is also written in the down-counter. After frequency division of a CFG signal for which the edge has been selected, the signal is sent via the mask timer to the capstan speed error detector as the DVCFG signal. The DVCFG2 signal generator consists of a 7-bit reload register (CFG frequency division register 2: CDIVR2) and a 7-bit down-counter. The 7-bit frequency divider does not have a mask timer. Frequency division is performed by setting the frequency-division value in CDIVR2. When the frequency-division value is written in CDIVR2, it is also written in the down-counter. After frequency division of a CFG signal for which the edge has been selected, the signal is sent to the capstan speed error detector and the Timer L as the DVCFG2 signal. Frequency division starts when the frequency-division value is written. When the DVTRG bit in the CDVC register is set to 0, reloading is executed with the switchover timing from PB (ASM) mode to REC mode. To switch from REF30 to CREF, change the settings of bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR). If synchronization is necessary for phase control, this can be provided by writing the frequencydivision value in CDIVR2. The down-counters are decremented on rising edges of the CFG signal when the CRF bit is 0 in the DVCFG control register (CDVC), and on both edges when the CRF bit is 1. Figure 28.66 shows examples of CFG frequency division waveforms. Rev.3.00 Jan. 10, 2007 page 775 of 1038 REJ09B0328-0300 Section 28 Servo Circuits CFG CRF bit = 1 CDIVR = 00 CRF bit = 0 CDIVR = 00 CRF bit = 0 CDIVR = 01 CRF bit = 0 CDIVR = 02 Figure 28.66 Frequency DivIsion Waveforms Mask timer The capstan mask timer is a 6-bit reload timer that uses a prescaled clock as a clock source. The mask timer is used for masking the DVCFG signal intended for controlling the capstan speeds. The capstan mask timer prevents edge detection to be carried out for an unnecessarily long duration by masking the edge detection for a certain period. The above trouble can result from abnormal revolution (runout) of the capstan motor because its revolution has to cover a wide range speeds from the slow/still up to the high speed search. The capstan mask timer is started by output of a pulse edge in the divided CFG signal (DVCFG). While the timer is running, a mask signal disables the output of further DVCFG pulses. The mask signal is shown in figure 28.67. The mask timer status can be recognized by reading the CMK flag in the DVCFG control register (CDVC). Rev.3.00 Jan. 10, 2007 page 776 of 1038 REJ09B0328-0300 Section 28 Servo Circuits DVCFG Mask Mask timer underflow Figure 28.67 Mask Signal Figures 28.68 and 28.69 show examples of CFG mask timer operations. CFG (racing) Edge detect Capstan motor mask timer Mask interval Mask interval DVCFG MCGin flag Cleared by writing 0 after reading 1 Figure 28.68 CFG Mask Timer Operation (When Capstan Motor Is Racing) Rev.3.00 Jan. 10, 2007 page 777 of 1038 REJ09B0328-0300 Section 28 Servo Circuits CFG Edge detect Capstan motor mask timer Mask interval Mask interval Figure 28.69 CFG Mask Timer Operation (When Capstan Motor Is Operating Normally) 28.14.4 DFG Noise Removal Circuit (1) Block Diagram Figure 28.70 shows the block diagram of the DFG noise removal circuit. Edge detection Delay circuit delay = 2 Edge detection DFG S R Q NCDFG Figure 28.70 DFG NoIse Removal Circuit (2) Register Descriptions Register configuration Table 28.24 shows the register configuration of the DFG mask circuit. Table 28.24 Register Configuration Name FG control register Abbrev. FGCR R/W W Size Byte Initial Value H'FE Address H'FD09E Rev.3.00 Jan. 10, 2007 page 778 of 1038 REJ09B0328-0300 Section 28 Servo Circuits FG Control Register (FGCR) Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 DRF 0 W Selects the edge of the DFG noise removal signal (NCDFG) to be sent to the drum speed error detector. If a read is attempted, an undetermined value is read out. Bits 7 to 1 are reserved. No write in them is valid. It is initialized to H'FE by a reset, stand-by or module stop. The edge selection circuit is located in the drum speed error detector, and outputs the register output to the drum speed error detector. Bits 7 to 1Reserved: No write in them is valid. If a read is attempted, an undetermined value is read out. Bit 0DFG Edge Selection Bit (DRF): Selects the edge of the NCDFG signal used in the drum speed error detector. Bit 0 DRF 0 1 Description Selects the rising edge of NCDFG signal Selects the falling edge of NCDFG signal (Initial value) Rev.3.00 Jan. 10, 2007 page 779 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) Description of Operation The DFG noise removal circuits generates a signal (NCDFG signal) with a delay circuit as a result of removing noise (signal fluctuation smaller than 2 ) from the DFG signal. The resulted NCDFG signal is behind the time when the DFG signal was detected by 2 . Figure 28.71 shows the NCDFG signal. Noise DFG NCDFG 2 2 2 = fosc Figure 28.71 NCDFG Signal Rev.3.00 Jan. 10, 2007 page 780 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.15 Sync Signal Detector 28.15.1 Overview This block performs detection of the horizontal sync signal (Hsync) and vertical sync signal (Vsync) from the composite sync signal (Csync), noise counting, and field detection. It detects the horizontal and vertical sync signals by setting threshold in the register and based on the servo clock (s = fosc/2). Noise masking is possible during the detection of the horizontal sync signals, and if any Hsync is missing, it can be supplemented. Also, if total volume of the noise detected in one frame of Csync amounted over a specified volume, the detector generates a noise detection interrupt. Note: This circuit detects a pulse with a specific width set by the threshold register. It does not classify or restore the sync signal to a formal one. 28.15.2 Block Diagram Figure 28.72 shows the block diagram of the sync signal detector. Rev.3.00 Jan. 10, 2007 page 781 of 1038 REJ09B0328-0300 Internal bus W R/W * SYNCR NOIS FLD SYCT NIS/VD Noise detection interrupt W W R/W W W W R/(W) R * VTR Section 28 Servo Circuits V threshold register (4 bits) (8 bits) (4 bits) (6 bits) (8 bits) * HTR * HRTR * HPWR * NWR H supplement Supplemented Noise detection H threshold H pulse width start time window register register register register * NDR Noise detection register (6 bits) IRRSNC VD interrupt Rev.3.00 Jan. 10, 2007 page 782 of 1038 REJ09B0328-0300 NOISE Noise detector Noise detection window Csync Field detector FILED Selection of polarity VD(SEPV) Sync signal detector SEPH Supplement control & noise mask control circuit OSCH Figure 28.72 Block Diagram of the Sync Signal Detector Up/Down counter (6 bits) H counter (8 bits) Noise counter (10 bits) Clear Toggle circuit H reload counter (8 bits) s/2 s = fosc/2 Section 28 Servo Circuits 28.15.3 Pin Configuration Table 28.25 shows the pin configuration of the sync signal detector. Table 28.25 Pin Configuration Name Composite sync signal input pin Abbrev. Csync I/O Input Function Composite sync signal input 28.15.4 Register Configuration Table 28.26 shows the register configuration of the sync signal detector. Table 28.26 Register Configuration Name Vertical sync signal threshold register Horizontal sync signal threshold register H supplement start time setting register Supplemented H pulse width setting register Noise detection window setting register Noise detector register Abbrev. VTR HTR HRTR HPWR NWR NDR R/W W W W W W W R/W Size Byte Byte Byte Byte Byte Byte Byte Initial Value H'C0 H'F0 H'00 H'F0 H'C0 H'00 H'F8 Address H'FD0B0 H'FD0B1 H'FD0B2 H'FD0B3 H'FD0B4 H'FD0B5 H'FD0B6 Sync signal control register SYNCR Rev.3.00 Jan. 10, 2007 page 783 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.15.5 Register Descriptions (1) Vertical Sync Signal Threshold Register (VTR) Bit : Initial value : R/ W : 7 -- 1 -- 6 -- 1 -- 5 VTR5 0 W 4 VTR4 0 W 3 VTR3 0 W 2 VTR2 0 W 1 VTR1 0 W 0 VTR0 0 W Sets the threshold for the vertical sync signal when the signal is detected from the composite sync signal. The threshold is set by bits 5 to 0 (VTR5 to VTR0). Bits 7 and 6 are reserved. VTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset, stand-by or module stop. (2) Horizontal Sync Signal Threshold Register (HTR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 HTR3 0 W 2 HTR2 0 W 1 HTR1 0 W 0 HTR0 0 W Sets the threshold for the horizontal sync signal when the signal is detected from the composite sync signal. The threshold is set by bits 3 to 0 (HTR3 to HTR0). Bits 7 and 4 are reserved. HTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'F0 by a reset, stand-by or module stop. Figure 28.73 shows threshold and separated sync signals. Rev.3.00 Jan. 10, 2007 page 784 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Hpuls 1/2 Hpuls Hpuls Csync TH Counter value H'00 VVTH HVTH TH SEPH SEPV VD interrupt Legend: TH : Cycle of the horizontal sync signal (NTSC: 63.6, PAL: 64 [s]) Hpuls : Pulse width of the horizontal sync signal (NTSC, PAL: 4.7 [s]) VVTH : Value set as the threshold of the vertical sync signal HVTH : Value set as the threshold of the horizontal sync signal SEPV : Detected vertical sync signal SEPH : Detected horizontal sync signal (before supplement) Figure 28.73 Threshold and Separated Sync Signals Example The set values to detect the vertical and horizontal sync signals (SEPV and SEPH) from Csync are required to meet the following conditions. Assumed that the set values in the VTHR register were VVTH and HVTH, (VVTH - 1) x 2/s > Hpuls (HVTH - 2) x 2/s Hpuls/2 < (HVTH - 1) ) x 2/s Where, Hpuls is pulse width (s) of the horizontal sync signal, and s is servo clock (fosc/2). Thus, if s = 5 MHz, NTSC system is used, (VVTH - 1) x 0.4s > 4.7s VVTH H'D (HVTH - 2) x 0.4s 2.35s < (HVTH - 1) x 0.4s HVTH H'7 Note: This circuits detects the pulse with the width set in the VTHR register. If a noise pulse with the width greater than the set value was input, the circuit regards that it detected a sync signal. Rev.3.00 Jan. 10, 2007 page 785 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (3) H Supplement Start Time Setting Register (HRTR) Bit : Initial value : R/W : 7 HRTR7 0 W 6 HRTR6 0 W 5 HRTR5 0 W 4 HRTR4 0 W 3 HRTR3 0 W 2 HRTR2 0 W 1 HRTR1 0 W 0 HRTR0 0 W Sets the timing to generate a supplementary pulse if a drop-out of a pulse of the horizontal sync signal occurred. HRTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. ((Value of HRTR7 to HRTR0) + 1) x 2/s = TH where, TH is the cycle of the horizontal sync signal (s), and s is the servo clock (fosc/2). Whether the horizontal sync signal exists or not is determined one clock before the supplementary pulse is generated. Accordingly, set to HRTR7 to HRTR0 a value obtained from the equation shown above plus one. Also, HRTR7 to HRTR0 set the noise mask period. If the horizontal sync signal had the normal pulses, it is masked in the mask period. The start and end of the mask period are computed frm the rising edge of OSCH and SEPH, respectively. See figure 28.75. (4) Supplemented H Pulse Width Setting Register (HPWR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 HPWR3 0 W 2 HPWR2 0 W 1 HPWR1 0 W 0 HPWR0 0 W HPWR sets the pulse width of the supplemented pulse which is generated if a drop-out of a pulse of the horizontal sync signal occurs. Bits 7 to 4 are reserved. HRWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'F0 by a reset or stand-by. ((Value of HPWR3 to HPWR0) + 1) x 2/s = Hpulse Where, Hpuls is the pulse width of the horizontal sync signal (s), and s is the servo clock (fosc/2). Rev.3.00 Jan. 10, 2007 page 786 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (5) Noise Detection Window Setting Register (NWR) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 NWR5 0 W 4 NWR4 0 W 3 NWR3 0 W 2 NWR2 0 W 1 NWR1 0 W 0 NWR0 0 W NWR sets the period (window) when the drop-out of the pulse of the horizontal sync signal is detected and the noise is counted. Set the timing of the noise detection window in bits 5 to 0. Bits 7, and 6 are reserved. NWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset, stand-by or module stop. Set the value of the noise detection window timing according to the following equation. ((Value of NWR5 to NWR0) + 1) x 2/s = 1/4 x TH Where, TH is the pulse width of the horizontal sync signal (s), and s is the servo clock (fosc/2). It is recommended that this timing value is set at about 1/4 of the cycle of the horizontal sync signal. (6) Noise Detection Register (NDR) Bit : Initial value : R/W : 7 NDR7 0 W 6 NDR6 0 W 5 NDR5 0 W 4 NDR4 0 W 3 NDR3 0 W 2 NDR2 0 W 1 NDR1 0 W 0 NDR0 0 W NDR sets the noise detection level when the noise of the horizontal sync signal is detected (when NWR is set). Set the noise detection level in bits 7 to 0. NDR is an 8-bit write-only register. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. The noise detector takes counts of the drop-outs of the horizontal sync signals and the noises within the pulses, and if they amount to a count greater than four times of the value set in NDR7 to NDR0, the detector sets the NOIS flag in the sync signal control register (SYNCR). Set the noise detection level at 1/4 of the noise counts in one frame. The noise counter is cleared whenever Vsync was detected twice. See section 28.15.6, Noise Detection, for the details of the noise detection window and the noise detection level. Rev.3.00 Jan. 10, 2007 page 787 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (7) Sync Signal Control Register (SYNCR) Bit : 7 -- 6 -- 5 -- 1 -- 4 -- 1 -- 3 NIS/VD 1 R/W 2 NOIS 0 R/(W)* 1 FLD 0 R 0 SYCT 0 R/W Initial value : 1 1 -- -- R/W : Note: * Only 0 can be written SYNCR controls the noise detection, field detection, polarity of the sync signal input, etc. SYNCR is an 8-bit register. It is initialized to H'F8 by a reset, stand-by or module stop. Bits 7 to 4 are reserved. No write is valid. Bit 1 is valid for read only. Bits 7 to 4Reserved: Writes are disabled. If a read is attempted, an undetermined value is read out. Bit 3Interrupt Selection Bit (NIS/VD): Selects whether an interrupt request is generated when a noise level was detected or when the VD signal was detected. Bit 3 NIS/VD 0 1 Description Interrupt at the noise level Interrupt at VD (Initial value) Bit 2Noise Detection Flag (NOIS): NOIS is a status flag indicating that the noise counts reached at more than four times of the value set in NDR. The flag is cleared only by writing 0 after reading 1. Care is required because it is not cleared automatically. Bit 2 NOIS 0 1 Description Noise count is smaller than four times of the value set in NDR (Initial value) Noise count is equal to or greater than four times of the value set in NDR Bit 1Field Detection Flag (FLD): Indicates whether the field currently being scanned is even or odd. See figure 28.74. Bit 1 FLD 0 1 Description Odd field Even field (Initial value) Rev.3.00 Jan. 10, 2007 page 788 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 0Sync Signal Polarity Selection Bit (SYCT): Selects the polarity of the sync signal (Csync) to be input. Bit 0 SYCT 0 1 Description (Initial value) Polarity Positive Negative Composite sync signal (Csync) SEPV Noise detection window Field detection flag (FLD) Even field (a) Even field (EVEN) Composite sync signal (Csync) SEPV Noise detection window Field detection flag (FLD) Odd field (b) Odd field (ODD) Figure 28.74 Field Detection Rev.3.00 Jan. 10, 2007 page 789 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.15.6 Noise Detection If drop-out of a pulse of the horizontal sync signal occurred, set a supplemented pulse at the timing set in HPWR and with the set pulse width. Set the noise detection window with HWR of about 1/4 of the horizontal sync signal, and the pulse with equal High and Low periods will be obtained. (1) Example of Setting Assumed that a supplemented pulse is set when fosc = 10MHz under the conditions s = 5MHz, NTSC:TH = 63.6 (s) and Hpuls = 4.7 (s), the set values of the supplemented pulse timing (HRTR7-0), supplemented pulse width (HPWR3-0) and noise detection window timing (NWR50) are expressed by the following equations. (Value of HRTR7 - 0) x 2/s = TH ((Value of HPWR3 - 0) + 1) x 2/s = Hpuls ((Value of NWR5 - 0) + 1) x 2/s = 1/4 x TH Where, TH is the cycle of the horizontal sync signal (s), Hpuls is the pulse width of the horizontal sync signal (s) and s is the servo clock (Hz) (fosc/2). Accordingly, (Value of HRTR7 to HRTR0) x 0.4 (s) = 63.6 (s) HRTR7 - 0 = H'9F ((Value of HPWR3 to HPWR0) + 1) x 0.4 (s) = 4.7 (s) HPWR3 - 0 = H'B ((Value of NWR5 to NWR0) + 1) x 0.4 (s) = 16 (s) NWR5 - 0 = H'27 Also, the noise mask period is computed as follows. ((Value of HRTR7 to HRTR0) + 1) - 24) x 2/s = 54 (s) Where, 24 is a constant required for a structural reason. Figure 28.75 shows the set period for HRTR, HPWR, and NWR. Rev.3.00 Jan. 10, 2007 page 790 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Drop-out of the horizontal sync signal TH Ignore signal during noise mask period. TH SEPH c H counter a b H'00 OVF H'E8 a H reload counter c Mask period Mask period Don't mask immediately after supplement Mask period Mask period Noise mask for H counter TM OSCH Mask period Mask period Mask period Do mask also immediately after supplement. Mask period Noise mask for OSCH Noise detection window Period determined by NWR5 to NWR0 period determined by a and a Period determined by HRTR7 to HRTR0 period determined by c and H'E8 Period determined by HPWR3 to HPER0 period determined by b Legend: SEPH : Horizontal sync signal after detection OSCH : Horizontal sync signal after supplement a : Value set for the noise detection window (NWR5 to NWR0) b : Value set for the pulse width of the horizontal sync signal (NPWR3 to NPWR0) c : Value set for supplement timing (HRTR7 to HRTR0) a, b, c : Complements of 1 of a,b,c, respectively H ' E 8 :Complement of 2 of multiplier 24 in the equation for the noise mask period (The noise mask period ends 24 counts before the overflow of H reload counter.) : Cycle of the horizontal sync signal TH (NTSC:63.6 [ms], PAL:64[ms]) TM : Timing at which the noise mask period ends. Figure 28.75 Set Period for HRTR, HPWR and NWR Rev.3.00 Jan. 10, 2007 page 791 of 1038 REJ09B0328-0300 Section 28 Servo Circuits (2) Operation to Detect Noise The noise detector considers an irregular pulse of the composite sync signal (Csync) and a chip of a pulse of the horizontal sync signal within a frame as noise. The noise counter takes counts of the irregular pulses during the High period of the noise detection window and the chips and drop-outs of the horizontal sync signal pulses during the Low period. Also, it counts more than one irregular pulses as one. The noise counter is cleared at every frame (Vsync is detected twice). The equivalent pulse contained in 9H of the vertical sync signal is counted also as an irregular pulse. It sets the noise detection flag (NOIS) in the sync signal control register (SYNCR) at 1 if the count of the irregular pulses + the count of the pulse chips and drop-outs of the horizontal sync signal > 4 x (value of NDR7 to NDR0). See section 28.15.5 (7), Sync Signal Control Register (SYNCR), for the NOIS bit. Figure 28.76 shows the operation of the noise detection. Noise Csync Noise detection window Noise detection level Noise counter Noise detection flag is set. Noise detection flag (NOIS) NOIS : Bit 2 of the sync signal control register (SYNCR) Figure 28.76 Operation of the NoIse Detection Rev.3.00 Jan. 10, 2007 page 792 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.15.7 Sync Signal Detector Activation The sync signal detector starts operation by release of reset, or by accepting input of a sync signal after its transition from power-down mode to active mode and release of module stop. The signal given to the detector is the polarity pulse assigned by the SYCT bit of the sync signal control register (SYNCR). The detector starts operation even if this pulse was a noise pulse with a width short of the regular width. The minimum pulse width which can activate the detector is not constant depending on the internal operation of the input circuit. Accordingly, if the assured activation of the detector is required, input a pulse with a width greater than 4/s (s = fosc/2 (Hz)). In such a case, care is required to noise, etc., because even a pulse with a width smaller than 4/s may cause activation. Rev.3.00 Jan. 10, 2007 page 793 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.16 Servo Interrupt 28.16.1 Overview The interrupt exception processing of the servo module is started by one of ten factors, i.e. the drum speed error detector (x2), drum phase error detector, capstan speed error detector (x2), capstan phase error detector, HSW timing generator (x2), sync detector and CTL circuit. For these interrupt factors, see each of their circuit sections in this manual. Also, see section 5, Exception Handling. 28.16.2 Register Configuration Table 28.27 shows the list of the registers which control the interrupt of the servo section. Table 28.27 Registers which Control the Interrupt of the Servo Section Name Abbrev. R/W R/W R/W R/W R/W Size Byte Byte Byte Byte Initial Value H'00 H'FC H'00 H'FC Address H'FD0B8 H'FD0B9 H'FD0BA H'FD0BB Servo interrupt permission SIENR1 register 1 Servo interrupt permission SIENR2 register 2 Servo interrupt request register 1 Servo interrupt request register 2 SIRQR1 SIRQR2 28.16.3 Register Description (1) Servo Interrupt Permission Register 1 (SIENR1) Bit : Initial value : R/W : 7 IEDRM3 0 R/W 6 IEDRM2 0 R/W 5 IEDRM1 0 R/W 4 IECAP3 0 R/W 3 IECAP2 0 R/W 2 IECAP1 0 R/W 1 IEHSW2 0 R/W 0 IEHSW1 0 R/W SIENR1 controls the permission and prohibition of the interrupt of the servo section. SIENR1 is an 8-bit readable/writable register. It is initialized to H'00 by a reset, stand-by or module stop. Rev.3.00 Jan. 10, 2007 page 794 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 7Drum Phase Error Detection Interrupt Permission Bit (IEDRM3) Bit 7 IEDRM3 0 1 Description Prohibits the interrupt request through IRRDRM3 Permits the interrupt request through IRRDRM3 (Initial value) Bit 6Drum Speed Error Detection (Lock Detection) Interrupt Permission Bit (IEDRM2) Bit 6 IEDRM2 0 1 Description Prohibits the interrupt request through IRRDRM2 Permits the interrupt request through IRRDRM2 (Initial value) Bit 5Drum Speed Error Detection (OVF, Latch) Interrupt Permission Bit (IEDRM1) Bit 5 IEDRM1 0 1 Description Prohibits the interrupt request through IRRDRM1 Permits the interrupt request through IRRDRM1 (Initial value) Bit 4Capstan Phase Error Detection Interrupt Permission Bit (IECAP3) Bit 4 IECAP3 0 1 Description Prohibits the interrupt request through IRRCAP3 Permits the interrupt request through IRRCAP3 (Initial value) Bit 3Capstan Speed Error Detection (Lock Detection) Interrupt Permission Bit (IECAP2) Bit 3 IECAP2 0 1 Description Prohibits the interrupt request through IRRCAP2 Permits the interrupt request through IRRCAP2 (Initial value) Rev.3.00 Jan. 10, 2007 page 795 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 2Capstan Speed Error Detection (OVF, Latch) Interrupt Permission Bit (IECAP1) Bit 2 IECAP1 0 1 Description Prohibits the interrupt request through IRRCAP1 Permits the interrupt request through IRRCAP1 (Initial value) Bit 1HSW Timing Generation (Counter Clear, Capture) Interrupt Permission Bit (IEHSW2) Bit 1 IEHSW2 0 1 Description Prohibits the interrupt request through IRRHSW2 Permits the interrupt request through IRRHSW2 (Initial value) Bit 0HSW Timing Generation (OVW, Matching, STRIG) Interrupt Permission Bit (IEHSW1) Bit 0 IEHSW1 0 1 Description Prohibits the interrupt request through IRRHSW1 Permits the interrupt request through IRRHSW1 (Initial value) (2) Servo Interrupt Permission Register 2 (SIENR2) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 IESNC 0 R/W 0 IECTL 0 R/W SIENR2 controls the permission and prohibition of the interrupt of the servo section. SIENR2 is an 8-bit readable/writable register. It is initialized to H'FC by a reset, stand-by or module stop. Bits 7 to 2Reserved: No read or write is valid. If a read is attempted, an undetermined value is read out. Rev.3.00 Jan. 10, 2007 page 796 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 1Vertical Sync Signal Interrupt Permission Bit (IESNC) Bit 1 IESNC 0 1 Description Prohibits the interrupt (interrupt to the vertical sync signal) request through IRRSNC (Initial value) Permits the interrupt request through IRRSNC Bit 0CTL Interrupt Permission Bit (IECTL) Bit 0 IECTL 0 1 Description Prohibits the interrupt request through IRRCTL Permits the interrupt request through IRRCTL (Initial value) (3) Servo Interrupt Request Register 1 (SIRQR1) Bit : 7 6 5 4 3 2 1 0 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Initial value : 0 0 0 0 R/W : R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. SIRQR1 displays an occurrence of an interrupt request of the servo section. If the interrupt request occurred, the corresponding bit is set to 1. SIRQR1 is an 8-bit readable/writable register. Writing is allowed only in the case of writing 0 to clear the flag. It is initialized to H'00 by a reset, stand-by or module stop. Bit 7Drum Phase Error Detector Interrupt Request Bit (IRRDRM3) Bit 7 IRRDRM3 0 1 Description No interrupt request from the drum phase error detector Interrupt requested from the drum phase error detector (Initial value) Rev.3.00 Jan. 10, 2007 page 797 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 6Drum Speed Error Detector (Lock Detection) Interrupt Request Bit (IRRDRM2) Bit 6 IRRDRM2 0 1 Description No interrupt request from the drum speed error detector (lock detection) (Initial value) Interrupt requested from the drum speed error detector (lock detection) Bit 5Drum Speed Error Detector (OVF, Latch) Interrupt Request Bit (IRRDRM1) Bit 5 IRRDRM1 0 1 Description No interrupt request from the drum speed error detector (OVF, latch) Interrupt requested from the drum speed error detector (OVF, latch) (Initial value) Bit 4Capstan Phase Error Detector Interrupt Request Bit (IRRCAP3) Bit 4 IRRCAP3 0 1 Description No interrupt request from the capstan phase error detector Interrupt requested from the capstan phase error detector (Initial value) Bit 3Capstan Speed Error Detector (Lock Detection) Interrupt Request Bit (IRRCAP2) Bit 3 IRRCAP2 0 1 Description No interrupt request from the capstan speed error detector (lock detection) (Initial value) Interrupt requested from the drum speed error detector (lock detection) Bit 2Capstan Speed Error Detector (OVF, Latch) Interrupt Request Bit (IRRCAP1) Bit 2 IRRCAP1 0 1 Description No interrupt request from the capstan speed error detector (OVF, latch) (Initial value) Interrupt requested from the capstan speed error detector (OVF, latch) Rev.3.00 Jan. 10, 2007 page 798 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 1HSW Timing Generator (Counter Clear, Capture) Interrupt Permission Bit (IRRHSW2) Bit 1 IRRHSW2 0 1 Description No interrupt request from the HSW timing generator (counter clear, capture) (Initial value) Interrupt requested from the HSW timing generator (counter clear, capture) Bit 0HSW Timing Generator (OVW, Matching, STRIG) Interrupt Permission Bit (IRRHSW1) Bit 0 IRRHSW1 0 1 Description No interrupt request from the HSW timing generator (OVW, matching, STRIG) (Initial value) Interrupt requested from the HSW timing generator (OVW, matching, STRIG) (4) Servo Interrupt Request Register 2 (SIRQR2) Bit : Initial value : 7 -- 6 -- 5 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 IRRSNC 0 R/(W)* 0 IRRCTL 0 R/(W)* 1 1 1 -- -- -- R/W : Note: * Only 0 can be written to clear the flag. SIRQR2 displays an occurrence of an interrupt request of the servo section. If the interrupt request occurred, the corresponding bit is set to 1. SIRQR2 is an 8-bit readable/writable register. Writing 0 after reading 1 is allowed; no other writing is allowed. It is initialized to H'FC by a reset, stand-by or module stop. Bits 7 to 2Reserved: No read or write is valid. If a read is attempted, an undetermined value is read out. Rev.3.00 Jan. 10, 2007 page 799 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Bit 1Vertical Sync Signal Interrupt Request Bit (IRRSNC) Bit 1 IRRSNC 0 1 Description No interrupt request from the sync signal detector (VD, noise) Interrupt requested from the sync signal detector (VD, noise) (Initial value) Bit 0CTL Signal Interrupt Request Bit (IRRCTL) Bit 0 IRRCTL 0 1 Description No interrupt request from CTL Interrupt requested from CTL (Initial value) Rev.3.00 Jan. 10, 2007 page 800 of 1038 REJ09B0328-0300 Section 28 Servo Circuits 28.17 Module Stop Control Reigster (MSTPCR) MSTPCRH Bit : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, that perform module stop mode control. When the MSTP1 bit is set to 1, servo circuit and 12-bit PWM stop the operation at the end of the bus cycle and enter to the module stop mode. For details, see 4.5 Module stop mode. MSTPCR is initialized to H'FFFF by a reset. Bit 1Module Stop 1 (MSTP1): This bit specifies module stop mode of the servo circuit and 12bit PWM. MSTPCRL Bit 1 MSTP1 0 1 Description Clear the module stop mode of the Servo Circuit and 12-bit PWM Set the module stop mode of the Servo Circuit and 12-bit PWM (Initial value) Rev.3.00 Jan. 10, 2007 page 801 of 1038 REJ09B0328-0300 Section 28 Servo Circuits Rev.3.00 Jan. 10, 2007 page 802 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Section 29 Electrical Characteristics 29.1 Absolute Maximum Ratings Table 29.1 lists the absolute maximum ratings. Table 29.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (ports other than port 0) Input voltage (port 0) A/D converter power supply voltage A/D converter input voltage Servo power supply voltage Servo amplifier input voltage Operating temperature Operating temperature (At Flash memory program/erase) Storage temperature Symbol Vcc Vin Vin AVcc AVin SVcc Vin Topr Topr Tstr Value -0.3 to +7.0 -0.3 to Vcc +0.3 -0.3 to AVcc +0.3 -0.3 to +7.0 -0.3 to AVcc +0.3 -0.3 to +7.0 -0.3 to SVcc +0.3 -20 to +75 0 to +75 -55 to +125 Unit V V V V V V V C C C Notes: 1. Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. All voltages are relative to Vss = SVss = AVss = 0.0 V. Rev.3.00 Jan. 10, 2007 page 803 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2 29.2.1 Electrical Characteristics of HD64F2194 DC Characteristics of HD64F2194 Table 29.2 DC Characteristics of HD64F2194 and HD64F2194C (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Input high voltage Symbol Applicable Pins VIH MD0 RES, NMI, FWE, IC, IRQ0 to IRQ5 Vcc = 2.7 V to 5.5 V SCK1, SCK2, SI1, SI2, CS, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, ADTRG OSC1, X1 Vcc = 2.7 V to 5.5 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Csync Test Conditions Min Vcc = 2.7 V to 5.5 V Typ Max Vcc +0.3 Vcc +0.3 Vcc +0.3 Vcc +0.3 Unit V Notes 0.9 Vcc 0.8 Vcc 0.9 Vcc 0.8 Vcc Vcc -0.5 Vcc -0.3 Vcc +0.3 Vcc +0.3 Vcc +0.3 Vcc +0.3 0.7 Vcc Vcc = 2.7 V to 5.5 V 0.8 Vcc 0.7 Vcc Vcc +0.3 Rev.3.00 Jan. 10, 2007 page 804 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Input low voltage Symbol Applicable Pins VIL MD0 RES, NMI, FWE, IC, IRQ0 to IRQ5 Test Conditions Min Vcc = 2.7 V to 5.5 V -0.3 -0.3 Vcc = 2.7 V to 5.5 V -0.3 -0.3 Typ Max Unit Notes 0.1 Vcc V 0.2 Vcc 0.1 Vcc 0.2 Vcc SCK1, SCK2, SI1, SI2, CS, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, ADTRG OSC1, X1 Vcc = 2.7 V to 5.5 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Csync Output high VOH voltage SO1, SO2, SCK1, SCK2, -IOH = 1.0 mA PWM1, PWM2, PWM3, PWM4, PWM14, STRB, -IOH = 0.5 mA BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to -IOH = 0.1 mA PPG77, Vcc = 2.7 V to RP0 to RP7, 5.5 V P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 -0.3 -0.3 -0.3 Vcc = 2.7 V to 5.5 V -0.3 0.5 0.3 0.3 Vcc 0.2 Vcc -0.3 Vcc -1.0 Vcc -0.5 Vcc -0.5 0.2 Vcc V V V Reference value Rev.3.00 Jan. 10, 2007 page 805 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Output low voltage Symbol Applicable Pins VOL Test Conditions Min Typ Max 0.6 0.4 Unit V Notes SO1, SO2, SCK1, IOL = 1.6 mA SCK2, PWM1, PWM2, IOL = 0.4 mA PWM3, PWM4, PWM14, Vcc = 2.7 V to STRB, BUZZ, TMO, 5.5 V TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, PS0 to PS4 P80 to P87, IOL = 20 mA IOL = 1.6 mA IOL = 0.4 mA Vcc = 2.7 V to 5.5 V 1.5 0.6 0.4 Input/output IIL leakage current MD0, OSC1 RES, NMI, FWE, IRQ0 to IRQ5, IC SCK1, SCK2, SI1, SI2, CS, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, ADTRG P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P53, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 P00 to P07, AN8 to ANB Vin = 0.5 V to Vcc -0.5 V 1.0 A Vin = 0.5 to Vcc -0.5 V 1.0 Vin = 0.5 to Vcc -0.5 V 1.0 Vin = 0.5 to AVcc -0.5 V 1.0 Rev.3.00 Jan. 10, 2007 page 806 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Symbol Applicable Pins P10 to P17, P20 to P27, P30 to P37, Test Conditions Min Vcc = 5.0 V, Vin = 0 V 50 Typ Max 300 Unit A Notes Note 1 Pull-up MOS -Ip current Input capaci- Cin tance fin = 1 MHz, All input pins except power supply, P13, P23, Vin = 0 V, P24 and analog system Ta = 25 C pins P13, P23, P24 fin = 1 MHz, Vin = 0 V, Ta = 25C Vcc = 5 V, fOSC = 10-MHz, High-speed mode Vcc = 5 V, fOSC = 10-MHz, Medium-speed mode (1/64) Vcc Vcc = 5 V, fOSC = 10 MHz 15 pF 20 Active mode IOPE current dissipation (CPU operating) Vcc 50 70 mA Note 2 35 Reference value Active mode IRES current dissipation (reset) Sleep mode ISLEEP current dissipa-tion Subactive ISUB mode current dissipation 30 45 mA Note 2 Vcc Vcc = 5 V, fOSC =10-MHz High-speed mode 20 30 Vcc Vcc = 2.7 V, With 32-kHz crystal oscillator ( sub = w/2) Vcc = 2.7 V, With 32-kHz crystal oscillator ( sub = w/8) 90 150 A Note 2 40 Reference value, Note 2 A Note 2 Subsleep ISUBSLP mode current dissipation Vcc Vcc = 2.7 V, With 32-kHz crystal oscillator ( sub = w/2) Vcc = 2.7 V, With 32-kHz crystal oscillator ( sub = w/8) 15 30 10 Reference value, Note 2 Rev.3.00 Jan. 10, 2007 page 807 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Symbol Applicable Pins Vcc Test Conditions Min Vcc = 2.7 V, With 32-kHz crystal oscillator Vcc = 5.0 V, With 32-kHz crystal oscillator ISTBY Standby mode current dissipation RAM data retaining voltage in standby mode VSTBY Vcc X1 = Vcc, Without 32-kHz crystal oscillator 2.0 Typ 5 Max 10 Unit A Notes Note 2 Watch mode IWATCH current dissipation 10 Reference value, Note 2 Note 2 5 V Notes: Do not open the AVcc and AVss pin even when the A/D converter is not in use. 1. Current value when the relevant bit of the pull-up MOS select register (PUR1 to PUR3) is set to 1. 2. The current on the pull-up MOS or the output buffer excluded. Table 29.3 Pin Status at Current Dissipation Measurement Mode Active mode High-speed, mediumspeed Sleep mode High-speed, mediumspeed Reset Standby mode Subactive mode Subsleep mode Watch mode RES pin Vcc Internal State Operating Pin Vcc Oscillator Pin Main clock: Crystal oscillator Sub clock: X1 pin = Vcc Vcc CPU and servo circuits stopped. Reset All stopped CPU and timer A operating Timer A operating Timer A operating Vcc Vss Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Main clock: Crystal oscillator Sub clock: Crystal oscillator Rev.3.00 Jan. 10, 2007 page 808 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Table 29.4 Bus Drive Characteristics of HD64F2194 and HD64F2194C (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable pin: SCL, SDA Applicable Test Symbol Pins Conditions - Values Min 0.2 Vcc Typ Max 0.7 Vcc Unit V V V Item Schmidt trigger input VT voltage + VT + SCL, SDA VT -VT- Input High voltage Input Low voltage VIH VIL SCL, SDA SCL, SDA SCL, SDA IOL = 8 mA IOL = 3 mA SCL and SDA output tof fall time SCL, SDA 0.05 Vcc 0.7 Vcc -0.5 20 + 0.1Cb Vcc +0.5 V 0.2 Vcc 0.5 0.4 250 ns V V Output Low voltage VOL Rev.3.00 Jan. 10, 2007 page 809 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2.2 Allowable Output Currents of HD64F2194 and HD64F2194C The specifications for the digital pins are shown below. Table 29.5 Allowable Output Currents of HD64F2194 and HD64F2194C (Conditions: Vcc = 2.7 V to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C) Item Allowable input current (to chip) Allowable input current (to chip) Allowable input current (to chip) Allowable output current (from chip) Total allowable input current (to chip) Total allowable output current (from chip) Symbol IO IO IO -IO IO -IO Value 2 22 10 2 80 50 Unit mA mA mA mA mA mA Notes 1 2 3 4 5 6 Notes: 1. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS (except for port 8, SCL and SDA). 2. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to port 8. 3. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to SCL and SDA. 4. The allowable output current is the maximum value of the current flowing from VCC to each I/O pin. 5. The total allowable input current is the sum of the currents flowing from all I/O pins to VSS simultaneously. 6. The total allowable output current is the sum of the currents flowing from VCC to all I/O pins. Rev.3.00 Jan. 10, 2007 page 810 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2.3 AC Characteristics of HD64F2194 and HD64F2194C Table 29.6 AC Characteristics of HD64F2194 and HD64F2194C (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable Pins Values Test Conditions Min Typ Max Unit Item Symbol Notes Clock oscillation frequency Clock cycle time fOSC tcyc OSC1, OSC2 OSC1, OSC2 X1, X2 X1, X2 OSC1, OSC2 X1, X2 8 100 Vcc = 2.7 V to 5.5 V Vcc = 2.7 V to 5.5 V Crystal oscillator 10 125 MHz ns kHz s ms s Figure 29.2 Figure 29.1 Subclock oscillation fX frequency Subclock cycle time tsubcyc Oscillation stabilization time trc 32.768 30.518 10 2 32-kHz crystal oscillator Vcc = 2.7 V to 5.5 V 40 40 500 External clock high tCPH width External clock low tCPL width External clock rise tCPr time External clock fall time External clock stabilization delay time tCPf tDEXT OSC1 OSC1 OSC1 OSC1 OSC1 10 10 ns ns ns ns s Figure 29.1 Figure 29.3 Figure 29.2 Subclock input low tEXCLL level pulse width Subclock input high tEXCLH level pulse width X1 X1 Vcc = 2.7 V to 5.5 V Vcc = 2.7 V to 5.5 V 15.26 15.26 s s Rev.3.00 Jan. 10, 2007 page 811 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Applicable Pins Values Test Conditions Min Typ Max Unit Item Symbol Notes Figure 29.2 Subclock input rise tEXCLr time Subclock input fall tECXLf time RES pin low level width tREL X1 X1 RES Vcc = 2.7 V to 5.5 V Vcc = 2.7 V to 5.5 V Vcc = 2.7 V to 20 5.5 V 10 10 ns ns tcyc tcyc tsubcyc Figure 29.4 Figure 29.5 Input pin high level tIH width IRQ0 to Vcc = 2.7 V to 2 IRQ5, NMI, 5.5 V IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG IRQ0 to Vcc = 2.7 V to 2 IRQ5, NMI, 5.5 V IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG Input pin low level width tIL tcyc tsubcyc tcyc OSC1 VIH VIL tCPH tCPL tCPf tCPr Figure 29.1 System Clock Timing Rev.3.00 Jan. 10, 2007 page 812 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics tsubcyc tEXCLH VIH VIL tEXCLL X1 Vcc x 0.5 tEXCLr tEXCLf Figure 29.2 Subclock Input Timing Vcc 4.0 V OSC1 (Internal) RES tDEXT* Note: * The tDEXT includes the RES pin Low level width 20 tcyc. Figure 29.3 External Clock Stabilization Delay Timing Rev.3.00 Jan. 10, 2007 page 813 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics RES VIL tREL Figure 29.4 Reset Input Timing IRQ0 to IRQ5, NMI, IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG VIH VIL tIL tIH Figure 29.5 Input Timing Rev.3.00 Jan. 10, 2007 page 814 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2.4 Serial Interface Timing of HD64F2194 and HD64F2194C Table 29.7 Serial Interface Timing of HD64F2194 and HD64F2194C (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable Test Symbol Pins Conditions tscyc SCK1 Asynchronization Values Min 4 Typ Max 0.6 1.5 60 1.5 60 100 200 tscyc tcyc ns tcyc ns ns ns ns ns ns ns tscyc tscyc Figure 29.8 Figure 29.7 Figure 29.7 Unit tcyc Figure Figure 29.6 Item Input clock cycle Clock 6 synchronization SCK2 Input clock pulse width tSCKW SCK1, SCK2 SCK1 SCK2 Input clock fall time tSCKf Transmit data delay tTXD time (clock sync) Receive data setup tRXS time (clock sync) Receive data hold time (clock sync) tRXH SCK1 SCK2 SO1 SI1 SI1 SO2 SI2 SI2 CS CS 2 0.4 100 100 180 180 1 1 Input clock rise time tSCKr Transmit data output tTXD delay time Receive data setup tRXS time (clock sync) Receive data hold time (clock sync) CS setup time CS hold time tRXH tCSS tCSH Rev.3.00 Jan. 10, 2007 page 815 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics tSCKW VIH or VOH VIL or VOL tSCKr tSCKf tscyc SCK1 Figure 29.6 SCK1 Clock Timing SCK1, SCK2 tTXD SO1, SO2 VIH VIL tRXS SI1, SI2 tRXH Figure 29.7 SCI I/O Timing/Clock Synchronization Mode CS tCSS VIH tCSH SCK2 VIH VIL Figure 29.8 SCI2 Chip Select Timing Rev.3.00 Jan. 10, 2007 page 816 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Vcc 2.4 k LSI output pin 30 pF 12 k Timing reference level VOH: 2.0 V VOL: 0.8 V Figure 29.9 Output Load Conditions Rev.3.00 Jan. 10, 2007 page 817 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Table 29.8 I C Bus Interface Timing of HD64F2194 and HD64F2194C (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Test Symbol Conditions Min Typ tSCL tSCLH tSCLL tsr tsf 12 3 5 5 3 3 3 0.5 0 2 Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time Max 7.5* 300 1 400 Unit tcyc tcyc tcyc tcyc ns tcyc tcyc tcyc tcyc tcyc tcyc ns pF Figure Figure 29.10 SCL, SDA input spike pulse tsp removal time SDA input bus free time Start condition input hold time Re-transmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacity load Note: * tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Can also be set to 17.5 tcyc depending on the selection of clock to be used by the I C module. 2 Rev.3.00 Jan. 10, 2007 page 818 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics SDA tBUF VIH VIL tSCLH tSP tSTOS tSTAH SCL P* S* tSf tSCLL tSTAS Sr* tSCL tSr tSDAH tSDAS P* Note: * S, P, and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions Figure 29.10 I C Bus Interface I/O Timing 2 Rev.3.00 Jan. 10, 2007 page 819 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2.5 A/D Converter Characteristics of HD64F2194 and HD64F2194C Table 29.9 A/D Converter Characteristics of HD64F2194 and HD64F2194C (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable Test Symbol Pins Conditions AVcc AVIN AICC AISTOP AVcc AN0 to AN7, AN8 to ANB AVcc AVcc AVcc = 5.0 V Values Min Vcc -0.3 AVss Typ Vcc Max Unit Item Analog power supply voltage Analog input voltage Analog power supply current Vcc +0.3 V AVcc 2.0 10 V mA A Vcc = 2.7 to 5.5 V, at reset and in power-down mode AVcc = 5.0 V 13.4 Analog input capacitance CAIN AN0 to AN7, AN8 to ANB AN0 to AN7, AN8 to ANB 30 10 10 4 26.6 pF k Bit LSB s Allowable signal RAIN source impedance Resolution Absolute accuracy Conversion time Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc = Vcc and AVss = Vss. Rev.3.00 Jan. 10, 2007 page 820 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2.6 Servo Section Electrical Characteristics of HD64F2194 and HD64F2194C Table 29.10 Servo Section Electrical Characteristics of HD64F2194 and HD64F2194C (Reference Values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Applicable Symbol Pins Test Conditions CTL (+) Reference Values Min Typ 34.0 36.5 39.0 41.5 44.0 46.5 49.0 51.5 54.0 56.5 59.0 61.5 64.0 66.5 69.0 71.5 Max 36.0 38.5 41.0 43.5 46.0 48.5 51.0 53.5 56.0 58.5 61.0 63.5 66.0 68.5 71.0 73.5 Unit dB Item PB-CTL input amplifier voltage gain CTLGR3 = 0, CTLGR2 = 0, CTLGR1 32.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 0, CTLGR1 34.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 0, CTLGR2 = 0, CTLGR1 37.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 0, CTLGR1 39.5 = 1, CTLGR0 = 1, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 42.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 44.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 47.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 49.5 = 1, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 52.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 54.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 57.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 59.5 = 1, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 62.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 64.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 67.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 69.5 = 1, CTLGR0 = 1, f = 10 kHz Rev.3.00 Jan. 10, 2007 page 821 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Applicable Pins CTLSMT (i) Reference Values Test Conditions AC coupling, C = 0.1 F Typ (non pol) AC coupling, C = 0.1 F Typ (non pol) Min CTL (+) CTL (-) Series resistance = 0 CTLREF CFG CFG CFG V+THCF V-THCF DFG CFG Rise threshold level Fall threshold level Rising edge Schmidt level Falling edge Schmidt level DPG Rising edge Schmidt level Falling edge Schmidt level Vpulse -IOH = 0.1 mA No load, Hi-Z= 1 IOL = 0.1 mA Vpulse AC coupling, C = 1 F Typ, f = 1 kHz 1.0 4.0 Typ 250 -250 150 8 8 10 1/2 SVcc 1/2 SVCC 10 2.25 2.75 1.95 1.85 3.55 3.45 2.5 15 Max 1.0 k V V V k V V Vpp k V mA Unit mVp Item PB-CTL Schmidt input Symbol V+TH V-TH Analog switch ON resistance REC-CTL output current REB ICTL REC-CTL inter-pin RCTL resistance CTL reference output voltage CFG pin bias voltage CFG input level CFG input impedance CFG input threshold voltage DFG Schmidt input V+THDF V-THDF DPG Schmidt input V+THDP V-THDP 3-level output voltage VOH VOM VOL 3-level output pin divided voltage resistance CFG Duty CFG AC coupling, C = 1 F Typ, f = 1 kHz 48 52 % Rev.3.00 Jan. 10, 2007 page 822 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Table 29.11 Servo Section Electrical Characteristics of HD64F2194 and HD64F2194C (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Values Applicable Symbol Pins Test Conditions Min Typ VIH VIL COMP, EXCTL, EXCAP, EXTTRG H.AmpSW, C.Rotary, VIDEOFF, AUDIOFF, DRMPWM, CAPPWM, SV1, SV2 SVcc -IOH = 1 mA IOL = 1.6 mA 0.8 Vcc -0.3 Vcc -1.0 Item Digital input high voltage Digital input low voltage Max Vcc +0.3 0.2 Vcc 0.6 Unit V Digital output high VOH voltage Digital output low VOL voltage V Current dissipationICCSV At no load 5 10 mA Rev.3.00 Jan. 10, 2007 page 823 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.2.7 FLASH Memory Characteristics Table 29.12 shows the flash memory characteristics. Table 29.12 Flash Memory Characteristics (Preliminary) Conditions: Vcc = 5.0 V 10%, AVcc = 5.0 V 10%, Vss = AVss = 0 V, Ta = 0 to +75C (operating temperature range at programming/erasing) Item Programming time* * * Erasing time* * * 135 124 Symbol Min Typ tP tE NWEC 10 100 Max 200 Unit ms/ 32 bytes Test Conditions 1200 ms/ block Times Years 200 When z = 200 s Reprogramming count Data retention time* 9 100 10000 -- *7 *8 10 -- 200 -- s s s s s s s s tDRP *1 10 At Wait time after SWE-bit setting Programming Wait time after PSU-bit setting*1 50 Wait time after P-bit setting* * 1 Wait time after P-bit clearing* Wait time after PSU-bit 1 clearing* Wait time after PV-bit setting* 1 Wait time after dummy write* Maximum No. of 145 programmings* * * At Erasing 1 14 150 10 10 4 2 1 Wait time after PV-bit clearing* 4 1000 Times 1000 10 240 s s ms s s s s s 10 1 Wait time after SWE-bit setting* 10 1 Wait time after ESU-bit setting* 200 Wait time after E-bit setting* * 1 Wait time after E-bit clearing* Wait time after ESU-bit 1 clearing* Wait time after EV-bit setting* 1 Wait time after dummy write* 16 5 10 10 1 20 2 1 Wait time after EV-bit clearing* 5 16 Maximum No. of erasings* * 120 Rev.3.00 Jan. 10, 2007 page 824 of 1038 REJ09B0328-0300 Times 240 Times Section 29 Electrical Characteristics Notes: 1. Perform each time setting according to the programming/erasing algorithm. 2. Programming time per 32 bytes (total time of setting P-bit of the flash memory control register. Programming verify time is not included). 3. Time to erase 1 block (total time of setting E-bit of the flash memory control register. Erasing verify time is not included). 4. Maximum programming time (tP (max.)) = Wait time after P-bit setting (z) x Maximum No. of programming (N) 5. No. of times when wait time after P-bit setting (z) = 200 s. Set maximum No. of programming shall be set less than maximum programming time (tP (max.)) according to the actual setting (z). 6. Relationship between wait time after E-bit setting (z) and maximum No. of erasing (N) for maximum erasing time (tE (max.)) is as follows: tE (max.) = Wait time after E-bit setting x Maximum No. of erasing (N) Set the (z) and (N) values so that they satisfy the above equation. (Ex.) When z = 5 [ms], N = 240 times (Ex.) When z = 10 [ms], N = 120 times 7. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 8. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 9. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. 29.2.8 Usage Note The F-ZTAT version and the Mask ROM version satisfy the electrical characteristics indicated in this manual, but the actual power value, operating margin, and noise margin may differ from those in this manual, due to the difference of production process, on-chip ROM, layout pattern, etc. When executing the system examination using the F-ZTAT version, be sure to execute the same system examination using the Mask ROM version when changing to the Mask ROM version. Rev.3.00 Jan. 10, 2007 page 825 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.3 Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A 29.3.1 Table 29.13 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Input high voltage Symbol VIH Applicable Pins MD0 RES, NMI, IC, IRQ0 to IRQ5 Vcc = 2.5 V to 5.5 V SCK1, SCK2, SI1, SI2, CS, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, ADTRG OSC1, X1 Vcc = 2.5 V to 5.5 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Csync Test Conditions Vcc = 2.5 V to 5.5 V Min Typ Max Vcc +0.3 Vcc +0.3 Vcc +0.3 Vcc +0.3 Unit Notes V 0.9 Vcc 0.8 Vcc 0.9 Vcc 0.8 Vcc Vcc -0.5 Vcc -0.3 Vcc +0.3 Vcc +0.3 Vcc +0.3 Vcc +0.3 0.7 Vcc Vcc = 2.5 V to 5.5 V 0.8 Vcc 0.7 Vcc Vcc +0.3 Rev.3.00 Jan. 10, 2007 page 826 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Input low voltage Symbol VIL Applicable Pins MD0 RES, NMI, IC, IRQ0 to IRQ5 SCK1, SCK2, SI1, SI2, CS, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, ADTRG OSC1, X1 Vcc = 2.5 V to 5.5 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Csync Output high VOH voltage SO1, SO2, SCK1, SCK2, PWM1, PWM2, PWM3, PWM4, PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 -IOH = 1.0 mA -IOH = 0.5 mA -IOH = 0.1 mA Vcc = 2.5 V to 5.5 V Test Conditions Vcc = 2.5 V to 5.5 V Min -0.3 -0.3 Vcc = 2.5 V to 5.5 V -0.3 -0.3 Typ Max Unit Notes 0.1 Vcc V 0.2 Vcc 0.1 Vcc 0.2 Vcc -0.3 -0.3 -0.3 Vcc = 2.5 V to 5.5 V -0.3 0.5 0.3 0.3 Vcc 0.2 Vcc -0.3 Vcc -1.0 Vcc -0.5 Vcc -0.5 0.2 Vcc V V V Referenc e value Rev.3.00 Jan. 10, 2007 page 827 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Symbol Applicable Pins Test Conditions Min Typ Max 0.6 0.4 Unit Notes V Output low VOL voltage SO1, SO2, SCK1, IOL = 1.6 mA SCK2, PWM1, IOL = 0.4 mA PWM2, PWM3, Vcc = 2.5 V to 5.5 V PWM4, PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, PS0 to PS4 P80 to P87 IOL = 20 mA IOL = 1.6 mA IOL = 0.4 mA Vcc = 2.5 V to 5.5 V 1.5 0.6 0.4 1.0 A Input/ output leakage current IIL MD0, OSC1 RES, NMI, IRQ0 to IRQ5, IC Vin = 0.5 to Vcc -0.5 V SCK1, SCK2, SI1, Vin = 0.5 to SI2, CS, FTIA, FTIB, Vcc -0.5 V FTIC, FTID, TRIG, TMBI, ADTRG P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87 PS0 to PS4 P00 to P07, AN8 to ANB Vin = 0.5 to Vcc -0.5 V 1.0 1.0 Vin = 0.5 to AVcc -0.5 V 1.0 Rev.3.00 Jan. 10, 2007 page 828 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Pull-up MOS current Input capacity Symbol -Ip Applicable Pins P10 to P17, P20 to P27, P30 to P37 Test Conditions Vcc = 5.0 V, Vin = 0 V Min 50 Typ Max 300 Unit Notes A Note 1 Cin All input pins except fin = 1 MHz, power supply, P23, Vin = 0 V, Ta = 25C P24 and analog system pins P23, P24 fin = 1 MHz, Vin = 0 V, Ta = 25C Vcc = 5 V, fOSC = 10-MHz High-speed mode 15 pF 20 Active mode IOPE current dissipa-tion (CPU operating) Vcc 50 70 mA Note 2 Vcc = 5 V, fOSC = 10-MHz Medium-speed mode (1/64) Vcc Vcc = 5 V, fOSC = 10 MHz 35 Reference value Active mode IRES current dissipa-tion (reset) Sleep mode ISLEEP current dissipa-tion Subactive ISUB mode current dissipa-tion 25 45 mA Note 2 Vcc Vcc = 5 V, fOSC = 10-MHz Highspeed mode Vcc = 2.5 V, With 32-kHz crystal oscillator ( sub = w/2) Vcc = 2.5 V, With 32-kHz crystal oscillator ( sub = w/8) 20 30 Vcc 40 100 A Note 2 20 Reference value, Note 2 A Note 2 Subsleep ISUBSLP mode current dissipa-tion Vcc Vcc = 2.5 V, With 32-kHz crystal oscillator ( sub = w/2) Vcc = 2.5 V, With 32-kHz crystal oscillator ( sub = w/8) 15 30 10 Reference value, Note 2 Rev.3.00 Jan. 10, 2007 page 829 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Values Item Symbol Applicable Pins Vcc Test Conditions Vcc = 2.5 V, With 32-kHz crystal oscillator Vcc = 5.0 V, With 32-kHz crystal oscillator Vcc Min Typ 5 Max 10 Unit Notes A Note 2 Watch IWATCH mode current dissipa-tion 10 Reference value, Note 2 Note 2 ISTBY Standby mode current dissipa-tion RAM data retaining voltage in standby mode VSTBY X1 = Vcc, Without 32-kHz crystal oscillator 5 Vcc 2.0 V Notes: Do not open the AVcc and AVss pin even when the A/D converter is not in use. 1. Current value when the relevant bit of the pull-up MOS select register (PUR1 to PUR3) is set to 1. 2. The current on the pull-up MOS or the output buffer excluded. Table 29.14 Pin Status at Current Dissipation Measurement Mode Active mode High-speed, mediumspeed Sleep mode High-speed, mediumspeed Reset Standby mode Subactive mode Subsleep mode Watch mode RES Pin Vcc Internal State Operating Pin Vcc Oscillator Pin Main clock: Crystal oscillator Sub clock: X1 pin = Vcc Vcc CPU and servo circuits stopped Reset All stopped CPU and timer A operating Timer A operating Timer A operating Vcc Vss Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Main clock: Crystal oscillator Sub clock: Crystal oscillator Rev.3.00 Jan. 10, 2007 page 830 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Table 29.15 Bus Drive Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable pin: SCL, SDA Applicable Test Pins Conditions SCL, SDA Values Min 0.2 Vcc 0.05 Vcc SCL, SDA SCL, SDA SCL, SDA IOL = 8 mA IOL = 3 mA SCL, SDA 0.7 Vcc -0.5 Typ Max 0.7 Vcc Vcc +0.5 0.2 Vcc 0.5 0.4 250 ns Unit V V V V V V Item Symbol - Schmidt trigger VT input voltage + VT + VT -VT- Input High voltage Input Low voltage Output Low voltage VIH VIL VOL SCL and SDA tof output fall time 20 + 0.1Cb Rev.3.00 Jan. 10, 2007 page 831 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.3.2 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A The specifications for the digital pins are shown below. Table 29.16 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = 2.5 V to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C) Item Allowable input current (to chip) Allowable input current (to chip) Allowable input current (to chip) Allowable output current (from chip) Total allowable input current (to chip) Total allowable output current (from chip) Symbol IO IO IO -IO IO -IO Value 2 22 10 2 80 50 Unit mA mA mA mA mA mA Notes 1 2 3 4 5 6 Notes: 1. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS (except for port 8, SCL and SDA). 2. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to port 8. 3. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to SCL and SDA. 4. The allowable output current is the maximum value of the current flowing from VCC to each I/O pin. 5. The total allowable input current is the sum of the currents flowing from all I/O pins to VSS simultaneously. 6. The total allowable output current is the sum of the currents flowing from VCC to all I/O pins. Rev.3.00 Jan. 10, 2007 page 832 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.3.3 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.17 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable Symbol Pins fOSC tcyc fX OSC1, OSC2 OSC1, OSC2 X1, X2 Test Conditions Values Min 8 100 Vcc = 2.5 V to 5.5 V Vcc = 2.5 V to 5.5 V Typ Max 10 125 Unit MHz ns kHz Figure 29.11 Notes Item Clock oscillation frequency Clock cycle time Subclock oscillation frequency Subclock cycle time Oscillation stabilization time 32.768 tsubcyc trc X1, X2 30.518 10 2 s ms s Figure 29.12 OSC1, OSC2 Crystal oscillator X1, X2 32-kHz crystal oscillator Vcc = 2.5 V to 5.5 V 40 40 500 External clock high width tCPH OSC1 OSC1 OSC1 OSC1 OSC1 10 10 ns ns ns ns s Figure 29.11 External clock low tCPL width External clock rise tCPr time External clock fall tCPf time External clock tDEXT stabilization delay time Figure 29.13 Rev.3.00 Jan. 10, 2007 page 833 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Applicable Symbol Pins X1 X1 Test Conditions Values Min Typ Max Unit s s Notes Figure 29.12 15.26 15.26 Item Subclock input low tEXCLL level pulse width Subclock input high level pulse width Subclock input rise time tEXCLH Vcc = 2.5 V to 5.5 V Vcc = 2.5 V to 5.5 V Vcc = 2.5 V to 5.5 V Vcc = 2.5 V to 5.5 V Vcc = 2.5 V to 20 5.5 V tEXCLr X1 X1 RES 10 10 ns ns tcyc tcyc tsubcyc Figure 29.12 Subclock input fall tEXCLf time RES pin low level tREL width Input pin high level width tIH Figure 29.14 Figure 29.15 IRQ0 to IRQ5, Vcc = 2.5 V to 2 NMI, IC, 5.5 V ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG IRQ0 to IRQ5, Vcc = 2.5 V to 2 NMI, IC, 5.5 V ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG Input pin low level tIL width tcyc tsubcyc tcyc OSC1 VIH VIL tCPH tCPL tCPf tCPr Figure 29.11 System Clock Timing Rev.3.00 Jan. 10, 2007 page 834 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics tsubcyc tEXCLH VIH VIL tEXCLL X1 Vcc x 0.5 tEXCLr tEXCLf Figure 29.12 Subclock Input Timing Vcc 4.0 V OSC1 (Internal) RES tDEXT* Note: * The tDEXT includes the RES pin Low level width 20 tcyc. Figure 29.13 External Clock Stabilization Delay Timing Rev.3.00 Jan. 10, 2007 page 835 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics RES VIL tREL Figure 29.14 Reset Input Timing IRQ0 to IRQ5, NMI, IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG VIH VIL tIL tIH Figure 29.15 Input Timing Rev.3.00 Jan. 10, 2007 page 836 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.3.4 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.18 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable Test Symbol Pins Conditions tscyc SCK1 Asynchronization Values Min 4 Typ Max 0.6 1.5 60 1.5 60 100 200 tscyc tcyc ns tcyc ns ns ns ns ns ns ns tscyc tscyc Figure 29.18 Figure 29.17 Figure 29.17 Unit tcyc Figure Figure 29.16 Item Input clock cycle Clock 6 synchronization SCK2 Input clock pulse width tSCKW SCK1, SCK2 SCK1 SCK2 Input clock fall time tSCKf Transmit data delay tTXD time (clock sync) Receive data setup tRXS time (clock sync) Receive data hold time (clock sync) tRXH SCK1 SCK2 SO1 SI1 SI1 SO2 SI2 SI2 CS CS 2 0.4 100 100 180 180 1 1 Input clock rise time tSCKr Transmit data output tTXD delay time Receive data setup tRXS time (clock sync) Receive data hold time (clock sync) CS setup time CS hold time tRXH tCSS tCSH Rev.3.00 Jan. 10, 2007 page 837 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics tSCKW VIH or VOH VIL or VOL tSCKr tSCKf tscyc SCK1 Figure 29.16 SCK1 Clock Timing SCK1, SCK2 tTXD SO1, SO2 VIH VIL tRXS SI1, SI2 tRXH Figure 29.17 SCI I/O Timing/Clock Synchronization Mode CS tCSS VIH tCSH SCK2 VIH VIL Figure 29.18 SCI2 Chip Select Timing Rev.3.00 Jan. 10, 2007 page 838 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Vcc 2.4 k LSI output pin 30 pF 12 k Timing reference level VOH: 2.0 V VOL: 0.8 V Figure 29.19 Output Load Conditions Rev.3.00 Jan. 10, 2007 page 839 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Table 29.19 I C Bus Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Test Symbol Conditions Min Typ tSCL tSCLH tSCLL tsr tsf 12 3 5 5 3 3 3 0.5 0 2 Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time Max 7.5* 300 1 400 Unit tcyc tcyc tcyc tcyc ns tcyc tcyc tcyc tcyc tcyc tcyc ns pF Figure Figure 29.10 SCL, SDA input spike pulse tsp removal time SDA input bus free time Start condition input hold time Re-transmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacity load Note: * tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Can also be set to 17.5 tcyc depending on the selection of clock to be used by the I C module. 2 Rev.3.00 Jan. 10, 2007 page 840 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics SDA tBUF VIH VIL tSCLH tSP tSTOS tSTAH SCL P* S* tSf tSCLL tSTAS Sr* tSr tSCL tSDAH tSDAS P* Note: * S, P, and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions Figure 29.20 I C Bus Interface I/O Timing 2 Rev.3.00 Jan. 10, 2007 page 841 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.3.5 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.20 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Applicable Symbol Pins Test Conditions Min Typ AVcc AVIN AICC AISTOP AVcc AN0 to AN7, AN8 to ANB AVcc AVcc AVcc = 5.0 V Vcc -0.3 AVss Vcc Item Analog power supply voltage Analog input voltage Analog power supply current Max Unit Vcc +0.3 V AVcc 2.0 10 V mA A Vcc = 2.5 V to 5.5 V, at reset and in power-down mode AVcc = 5.0 V 13.4 Analog input capacitance CAIN AN0 to AN7, AN8 to ANB AN0 to AN7, AN8 to ANB 30 10 10 4 26.6 pF k Bit LSB s Allowable signal RAIN source impedance Resolution Absolute accuracy Conversion time Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc = Vcc and AVss = Vss. Rev.3.00 Jan. 10, 2007 page 842 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics 29.3.6 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.21 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Applicable Symbol Pins Test Conditions CTL (+) Reference Values Min Typ 34.0 36.5 39.0 41.5 44.0 46.5 49.0 51.5 54.0 56.5 59.0 61.5 64.0 66.5 69.0 71.5 Max 36.0 38.5 41.0 43.5 46.0 48.5 51.0 53.5 56.0 58.5 61.0 63.5 66.0 68.5 71.0 73.5 Unit dB Item PB-CTL input amplifier voltage gain CTLGR3 =0, CTLGR2 = 0, CTLGR1 32.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 0, CTLGR1 34.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 0, CTLGR2 = 0, CTLGR1 37.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 0, CTLGR1 39.5 = 1, CTLGR0 = 1, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 42.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 44.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 47.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 0, CTLGR2 = 1, CTLGR1 49.5 = 1, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 52.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 54.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 57.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 0, CTLGR1 59.5 = 1, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 62.0 = 0, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 64.5 = 0, CTLGR0 = 1, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 67.0 = 1, CTLGR0 = 0, f = 10 kHz CTLGR3 = 1, CTLGR2 = 1, CTLGR1 69.5 = 1, CTLGR0 = 1, f = 10 kHz Rev.3.00 Jan. 10, 2007 page 843 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Applicable Pins Reference Values Test Conditions Min CTL (+) CTL (-) Series resistance = 0 CTLREF CFG CFG AC coupling, C = 1 F Typ, f = 1 kHz 1.0 Typ 250 -250 150 8 8 10 1/2 SVCC 1/2 SVCC Max k V V Vpp mA Unit mVp Item PB-CTL Schmidt input Symbol V+TH V-TH CTLSMT (i) AC coupling, C = 0.1 F Typ (non pol) AC coupling, C = 0.1 F Typ (non pol) Analog switch ON REB resistance REC-CTL output current ICTL REC-CTL inter-pin RCTL resistance CTL reference output voltage CFG pin bias voltage CFG input level CFG input impedance CFG input threshold value V+THCF V-THCF CFG CFG Rise threshold level Fall threshold level DFG Rising edge Schmidt level Falling edge Schmidt level DPG Rising edge Schmidt level Falling edge Schmidt level Vpulse -IOH = 0.1 mA No load, Hi-Z = 1 IOL = 0.1 mA Vpulse 4.0 10 2.25 2.75 1.95 1.85 3.55 3.45 2.5 15 1.0 k V DFG Schmidt input V+THDF V-THDF DPG Schmidt input V+THDP V-THDP 3-level output voltage VOH VOM VOL 3-level output pin divided voltage resistance CFG Duty V V V k CFG AC coupling, C = 1 F Typ, f = 1 kHz 48 52 % Rev.3.00 Jan. 10, 2007 page 844 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Table 29.22 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Applicable Symbol Pins Test Conditions VIH VIL COMP, EXCTL, EXCAP, EXTTRG H.AmpSW, C.Rotary, VIDEOFF, AUDIOFF, DRMPWM, CAPPWM, SV1, SV2 SVcc -IOH = 1 mA IOL = 1.6 mA Values Min 0.8 Vcc -0.3 Vcc -1.0 Typ Max Unit Item Digital input high voltage Digital input low voltage Vcc +0.3 V 0.2 Vcc 0.6 V Digital output high VOH voltage Digital output low VOL voltage Current dissipationICCSV At no load 5 10 mA Rev.3.00 Jan. 10, 2007 page 845 of 1038 REJ09B0328-0300 Section 29 Electrical Characteristics Rev.3.00 Jan. 10, 2007 page 846 of 1038 REJ09B0328-0300 Appendix A Instruction Set Appendix A Instruction Set A.1 Instructions Operation Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 General register (destination)* 1 General register (source)* 1 General register* 1 General register (32-bit register) Multiplication-Addition register (32-bit register)* Destination operand Source operand Extend register Condition code register N (negative flag) in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move from the left to the right Logical complement Contents of operand 8-, 16-, 24-, 32-bit length Rev.3.00 Jan. 10, 2007 page 847 of 1038 REJ09B0328-0300 2 Appendix A Instruction Set Notes: 1. General register is 8-bit (R0H to R7H, R0L to R7L), 16-bit (R0 to R7) or 32-bit (ER0 to ER7). 2. MAC register cannot be used in this LSI. Condition Code Notation Symbol Description Modified according to the instruction result * 0 1 Not fixed (value not guaranteed) Always cleared to 0 Always set to 1 Not affected by the instruction execution result Rev.3.00 Jan. 10, 2007 page 848 of 1038 REJ09B0328-0300 Appendix A Instruction Set Table A.1 List of Instruction Set (1) Data Transfer Instruction Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation @@aa @aa Condition Code No of Execution States *1 Advanced Mode @ERn #xx Rn -- I #xx:8Rd8 Rs8Rd8 @ERsRd8 @(d:16,ERs)Rd8 @(d:32,ERs)Rd8 @ERsRd8,ERs32+1ERs32 @aa:8Rd8 @aa:16Rd8 @aa:32Rd8 Rs8@ERd Rs8@(d:16,ERd) Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 Rs16Rd16 @ERsRd16 @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 @ERsRd16,ERs32+2ERs32 @aa:16Rd16 @aa:32Rd16 Rs16@ERd Rs16@(d:16,ERd) Rs16@(d:32,ERd) ERd32-2ERd32,Rs16@ERd Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 @aa:32ERd32 ERs32@ERd ERs32@(d:16,ERd) ERs32@(d:32,ERd) ERd32-4ERd32,ERs32@ERd ERs32@aa:16 ERs32@aa:32 @SPRn16,SP+2SP @SPERn32,SP+4SP SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeat for the number of returns (SP-4SP,ERn32@SP) Repeat for the number of returns -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HNZVC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ------ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOV POP PUSH LDM STM MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn LDM @SP+,(ERm-ERn) STM (ERm-ERn),@-SP B B B B B B B B B B B B B B B B W W W W W W W W W W W W W W L L L L L L L L L L L L L L W L W L L L 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 6 2 4 8 2 4 6 6 2 4 6 10 4 6 8 4 6 10 4 6 8 2 4 2 4 4 4 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] 7/9/11 [1] [2] [2] ------------ MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 Cannot be used in this LSI Rev.3.00 Jan. 10, 2007 page 849 of 1038 REJ09B0328-0300 Appendix A Instruction Set (2) Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation @@aa @aa Condition Code No of Execution States *1 @ERn #xx Rn -- I -- -- Rd8+Rs8Rd8 -- Rd16+#xx:16Rd16 -- Rd16+Rs16Rd16 -- ERd32+#xx:32ERd32 -- ERd32+ERs32ERd32 -- Rd8+#xx:8+CRd8 -- Rd8+Rs8+CRd8 -- ERd32+1ERd32 -- ERd32+2ERd32 -- ERd32+4ERd32 -- Rd8+1Rd8 -- Rd16+1Rd16 -- Rd16+2Rd16 -- ERd32+1ERd32 -- ERd32+2ERd32 -- Rd8 10 Decimal adjust Rd8 -- Rd8-Rs8Rd8 -- Rd16-#xx:16Rd16 -- Rd16-Rs16Rd16 -- ERd32-#xx:32ERd32 -- ERd32-ERs32ERd32 -- Rd8-#xx:8-CRd8 -- Rd8-Rs8-CRd8 -- ERd32-1ERd32 -- ERd32-2ERd32 -- ERd32-4ERd32 -- Rd8-1Rd8 -- Rd16-1Rd16 -- Rd16-2Rd16 -- ERd32-1ERd32 -- ERd32-2ERd32 -- Rd8 10 Decimal adjust Rd8 Rd8xRs8Rd16(Multiplication w/o sign) -- Rd16xRs16ERd32(Multiplication w/o sign) -- Rd8xRs8Rd16(Multiplication w/o sign) -- Rd16xRs16ERd32(Multiplication w/o sign) -- Rd16/Rs8Rd16 (RdH: Rmainder, RdL: -- Rd8+#xx:8Rd8 Quatient)(Division w/o sign) ERd32/Rs16ERd32 (Ed:Remainder, Rd: Quatient)(Division with sign) Rd16/Rs8Rd16(RdH: Rmainder, RdL: Quatient)(Division w/o sign) ERd32/Rs16ERd32 (Ed:Remainder, Rd: Quatient)(Division with sign) Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 0-ERd32ERd32 0( HNZVC Advanced Mode ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC.B Rd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA Rd DAA SUB.B Rs,Rd SUB SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX #xx:8,Rd SUBX SUBX Rs,Rd SUBS #1,ERd SUBS SUBS #2,ERd SUBS #4,ERd DEC.B Rd DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS Rd DAS MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd EXTU.L ERd EXTS.W Rd EXTS.L ERd TAS*2 MAC TAS @ERd ADD B B W W L L B B L L L B W W L L B B W W L L B B L L L B W W L L B B W B W B W B W B B W W L L B W L W L W L B 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 2 4 4 2 2 4 2 6 2 2 2 2 2 2 2 2 4 [3] [3] [4] [4] [5] [5] ---------- ---------- ---------- -- -- -- -- -- -- -- -- -- -- * * [3] [3] [4] [4] [5] [5] -------- -------- -------- -- -- -- -- -- *-- -------- -------- ---- ---- [6] [7] -- -- -- -- -- -- -- -- -- -- * -- -- -- -- -- 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 1 12 20 13 21 12 20 13 21 1 1 2 1 3 1 1 1 1 1 1 1 1 4 -- -- [6] [7] -- -- -- -- [8] [7] -- -- -- -- [8] [7] -- -- -- -- -- -- -- -- -- -- -- -- -- -- [3] [3] [4] [4] NEG EXTU EXTS --0 --0 -- 0-- 0-- 0-- 0-- 0-- ---- ---- ( MAC @ERn+,@ERm+ CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd Cannot be used in this LSI [2] Rev.3.00 Jan. 10, 2007 page 850 of 1038 REJ09B0328-0300 Appendix A Instruction Set (3) Logic Operations Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No of Execution States *1 @(d,PC) Mnemonic Size @(d,ERn) Operation @@aa @aa @ERn #xx Rn -- I Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 ~Rd8Rd8 ~Rd16Rd16 ~ERd32ERd32 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HNZVC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Advanced Mode AND OR XOR NOT AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT.B Rd NOT.W Rd NOT.L ERd B B W W L L B B W W L L B B W W L L B W L 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 Rev.3.00 Jan. 10, 2007 page 851 of 1038 REJ09B0328-0300 Appendix A Instruction Set (4) Shift Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation Condition Code No of Execution States *1 @@aa @ERn @aa #xx Rn -- I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HNZVC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Advanced Mode SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 C MSB LSB MSB LSB C 0 C MSB LSB 0 MSB LSB C 0 0 0 0 0 0 C MSB LSB MSB LSB C C MSB LSB MSB LSB C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev.3.00 Jan. 10, 2007 page 852 of 1038 REJ09B0328-0300 Appendix A Instruction Set (5) Bit Manipulation Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation Condition Code No of Execution States *1 @@aa @ERn @aa #xx Rn -- I (#xx:3 of Rd8)1 (#xx:3 of @ERd)1 (#xx:3 of @aa:8)1 (#xx:3 of @aa:16)1 (#xx:3 of @aa:32)1 (Rn8 of Rd8)1 (Rn8 of @ERd)1 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 (Rn8 of @aa:32)0 (#xx:3 of Rd8)[~(#xx:3 of Rd8)] (#xx:3 of @ERd)[~(#xx:3 of @ERd)] (#xx:3 of @aa:8)[~(#xx:3 of @aa:8)] (#xx:3 of @aa:16)[~(#xx:3 of @aa:16)] (#xx:3 of @aa:32)[~(#xx:3 of @aa:32)] (Rn8 of Rd8)[~(Rn8 of Rd8)] (Rn8 of @ERd)[~(Rn8 of @ERd)] (Rn8 of @aa:8)[~(Rn8 of @aa:8)] (Rn8 of @aa:16)[~(Rn8 of @aa:16)] (Rn8 of @aa:32)[~(Rn8 of @aa:32)] ~(#xx:3 of Rd8)Z ~(#xx:3 of @ERd)Z ~(#xx:3 of @aa:8)Z ~(#xx:3 of @aa:16)Z ~(#xx:3 of @aa:32)Z ~(Rn8 of Rd8)Z ~(Rn8 of @ERd)Z ~(Rn8 of @aa:8)Z ~(Rn8 of @aa:16)Z ~(Rn8 of @aa:32)Z (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C ~(#xx:3 of Rd8)C ~(#xx:3 of @ERd)C ~(#xx:3 of @aa:8)C ~(#xx:3 of @aa:16)C ~(#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) ~C(#xx:3 of Rd8) ~C(#xx:3 of @ERd) ~C(#xx:3 of @aa:8) ~C(#xx:3 of @aa:16) ~C(#xx:3 of @aa:32) C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C HNZVC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Advanced Mode BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 Rev.3.00 Jan. 10, 2007 page 853 of 1038 REJ09B0328-0300 Appendix A Instruction Set Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation Condition Code No of Execution States *1 @@aa @ERn @aa #xx Rn -- I C [~(#xx:3 of Rd8)]C C [~(#xx:3 of @ERd)]C C [~(#xx:3 of @aa:8)]C C [~(#xx:3 of @aa:16)]C C [~(#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C [~(#xx:3 of Rd8)]C C [~(#xx:3 of @ERd)]C C [~(#xx:3 of @aa:8)]C C [~(#xx:3 of @aa:16)]C C [~(#xx:3 of @aa:32)]C C (#xx:3 of Rd8)C C (#xx:3 of @ERd)C C (#xx:3 of @aa:8)C C (#xx:3 of @aa:16)C C (#xx:3 of @aa:32)C C [~(#xx:3 of Rd8)]C C [~(#xx:3 of @ERd)]C C [~(#xx:3 of @aa:8)]C C [~(#xx:3 of @aa:16)]C C [~(#xx:3 of @aa:32)]C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HNZVC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Advanced Mode BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 Rev.3.00 Jan. 10, 2007 page 854 of 1038 REJ09B0328-0300 Appendix A Instruction Set (6) Branch Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation Operation Code No of Execution States *1 @@aa @ERn @aa #xx Rn Branch Condition -- I H N Z V C Advanced Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 5 4 5 4 5 6 5 Bcc JMP BSR JSR RTS BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 2 4 2 4 2 2 -- -- -- Never -- CZ=0 -- -- CZ=1 -- -- -- C=0 -- -- C=1 -- -- Z=0 -- -- Z=1 -- -- V=0 -- -- V=1 -- -- N=0 -- -- N=1 -- NV=0 -- -- NV=1 -- -- Z(NV)=0 -- -- Z(NV)=1 -- -- -- PCERn -- PCaa:24 -- PC@aa:8 -- PC@-SP,PCPC+d:8 -- PC@-SP,PCPC+d:16 -- PC@-SP,PCERn -- PC@-SP,PCaa:24 -- PC@-SP,PC@aa:8 -- PC@SP+ if condition is true then PCPC+d else next; Always Rev.3.00 Jan. 10, 2007 page 855 of 1038 REJ09B0328-0300 Appendix A Instruction Set (7) System Control Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ @(d,PC) Mnemonic Size @(d,ERn) Operation Condition Code No of Execution States *1 @@aa @ERn @aa #xx Rn -- I PC@-SP,CCR@-SP, EXR@-SP, HNZVC Advanced Mode TRAPA TRAPA #xx:2 RTE RTE -- -- -- B B B B W W W W W W W W W W W W B B W W W W W W W W W W W W B B B B B B -- 1 ---------- 8 [9] 5 [9] SLEEP SLEEP LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR STC CCR,Rd STC STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ORC ORC #xx:8,CCR ORC #xx:8,EXR XORC XORC #xx:8,CCR XORC #xx:8,EXR NOP NOP ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 2 4 4 6 6 10 10 4 4 6 6 8 8 2 2 4 4 6 6 10 10 4 4 6 6 8 8 2 4 2 4 2 4 2 ------------ ------------ ------------ ------------ 2 1 2 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 2 1 2 1 2 1 Rev.3.00 Jan. 10, 2007 page 856 of 1038 REJ09B0328-0300 Appendix A Instruction Set (8) Block Transfer Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No of Execution States *1 @(d,PC) Mnemonic Size @(d,ERn) Operation @@aa @aa @ERn #xx Rn -- I if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; HNZVC Advanced Mode EEPMOV EEPMOV.B -- 4 ------------ 4+2n *3 EEPMOV.W -- 4 ------------ 4+2n *3 Notes: 1. The values indicated in the column of number of execution states apply when instruction code and operand exist in the on-chip memory. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. n is the initial setting value of R4L or R4. [1] 7 states when the number of return/retract registers is 2, 9 states when the number of registers is 3, and 11 states when the number of registers is 4. [2] Cannot be used in this LSI. [3] Set to 1 when a carry or borrow occurs at bit 11, otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27, otherwise cleared to 0. [5] Retains the value before computation when the computation result is 0, otherwise cleared to 0. [6] Set to 1 when the divisor is negative, otherwise cleared to 0. [7] Set to 1 when the divisor is 0, otherwise cleared to 0. [8] Set to 1 when the quotient is negative, otherwise cleared to 0. [9] 1 is added to the number of execution states when EXR is valid. Rev.3.00 Jan. 10, 2007 page 857 of 1038 REJ09B0328-0300 Size A.2 Instruction 3rd byte 4th byte 5th byte 6th byte 7the byte 8th byte 9th byte 10th byte Mnemonic Instruction Format ADD IMM IMM ADDS Appendix A Instruction Set ADDX Instruction Codes AND IMM IMM 6 0 ers 0 erd IMM 0 IMM 0 IMM abs 7 0 IMM abs disp disp disp disp disp disp disp disp disp disp 6 0 7 6 0 IMM 0 0 0 0 7 7 6 6 6 6 Rev.3.00 Jan. 10, 2007 page 858 of 1038 REJ09B0328-0300 B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1st byte rd 8 8 0 9 7 9 0 A 7 A 0 B 0 B 0 B 0 rd 9 E 0 rd E 6 1 9 7 6 6 A 7 1 0 6 0 1 0 6 7 C 7 E 7 A 6 A 6 0 4 8 5 1 4 8 5 2 4 8 5 3 4 8 5 4 4 8 5 5 4 8 5 6 4 8 5 7 4 8 5 8 4 8 5 9 4 8 5 2nd byte IMM rs rd 1 rd rs rd 1 0 erd 1 ers 0 erd 0 0 erd 8 0 erd 9 0 erd IMM rs rd IMM rs rd 6 rd rs rd 6 0 erd F 0 IMM 4 1 0 IMM rd 0 erd 0 abs 1 0 3 0 disp 0 0 disp 1 0 disp 2 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 ANDC BAND Bcc ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 Size Instruction 3rd byte disp disp disp disp disp disp 7 7 7 abs 6 6 abs 6 abs 7 7 7 abs 7 7 7 7 0 0 7 abs 7 7 4 4 0 0 1 IMM 1 IMM abs 7 abs 6 6 7 7 0 0 1 IMM 1 IMM abs 6 abs 7 1 IMM 0 6 7 1 IMM 0 4 1 IMM 0 7 4 1 IMM 0 7 1 IMM 0 7 7 1 IMM 0 1 IMM 1 IMM abs 6 6 0 0 6 1 IMM 0 7 6 1 IMM 0 1 IMM 1 IMM abs 2 rn 2 2 rn rn 0 0 0 6 2 rn 0 2 0 IMM 0 7 2 0 IMM 0 2 2 0 IMM 0 IMM abs 0 0 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Instruction Format 10th byte Bcc (Cont.) BCLR BIAND BILD BIOR Appendix A Instruction Set Rev.3.00 Jan. 10, 2007 page 859 of 1038 REJ09B0328-0300 BIST BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 -- -- -- -- -- -- -- -- -- -- -- -- B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 1st byte A 4 8 5 B 4 8 5 C 4 8 5 D 4 8 5 E 4 8 5 F 4 8 5 2 7 D 7 F 7 A 6 A 6 2 6 D 7 F 7 A 6 A 6 6 7 C 7 E 7 A 6 A 6 7 7 C 7 E 7 A 6 A 6 4 7 C 7 E 7 A 6 A 6 7 6 D 7 F 7 A 6 A 6 2nd byte disp A 0 disp B 0 disp C 0 disp D 0 disp E 0 disp F 0 0 IMM rd 0 erd 0 abs 1 8 3 8 rn rd 0 erd 0 abs 1 8 3 8 1 IMM rd 0 erd 0 abs 1 0 3 0 1 IMM rd 0 erd 0 abs 1 0 3 0 1 IMM rd 0 erd 0 abs 0 1 0 3 1 IMM rd 0 0 erd abs 8 1 8 3 Size Instruction 3rd byte 7 7 7 abs 7 5 1 IMM 7 7 7 abs 7 7 0 IMM 7 7 7 abs 7 6 6 abs 6 abs 7 7 7 abs 7 7 abs 6 6 0 0 abs abs disp 6 6 7 7 0 0 0 IMM 0 IMM abs 6 abs 7 0 IMM 0 6 7 0 IMM 0 rn rn 0 0 6 0 rn 0 6 0 rn 0 0 0 0 0 7 0 0 IMM 0 7 0 0 IMM 0 0 IMM 0 IMM abs 4 4 4 0 0 0 IMM 0 7 4 0 IMM 0 0 IMM 0 IMM abs 1 rn 0 6 1 rn 0 1 1 rn rn 0 0 1 0 IMM 0 1 0 IMM 0 1 1 0 IMM 0 IMM abs 0 0 7 0 IMM 0 0 7 7 0 IMM 0 IMM abs 0 0 0 5 1 IMM 0 5 5 1 IMM 1 IMM abs 0 0 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte 1 0 Mnemonic Instruction Format BIXOR Appendix A Instruction Set BLD 0 0 BNOT 0 0 Rev.3.00 Jan. 10, 2007 page 860 of 1038 REJ09B0328-0300 0 0 0 0 0 0 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B -- -- B B B B B 0 0 1st byte 5 7 C 7 E 7 A 6 A 6 7 7 C 7 E 7 A 6 A 6 1 7 D 7 F 7 A 6 A 6 1 6 D 7 F 7 A 6 A 6 4 7 C 7 E 7 A 6 A 6 0 7 D 7 F 7 A 6 A 6 0 6 D 7 F 7 A 6 A 6 5 5 C 5 7 6 D 7 F 7 A 6 A 6 2nd byte IMM rd erd 0 abs 1 0 3 0 IMM rd erd 0 abs 1 0 3 0 IMM rd erd 0 abs 1 8 3 8 rn rd erd 0 abs 1 8 3 8 IMM rd erd 0 abs 1 0 3 0 IMM rd erd 0 abs 1 8 3 8 rn rd erd 0 abs 1 8 3 8 disp 0 0 IMM rd erd 0 abs 8 1 8 3 BOR BSET BSR BST BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 Size Instruction 3rd byte 7 7 7 abs 7 0 IMM 3 0 6 6 abs rn 6 rn 3 abs 7 7 0 IMM 0 IMM abs 7 abs 7 5 0 IMM 0 5 0 IMM 0 5 5 0 0 6 3 0 0 3 3 rn rn 0 0 3 0 IMM 0 3 3 0 IMM 0 IMM abs 0 0 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Instruction Format 10th byte BTST BXOR CLRMAC CMP IMM IMM 2nd byte 1st byte 0 IMM rd 3 7 0 0 erd C 7 abs E 7 0 1 A 6 0 3 A 6 rd rn 3 6 0 erd C 7 0 abs E 7 1 A 6 0 3 A 6 0 0 IMM rd 5 7 0 erd C 7 0 abs E 7 1 A 6 0 3 A 6 0 Cannot be used in this LSI DAA DAS DEC DIVXS 5 5 1 3 rs rs rd 0 erd DIVXU 5 5 9 9 EEPMOV 8 8 F F EXTS Appendix A Instruction Set Rev.3.00 Jan. 10, 2007 page 861 of 1038 REJ09B0328-0300 EXTU BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd B B B B B B B B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- W L W L A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 1 1 1 1 rs 2 rs 2 1 ers 0 0 0 5 D 7 F D D rs rs 5 D D F 5 7 rd C 9 D A F F F A B B B B 1 1 1 3 B B 7 7 7 7 IMM rd rd rd 0 erd 0 erd rd rd rd rd rd 0 erd 0 erd 0 0 rd 0 erd C 4 rd 0 erd rd 0 erd Size Instruction 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10 byte 2nd byte rd 0 rd 5 rd D 0 erd 7 0 erd F 0 0 ern abs 0 abs abs IMM 0 7 IMM abs 0 ern Mnemonic Instruction Format INC JMP Appendix A Instruction Set JSR Rev.3.00 Jan. 10, 2007 page 862 of 1038 REJ09B0328-0300 disp disp 6 6 B B 2 2 0 0 disp disp 0 0 0 0 0 0 0 0 abs abs abs abs 1st byte A 0 B 0 B 0 B 0 B 0 9 5 A 5 B 5 D 5 E 5 F 5 7 0 1 0 3 0 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4 0 1 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 6 6 6 6 7 7 6 6 6 6 6 6 6 6 6 9 9 F F 8 8 D D B B B B D D D 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 0 0 0 2 0 2 0 ern+1 7 0 ern+2 7 0 ern+3 7 Cannot be used in this LSI disp 6 A 2 rd disp 0 0 0 0 abs abs 1 1 0 disp 6 A A rs disp B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W W W L L L L L -- B B B B B B B B B B B B F 0 6 6 7 6 2 6 6 6 6 7 rd C 8 E 8 C rd A A 8 E 8 IMM rs rd ers rd ers rd ers 0 ers rd abs 0 rd 2 rd erd rs erd rs erd 0 LDC LDM LDMAC MAC MOV INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) Size Instruction 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 1 abs abs IMM Mnemonic Instruction Format 10th byte MOV (Cont.) disp 6 abs abs disp 6 abs abs IMM 0 0 disp 6 B abs abs disp 6 0 0 0 B abs abs A 0 ers disp 2 0 erd disp 0 0 0 0 0 0 0 0 0 B A disp rs B 2 disp rd 0 0 0 0 1 1 0 1 1 1st byte C 6 rs 3 A 6 A 6 9 7 D 0 9 6 F 6 8 7 D 6 B 6 B 6 9 6 F 6 8 7 D 6 B 6 B 6 A 7 F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 6 7 6 6 6 6 6 7 6 6 6 1 1 0 1 9 F 8 D B B 9 F 8 D B B ers ers ers ers 0 2 erd erd erd erd 8 A erd erd 0 erd erd erd ers ers 0 ers ers ers Cannot be used in this LSI 5 5 0 2 rs rs rd 0 erd 2nd byte rs erd abs 8 rs A rs 0 rd rs rd ers rd ers rd ers 0 ers rd 0 rd 2 rd erd rs erd rs erd 0 erd rs 8 rs A rs 0 0 erd ers 0 erd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOVFPE MOVTPE MULXS MULXU NEG Appendix A Instruction Set Rev.3.00 Jan. 10, 2007 page 863 of 1038 REJ09B0328-0300 0 0 5 5 1 1 1 0 0 0 rd 0 erd rd rd 0 erd 0 1 1 0 2 7 7 7 0 C C rs rs 8 9 B 0 NOP MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) *1 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP B B B B W W W W W W W W W W W W W W W L L L L L L L L L L L L L B B B W B W B W L -- Size Instruction 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Mnemonic Instruction Format NOT OR IMM IMM 6 0 IMM 7 F 0 ern 0 ern 0 6 6 D D 4 4 ers 0 erd Appendix A Instruction Set ORC POP PUSH Rev.3.00 Jan. 10, 2007 page 864 of 1038 REJ09B0328-0300 B W L B B W W L L B B W L W L B B W W L L B B W W L L B B W W L L B B W W L L -- -- 1st byte 7 1 7 1 7 1 rd C 4 1 9 7 4 6 A 7 1 0 4 0 1 0 D 6 1 0 D 6 1 0 2 1 2 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 3 1 3 1 2 1 2 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 3 1 3 1 6 5 4 5 2nd byte 0 rd 1 rd 3 0 erd IMM rs rd 4 rd rs rd 4 0 erd F 0 IMM 4 1 7 rn 0 0 F rn 0 0 8 rd C rd 9 rd D rd B 0 erd F 0 erd 8 rd C rd 9 rd D rd B 0 erd F 0 erd 0 rd 4 rd 1 rd 5 rd 3 0 erd 0 erd 7 rd 0 rd 4 rd 1 rd 5 0 erd 3 0 erd 7 0 7 0 7 ROTL ROTR ROTXL ROTXR RTE RTS NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTS Size Instruction 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Instruction Format 10th byte SHAL SHAR SHLL SHLR SLEEP STC disp disp 6 6 B B A A 0 0 disp disp 1 1 1 1 0 0 1 1 abs abs abs abs STM 1st byte 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 6 6 6 6 6 9 9 F F 8 8 D D B B B B D D D 0 erd 0 erd 0 erd 0 erd 0 erd 0 erd 0 erd 0 erd 0 8 0 8 0 A 0 A 0 ern F 0 ern F 0 ern F Cannot be used in this LSI 2nd byte rd 8 rd C rd 9 rd D 0 erd B 0 erd F rd 8 rd C rd 9 rd D 0 erd B 0 erd F rd 0 rd 4 rd 1 rd 5 0 erd 3 0 erd 7 rd 0 rd 4 rd 1 rd 5 0 erd 3 7 0 erd 8 0 0 rd 1 rd 4 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 1 0 2 0 3 0 Appendix A Instruction Set Rev.3.00 Jan. 10, 2007 page 865 of 1038 REJ09B0328-0300 STMAC SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L(ERn-ERn+1) , @-SP STM.L (ERn-ERn+2) , @-SP STM.L (ERn-ERn+3) , @-SP STMAC MACH,ERd STMAC MACL,ERd B B W W L L B B W W L L B B W W L L B B W W L L -- B B W W W W W W W W W W W W L L L L L Size Instruction 3rd byte IMM IMM 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Mnemonic Instruction Format SUB SUBS Appendix A Instruction Set SUBX 7 B 0 erd C TAS*2 TRAPA XOR IMM Rev.3.00 Jan. 10, 2007 page 866 of 1038 REJ09B0328-0300 6 0 5 IMM 5 IMM 0 ers 0 erd B W W L L L L L B B B -- B B W W L L B B 1st byte 8 1 9 7 9 1 7 A A 1 B 1 1 B B 1 rd B E 1 1 0 5 7 D rd 1 5 9 7 5 6 A 7 0 1 0 5 0 1 2nd byte rd rs rd 3 rd rs 0 erd 3 1 ers 0 erd 0 erd 0 0 erd 8 0 erd 9 IMM rd rs 0 E 0 00 IMM IMM rs rd rd 5 rs rd 5 0 erd F 0 IMM 1 4 XORC SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. Either 1 or 0 can be set to bit 7 in 4th byte of MOV.L ERs, @(d: 32, ERd) instruction. 2. Only register ER0,ER1,ER4, or ER5 should be used when using the TAS instruction. Appendix A Instruction Set Legend: IMM: abs: disp: rs, rd, rn: Immediate data (2, 3, 8, 16, 32 bits) Absolute address (8, 16, 24, 32 bits) Displacement (8, 16, 32 bits) Register fields (8-bit register or 16-bit register is selected in 4 bits. rs, rd and rn correspond to the operand type Rs, Rd, and Rn respectively.) ers, erd, ern, erm: Register fields (address register or 32-bit register is selected in 3 bits. ers, erd ern and erm correspond to the operand type ERs, ERd, ERn and Rm respectively.) The following table shows the correspondence between the register field and the general register. Address Register, 32-bit Register Register Field General Register 000 001 : : : : 111 ER0 ER1 : : : : ER7 16-bit Register Register Field General Register 0000 0001 : : : : 0111 1000 1001 : : : : 1111 R0 R1 : : : : R7 E0 E1 : : : : E7 8-bit Register Register Field General Register 0000 0001 : : : : 0111 1000 1001 : : : : 1111 R0H R1H : : : : R7H R0L R1L : : : : R7L Rev.3.00 Jan. 10, 2007 page 867 of 1038 REJ09B0328-0300 BH highest bit is set to 0 2nd byte BL BH highest bit is set to 1 A.3 Instruction code: 1st byte Table A.3 AH AL BH AL 3 4 ORC OR MOV.B XOR AND SUBX SUB Table A.3(2) AH XORC ANDC LDC CMP ADDX ADD MOV 0 7 8 9 A B C D E 1 5 6 F 2 0 Table A.3(2) NOP STC LDC * * STMAC LDMAC Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) 1 Table A.3(2) Table A.3(2) Table A.3(2) 2 Appendix A Instruction Set 3 BLS BCC BVC Table A.3(2) 4 BCS BNE BEQ BVS JMP MOV EEPMOV Table A.3(3) BSR BPL BMI BGE BLT TRAPA BST MOV MOV Table A.3(2) Table A.3(2) Table A.3(2) BRA DIVXU RTS OR XOR AND BTST BSR RTE BRN BHI BGT JSR BLE 5 MULXU DIVXU MULXU Operation Code Map Operation Code Map 6 BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND ADD ADDX CMP SUBX OR XOR AND MOV BSET BNOT BCLR Table A.3 shows an operation code map. Rev.3.00 Jan. 10, 2007 page 868 of 1038 REJ09B0328-0300 7 8 9 A B C D E F Note: * Cannot be used in this LSI. Instruction code: AH AL BH BL 1st byte 2nd byte BH 1 5 6 * MAC SLEEP ADD INC INC MOV SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU NEG ROTR NEG SUB DEC DEC SUBS CMP BRN BCS BNE Table A.3(4) Table A.3(3) AH AL LDM STM STC LDC * CLRMAC Table A.3(3) 0 7 D 8 2 9 B C A 3 4 E TAS F Table A.3(3) 01 MOV 0A ADDS INC 0B ADDS INC INC 0F SHAL SHAR ROTL DAA 10 SHLR ROTXL ROTXR NOT SHLL SHAL SHAR ROTL ROTR EXTS SHAL SHAR ROTL ROTR EXTS 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS DEC DEC 1F BHI MOV CMP OR OR XOR XOR CMP SUB SUB AND AND Table A.3(4) DAS BLS * MOVFPE BCC BEQ BVC MOV BVS BPL MOV BMI 58 BRA BGE * MOVTPE BLT BGT BLE 6A ADD ADD MOV 79 MOV 7A MOV Appendix A Instruction Set Rev.3.00 Jan. 10, 2007 page 869 of 1038 REJ09B0328-0300 Note: * Cannot be used in this LSI. Instruction code: AL BH BL CH CL DH DL DH highest bit is set to 0 DH highest bit is set to 1 1st byte 2nd byte 3rd byte 4th byte AH CL 1 2 4 5 6 7 8 9 A B C D MULXS DIVXS DIVXS OR BTST BTST BNOT BNOT BTST BTST BNOT BNOT BCLR BCLR BCLR BCLR XOR AND 3 AH AL BH BL CH 0 E F 01C05 MULXS 01D05 01F06 Appendix A Instruction Set 7Cr06 *1 7Cr07 *1 7Dr06 *1 BSET BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 7Dr07 *1 BSET Rev.3.00 Jan. 10, 2007 page 870 of 1038 REJ09B0328-0300 BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 BSET 7Faa7 *2 BSET Notes: 1. 2. r is the register specification section. Absolute address is set at aa. Instruction code: AL FH highest bit is set to 0 FH highest bit is set to 1 1 BTST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 2 3 4 5 6 7 8 9 A B C D E F BH BL CH CL DH EH EL FH DL FL 1st byte 2nd byte 3th byte 4th byte 6th byte 5th byte AH EL AHALBHBLCHCLDHDLEH 0 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BNOT BCLR BSET 6A18aaaa7* Instruction code: AL BH BL CH CL DH EH EL FH DL FL 1st byte 2nd byte 3rd byte 4th byte 6th byte 5th byte 7th byte GH GL 8th byte HH HL HH highest bit is set to 0 HH highest bit is set to 1 AH GL 1 4 5 6 7 BTST 2 3 AHALBHBL ... FHFLGH 0 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BNOT BCLR BSET BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 6A38aaaaaaaa7* Appendix A Instruction Set Rev.3.00 Jan. 10, 2007 page 871 of 1038 REJ09B0328-0300 Note: * Absolute address is set at aa. Appendix A Instruction Set A.4 Number of Execution States This section explains execution state and how to calculate the number of execution states for each instruction of the H8S/2000 CPU. Table A.5 indicates number of cycles of instruction fetch and data read/write during instruction execution, and table A.4 indicates number of states required for each instruction size. The number of execution states can be obtained from the equation below. Number of execution states = I SI + J SJ + K SK + L SL + M SM + N SN Examples of execution state number calculation The conditions are as follows: In advanced mode, program and stack areas are set in the on-chip memory, a wait is inserted every 2 states in the on-chip supporting module access with 8-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5, I = L = 2, J = K = M = N = 0 From table A.4, SI = 1, SL = 2 Number of execution states = 2 x 1 + 2 x 2 = 6 2. JSR @@30 From table A.5, I = J = K = 2, L = M = N = 0 From table A.4, SI = SJ = SK = 1 Number of execution states = 2 x 1 + 2 x 1 + 2 x 1 = 6 Rev.3.00 Jan. 10, 2007 page 872 of 1038 REJ09B0328-0300 Appendix A Instruction Set Table A.4 Number of States Required for Each Execution Status (Cycle) Target of Access On-Chip Supporting Module Execution Status (Cycle) Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL Word data access SM Internal operation SN On-Chip Memory 1 8-Bit Bus -- 16-Bit Bus -- 2 4 1 1 2 2 1 Rev.3.00 Jan. 10, 2007 page 873 of 1038 REJ09B0328-0300 Appendix A Instruction Set Table A.5 Instruction Execution Status (No. of Cycles) Branch Instruction Address Fetch Read Word Stack Byte Data Data Operation Access Access K L M Internal Operation N Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs, Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx.16,Rd AND.W Rs,Rd AND L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3@aa:8 BAND #xx:3@aa:16 BAND #xx:3@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 J ADDS ADDX AND ANDC BAND 1 1 1 1 Bcc 1 1 1 1 Rev.3.00 Jan. 10, 2007 page 874 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic Bcc BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 J Word Stack Byte Data Data Operation Access Access K L M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 BCLR BIAND BILD BIOR BIST Rev.3.00 Jan. 10, 2007 page 875 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 2 2 2 2 2 2 1 J Word Stack Byte Data Data Operation Access Access K L 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 M Internal Operation N BLD BNOT BNOT BOR BSET BSR Rev.3.00 Jan. 10, 2007 page 876 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2 ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Cannot be used in this LSI. 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2n+2*2 2n+2*2 11 19 11 19 J Word Stack Byte Data Data Operation Access Access K L 1 1 1 1 1 1 1 1 1 1 1 1 M Internal Operation N BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU EEPMOV EXTS EXTU INC Rev.3.00 Jan. 10, 2007 page 877 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic JMP JMP @ERN JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LCD LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+,(ERn-ERn+1) LDM.L @SP+,(ERn-ERn+2) LDM.L @SP+,(ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ I 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 4 6 8 2 2 2 2 2 1 J Word Stack Byte Data Data Operation Access Access K L M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LDM 1 1 1 LDMAC MAC Cannot be used in this LSI. Rev.3.00 Jan. 10, 2007 page 878 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,Erd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 I 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 J Word Stack Byte Data Data Operation Access Access K L M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Rev.3.00 Jan. 10, 2007 page 879 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic MOVFPE MOVTPE MULXS MULXU NEG MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 11 19 11 19 I J Word Stack Byte Data Data Operation Access Access K L M Internal Operation N Cannot be used in this LSI. NOP NOT OR ORC POP PUSH ROTL ROTR Rev.3.00 Jan. 10, 2007 page 880 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd RPTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP I 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3*1 2 1 1 J Word Stack Byte Data Data Operation Access Access K L M Internal Operation N ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP Rev.3.00 Jan. 10, 2007 page 881 of 1038 REJ09B0328-0300 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Mnemonic STC STC.B CCR.Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L (ERn-ERn+1), @-Sp STM.L (ERn-ERn+2), @-Sp STM.L (ERn-ERn+3), @-Sp STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*3 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR I 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 4 6 8 J Word Stack Byte Data Data Operation Access Access K L M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 STM 1 1 1 STMAC SUB Cannot be used in this LSI. 1 2 1 3 1 1 1 1 2 2 1 1 2 1 3 2 1 2 2 2/3*1 2 2 SUBS SUBX TAS TRAPA XOR XORC Notes: 1. 3 applies when EXR is valid, and 2 applies when invalid. 2. Applies when the transfer data is n bytes. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Jan. 10, 2007 page 882 of 1038 REJ09B0328-0300 Appendix A Instruction Set A.5 Bus Status during Instruction Execution Table A.6 indicates execution status of each instruction available in this LSI. For the number of states required for each execution status, see table A.4, Number of States Required for Each Execution Status (Cycle). [How to see the table] Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 Internal operation 1 state 3 R:W EA 4 5 6 7 8 End of instruction Effective address is read by word. Read/write not executed The 2nd word of the instruction currently being executed is read by word. Legend: R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Read by byte Read by word Write by byte Write by word Bus not transferred immediately after this cycle Address of the 2nd word (3rd and 4th bytes) Address of the 3rd word (5th and 6th bytes) Address of the 4th word (7th and 8th bytes) Address of the 5th word (9th and 10th bytes) The head address of the instruction immediately after the instruction currently being executed Execution address Vector address Rev.3.00 Jan. 10, 2007 page 883 of 1038 REJ09B0328-0300 Appendix A Instruction Set Table A.6 Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd Instruction Execution Status 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT 2 3 4 5 6 7 8 9 ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BT d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W 2nd Internal R:W EA operation 1 state Rev.3.00 Jan. 10, 2007 page 884 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction BRN d:16 (BF d:16) 1 R:W 2nd 2 3 4 5 6 7 8 9 Internal R:W EA operation 1 state Internal R:W EA operation 1 state Internal R:W EA operation 1 state R:W EA Internal operation 1 state Internal R:W EA operation 1 state Internal R:W EA operation 1 state R:W EA Internal operation 1 state Internal R:W EA operation 1 state Internal R:W EA operation 1 state R:W EA Internal operation 1 state Internal R:W EA operation 1 state Internal R:W EA operation 1 state R:W EA Internal operation 1 state Internal R:W EA operation 1 state Internal R:W EA operation 1 state BHI d:16 R:W 2nd BLS d:16 R:W 2nd BCC d:16 (BHS d:16) R:W 2nd BCS d:16 (BLO d:16) R:W 2nd BNE d:16 R:W 2nd BEQ d:16 R:W 2nd BVC d:16 R:W 2nd BVS d:16 R:W 2nd BPL d:16 R:W 2nd BMI d:16 R:W 2nd BGE d:16 R:W 2nd BLT d:16 R:W 2nd BGT d:16 R:W 2nd BLE d:16 R:W 2nd BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT Rev.3.00 Jan. 10, 2007 page 885 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BOIR #xx:3,@aa:8 BOIR #xx:3,@aa:16 BOIR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA 2 R:W 3rd 3 R:W 4th 4 5 6 W:B EA 7 8 9 R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT Rev.3.00 Jan. 10, 2007 page 886 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn @aa:8 BNOT Rn @aa:16 BNOT Rn @aa:32 BOR #xx:3,Rd BOR #xx:3,ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 1 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT 2 3 4 5 6 7 8 9 R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B:W EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT Rev.3.00 Jan. 10, 2007 page 887 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 1 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd R:W EA W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA 2 3 4 5 6 7 8 9 R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 4th W:W:M stack(H) R:B:M EA R:W:M NEXT W:W stack(L) W:W:M stack(H) W:W stack(L) R:W EA Internal operation 1 state BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT Rev.3.00 Jan. 10, 2007 page 888 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BOXR #xx:3,Rd BOXR #xx:3,@ERd BOXR #xx:3,@aa:8 BOXR #xx:3,@aa:16 BOXR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.W #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B 1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT 2 R:B EA R:W 3rd R:W 3rd 3 R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT 4 5 6 7 8 9 Cannot be used in this LSI. R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT Internal operation 11 state Internal operation 19 state R:W 3rd R:W NEXT R:W NEXT Internal operation 11 state Internal operation 19 state R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B Ead *2 R:W NEXT Rev.3.00 Jan. 10, 2007 page 889 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 1 R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W EA Internal R:W EA operation 1 state R:W:M aa:8 R:W EA R:W:M aa:8 W:W:M stack(H) Internal R:W EA operation 1 state W:W stack (L) W:W:M stack(H) W:W stack (L) W:W stack (L) R:W EA 2 3 4 5 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B Ead *2 Repeat n times*2 6 R:W NEXT 7 8 9 JMP @@aa:8 R:W NEXT R:W NEXT R:W 2nd JSR @ERn JSR @aa:24 Internal R:W EA operation 1 state R:W:M aa:8 JSR @@aa:8 LCD #xx.8,CCR LCD #xx.8,EXR LCD Rs,CCR LCD Rs,EXR LCD @ERs,CCR LCD @ERs,EXR R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W aa:8 W:W:M stack(H) R:W NEXT R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th R:W EA R:W EA R:W 5th R:W 5th R:W NEXT R:W NEXT R:W EA R:W EA LCD @(d:16,ERs),CCR R:W 2nd LCD @(d:16,ERs),EXR R:W 2nd LCD @(d:32,ERs),CCR R:W 2nd LCD @(d:32,ERs),EXR R:W 2nd Rev.3.00 Jan. 10, 2007 page 890 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction LCD @ERs+,CCR 1 R:W 2nd 2 R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:W:M NEXT 3 4 5 6 7 8 9 Internal R:W EA operation 1 state Internal R:W EA operation 1 state R:W NEXT R:W NEXT R:W 4th R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W EA R:W EA LCD @ERs+,EXR R:W 2nd LCD @aa:16,CCR LCD @aa:16,EXR LCD @aa:32,CCR LCD @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd Internal R:W:M R:W operation stack(H)*3 stack(L)*3 1 state R:W:M Internal R:W operation stack(H)*3 stack(L)*3 1 state Internal R:W:M R:W operation stack(H)*3 stack(L)*3 1 state R:W 2nd R:W 2nd Cannot be used in this LSI. R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:B EA R:W NEXT R:W 3rd R:B EA R:W 4th R:W NEXT R:B EA Internal R:B EA operation 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd W:B EA R:W 4th R:W NEXT W:B EA R:B EA R:W NEXT R:B EA MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) Rev.3.00 Jan. 10, 2007 page 891 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction MOV.B Rs,@-ERd 1 R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W:M EA R:W EA+2 R:W NEXT R:W:M EA R:W EA+2 R:W NEXT R:W:M EA R:W EA+2 R:W EA R:W NEXT R:W 3rd R:W EA R:W 4th R:W NEXT R:W EA 2 3 4 5 6 7 8 9 Internal W:B EA operation 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd Internal R:W EA operation 1 state R:W NEXT R:W 3rd W:W EA R:W NEXT R:W 3rd W:W EA R:W 4th R:W NEXT W:W EA R:W EA R:W NEXT R:B EA MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd Internal W:W EA operation 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M 4th R:W 5th R:W:M EA R:W EA+2 Internal operation 1 state Rev.3.00 Jan. 10, 2007 page 892 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd 2 R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W:M 3rd R:W:W 3rd R:W:M NEXT R:W:M 3rd R:W:M 3rd 3 R:W NEXT R:W 4th W:W:M EA R:W NEXT 4 5 6 7 8 9 R:W:M EA R:W EA+2 R:W NEXT W:W EA+2 W:W:M EA W:W EA+2 R:W NEXT W:W EA+2 W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA W:W EA+2 R:W:M EA R:W EA+2 R:W:M 4th R:W 5th Internal W:W:M operation EA 1 state R:W NEXT R:W 4th W:W:M EA R:W NEXT MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,Rd MULXU.B Rs,Rd MULXU.W Rs,Rd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd R:W 2nd R:W 2nd Cannot be used in this LSI. R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation 11 state Internal operation 19 state Internal operation 11 state Internal operation 19 state Rev.3.00 Jan. 10, 2007 page 893 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn 1 R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT Internal R:W EA operation 1 state R:W:M NEXT Internal R:W:M EA R:W EA+2 operation 1 state 2 R:W NEXT 3 4 5 6 7 8 9 POP.L ERn PUSH.W Rn R:W NEXT R:W 2nd Internal W:W EA operation 1 state R:W:M NEXT Internal W:W:M operation EA 1 state W:W EA+2 PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2, ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2.Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Rev.3.00 Jan. 10, 2007 page 894 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2.ERd RTE 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W stack (EXR) R:W:M stack(H) R:W stack(H) R:W stack(L) R:W stack(L) Internal operation 1 state Internal R:W*4 operation 1 state 4 R:W* 2 3 4 5 6 7 8 9 RTS SHAL.B Rd SHAL B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd Rev.3.00 Jan. 10, 2007 page 895 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W:M NEXT W:W EA W:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th W:W EA W:W EA R:W 5th R:W 5th R:W NEXT R:W NEXT W:W EA W:W EA Internal operation: M 2 3 4 5 6 7 8 9 STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) R:W 2nd STC CCR,@(d:32,ERd) R:W 2nd STC EXR,@(d:32,ERd) R:W 2nd STC CCR,@-ERd R:W 2nd Internal W:W EA operation 1 state Internal W:W EA operation 1 state R:W NEXT R:W NEXT R:W 4th R:W 4th W:W EA W:W EA R:W NEXT R:W NEXT W:W EA W:W EA W:W stack (L)*3 STC EXR,@-ERd R:W 2nd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L (ERnERn+1),@-SP R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd W:W:M Internal operation stack (H) *3 1 state Rev.3.00 Jan. 10, 2007 page 896 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction STM.L (ERnERn+2),@-SP STM.L (ERnERn+3),@-SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUB #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*8 TRAPA #x:2 R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:B:M EA W:B EA W:W stack(H) W:W stack (EXR) R:W:M VEC R:W VEC+2 R:W*7 Internal operation 1 state R:W 3nd R:W NEXT R:W NEXT 1 R:W 2nd 2 R:W:M NEXT R:W:M NEXT 3 4 5 W:W stack (L)*3 W:W stack (L)*3 6 7 8 9 Internal W:W:M operation stack (H) *3 1 state Internal W:W:M operation stack (H) *3 1 state R:W 2nd Cannot be used in this LSI. Internal W:W operation stack(L) 1 state XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Rev.3.00 Jan. 10, 2007 page 897 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction Reset exception handling Interrupt exception handling 1 R:W:M VEC R:W* 6 2 R:W VEC+2 3 4 5 6 7 8 9 R:W*5 Internal operation 1 state W:W stack(H) W:W stack (EXR) R:W:M VEC R:W VEC+2 R:W*7 Internal operation 1 state Internal W:W operation stack(L) 1 state Notes: 1. EAs is the contents of ER5, and EAd is the contents of ER6. 2. 1 is added to EAs and EAd after execution. n is the initial value of R4L or R4. When 0 is set to n, R4L or R4 is not executed. 3. Repeated twice for 2-unit retract/return, three times for 3-unit retract/return, and four times for 4-retract/return. 4. Head address after return. 5. Start address of the program. 6. Pre-fetch address obtained by adding 2 to the PC to be retracted. When returning from sleep mode, standby mode or watch mode, internal operation is executed instead of read operation. 7. Head address of the interrupt process routine. 8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.3.00 Jan. 10, 2007 page 898 of 1038 REJ09B0328-0300 Appendix A Instruction Set A.6 Change of Condition Codes This section explains change of condition codes after instruction execution of the CPU. Legend of the following tables is as follows. m = 31: Longword size m = 15: Word size m = 7: Byte size Si: Di: Ri: Dn: : : 0: 1: *: Z': C': Bit i of source operand Bit i of destination operand Bit i of result Specified bit of destination operand No affection Changes depending on execution result Always cleared to 0 Always set to 1 Value undetermined Z flag before execution C flag before execution Rev.3.00 Jan. 10, 2007 page 899 of 1038 REJ09B0328-0300 Appendix A Instruction Set Table A.7 Change of Condition Code N Z V C Definition H=Sm-4Dm-4+Dm-4Rm-4+Sm-4Rm-4 N=Rm Z=RmRm-1 R0 V=SmDmRm+SmDmRm C=SmDm+DmRm+SmRm H=Sm-4Dm-4+Dm-4Rm-4+Sm-4Rm-4 N=Rm Z=Z'Rm R0 V=SmDmRm+SmDmRm C=SmDm+DmRm+SmRm - 0 - N=Rm Z= RmRm-1 R0 Instruction H ADD ADDS ADDX AND ANDC Value in the bit corresponding to execution result is stored. No flag change when EXR. Z=Dn C=C'Dn+C'Dn C=C'+Dn C=C'Dn+C'Dn C=Dn C=C'Dn C=Dn C=C'+Dn C=C'Dn BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC Cannot be used in this LSI. Rev.3.00 Jan. 10, 2007 page 900 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction H CMP N Z V C Definition H=Sm-4Dm-4+Dm-4Rm-4+Sm-4Rm-4 N=Rm Z=RmRm-1 R0 V=SmDmRm+SmDmRm C=SmDm+DmRm+SmRm * * N=Rm Z=RmRm-1 R0 C: Decimal addition carry N=Rm Z=RmRm-1 R0 C: Decimal subtraction borrow N=Rm Z=RmRm-1 V=DmRm R0 DAA DAS * * DEC DIVXS DIVXU EEPMOV EXTS EXTU INC 0 0 0 N=SmDm+SmDm Z=SmSm-1 S0 N=Sm Z=SmSm-1 S0 N=Rm Z=RmRm-1 Z=RmRm-1 N=Rm Z=RmRm-1 V=DmRm R0 R0 R0 JMP JSR LDC Value in the bit corresponding to execution result is stored. No flag change when EXR. LDM LDMAC MAC MOV Cannot be used in this LSI. 0 N=Rm Z=RmRm-1 R0 Rev.3.00 Jan. 10, 2007 page 901 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction H MOVFPE MOVTPE MULXS MULXU NEG H=Dm-4+Rm-4 N=Rm Z=RmRm-1 V=DmRm C=Dm+Rm 0 0 N=Rm Z=RmRm-1 N=Rm Z=RmRm-1 R0 R0 N=R2m Z=R2mR2m-1 R0 N Z V C Definition Cannot be used in this LSI. R0 NOP NOT OR ORC POP PUSH ROTL Value in the bit corresponding to execution result is stored. No flag change when EXR. 0 0 0 N=Rm Z=RmRm-1 N=Rm Z=RmRm-1 R0 R0 N=Rm Z=RmRm-1 R0 C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) N=Rm Z=RmRm-1 R0 C=D0(In case of 1 bit), C=D1(In case of 2 bits) N=Rm Z=RmRm-1 R0 C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) N=Rm Z=RmRm-1 R0 C=D0(In case of 1 bit), C=D1(In case of 2 bits) Value in the bit corresponding to execution result is stored. ROTR 0 ROTXL 0 ROTXR 0 RTE RTS Rev.3.00 Jan. 10, 2007 page 902 of 1038 REJ09B0328-0300 Appendix A Instruction Set Instruction H SHAL N Z V C Definition N=Rm Z=RmRm-1 R0 V = Dm * Dm-1 + Dm * Dm-1 (In case of 1-bit) V = Dm * Dm-1 * Dm-2 * Dm * Dm-1 * Dm-2 (In case of 2-bit) C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) SHAR 0 N=Rm Z=RmRm-1 R0 C=D0(In case of 1 bit), C=D1(In case of 2 bits) N=Rm Z=RmRm-1 R0 C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) N=Rm Z=RmRm-1 R0 C=D0(In case of 1 bit), C=D1(In case of 2 bits) SHLL 0 SHLR 0 0 SLEEP STC STM STMAC SUB Cannot be used in this LSI. H=Sm-4Dm-4+Dm-4Rm-4+Sm-4Rm-4 N=Rm Z=RmRm-1 R0 V=SmDmRm+SmDmRm C=SmDm+DmRm+SmRm H=Sm-4Dm-4+Dm-4Rm-4+Sm-4Rm-4 N=Rm Z=Z'Rm R0 V=SmDmRm+SmDmRm C=SmDm+DmRm+SmRm 0 0 N=Rm Z=RmRm-1 R0 N=Dm Z=DmDm-1 D0 SUBS SUBX TAS TRAPA XOR XORC Value in the bit corresponding to execution result is stored. No flag change when EXR. Rev.3.00 Jan. 10, 2007 page 903 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.1 Addresses R/W W Bus Access Width 7 16 16 DGKp15 DGKp7 DGKs W 16 16 DGKs15 DGKs7 DAp W 16 16 DAp15 DAp7 DBp W 16 16 DBp15 DBp7 DAs W 16 16 DAs15 DAs7 DBs W 16 16 DBs15 DBs7 DOfp W 16 16 DOfp15 DOfp7 DOfs W 16 16 DOfs15 DOfs7 CGKp W 16 16 CGKp15 CGKp7 CGKs W 16 16 CGKs15 CGKs7 CAp W 16 16 CAp15 CAp7 CBp W 16 16 CBp15 CBp7 CAs W 16 16 CAs15 CAs7 CBs W 16 16 CBs15 CBs7 COfp W 16 16 COfp15 COfp7 COfs W 16 16 COfs15 COfs7 6 DGKp14 DGKp6 DGKs14 DGKs6 DAp14 DAp6 DBp14 DBp6 DAs14 DAs6 DBs14 DBs6 DOfp14 DOfp6 DOfs14 DOfs6 CGKp14 CGKp6 CGKs14 CGKs6 CAp14 CAp6 CBp14 CBp6 CAs14 CAs6 CBs14 CBs6 COfp14 COfp6 COfs14 COfs6 5 DGKp13 DGKp5 DGKs13 DGKs5 DAp13 DAp5 DBp13 DBp5 DAs13 DAs5 DBs13 DBs5 DOfp13 DOfp5 DOfs13 DOfs5 CGKp13 CGKp5 CGKs13 CGKs5 CAp13 CAp5 CBp13 CBp5 CAs13 CAs5 CBs13 CBs5 COfp13 COfp5 COfs13 COfs5 4 DGKp12 DGKp4 DGKs12 DGKs4 DAp12 DAp4 DBp12 DBp4 DAs12 DAs4 DBs12 DBs4 DOfp12 DOfp4 DOfs12 DOfs4 CGKp12 CGKp4 CGKs12 CGKs4 CAp12 CAp4 CBp12 CBp4 CAs12 CAs4 CBs12 CBs4 COfp12 COfp4 COfs12 COfs4 3 DGKp11 DGKp3 DGKs11 DGKs3 DAp11 DAp3 DBp11 DBp3 DAs11 DAs3 DBs11 DBs3 DOfp11 DOfp3 DOfs11 DOfs3 CGKp11 CGKp3 CGKs11 CGKs3 CAp11 CAp3 CBp11 CBp3 CAs11 CAs3 CBs11 CBs3 COfp11 COfp3 COfs11 COfs3 2 DGKp10 DGKp2 DGKs10 DGKs2 DAp10 DAp2 DBp10 DBp2 DAs10 DAs2 DBs10 DBs2 DOfp10 DOfp2 DOfs10 DOfs2 CGKp10 CGKp2 CGKs10 CGKs2 CAp10 CAp2 CBp10 CBp2 CAs10 CAs2 CBs10 CBs2 COfp10 COfp2 COfs10 COfs2 1 DGKp9 DGKp1 DGKs9 DGKs1 DAp9 DAp1 DBp9 DBp1 DAs9 DAs1 DBs9 DBs1 DOfp9 DOfp1 DOfs9 DOfs1 CGKp9 CGKp1 CGKs9 CGKs1 CAp9 CAp1 CBp9 CBp1 CAs9 CAs1 CBs9 CBs1 COfp9 COfp1 COfs9 COfs1 0 DGKp8 DGKp0 DGKs8 DGKs0 DAp8 DAp0 DBp8 DBp0 DAs8 DAs0 DBs8 DBs0 DOfp8 DOfp0 DOfs8 DOfs0 CGKp8 CGKp0 CGKs8 CGKs0 CAp8 CAp0 CBp8 CBp0 CAs8 CAs0 CBs8 CBs0 COfp8 COfp0 COfs8 COfs0 Capstan digital filter Module Name Drum digital filter Register Address* Name H'D000 H'D001 H'D002 H'D003 H'D004 H'D005 H'D006 H'D007 H'D008 H'D009 H'D00A H'D00B H'D00C H'D00D H'D00E H'D00F H'D010 H'D011 H'D012 H'D013 H'D014 H'D015 H'D016 H'D017 H'D018 H'D019 H'D01A H'D01B H'D01C H'D01D H'D01E H'D01F DGKp Rev.3.00 Jan. 10, 2007 page 904 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'D020 H'D021 H'D022 H'D023 H'D024 H'D025 H'D026 H'D027 H'D028 H'D029 H'D02A H'D030 H'D031 H'D032 H'D033 H'D034 H'D035 H'D036 H'D037 H'D038 H'D039 H'D03A H'D03B H'D03C H'D03D H'D03E H'D03F H'D050 H'D051 H'D052 H'D053 H'D054 H'D055 H'D056 H'D057 H'D058 H'D059 CFVCR CPGCR R/W R/W 8 8 16 16 CFRLDR W 16 16 CFRUDR W 16 16 CFER R/W 16 16 CFPR W 16 16 DPPR1 DPER1 DPER2 W W W 8 8 16 16 16 16 DFVCR DPGCR DPPR2 R/W R/W W 8 8 16 16 16 16 DFRLDR W 16 16 DFRUDR W 16 16 DFER R/W 16 16 DFIC CFIC DFUCR DFPR R/W R/W R/W W 8 8 8 16 16 16 16 CZp W 16 16 CZs W 16 16 DZp W 16 16 DZs R/W W Bus Access Width 7 16 16 DZs7 DZp7 CZs7 CZp7 DFPR15 DFPR7 DFER15 DFER7 6 DZs6 DZp6 CZs6 CZp6 DROV CROV DFPR14 DFPR6 DFER14 DFER6 5 DZs5 DZp5 CZs5 CZp5 DPHA CPHA PTON DFPR13 DFPR5 DFER13 DFER5 4 DZs4 DZp4 CZs4 CZp4 DZPON CZPON CP/DP DFPR12 DFPR4 DFER12 DFER4 3 DZs11 DZs3 DZp11 DZp3 CZs11 CZs3 CZp11 CZp3 DZSON CZSON CFEPS DFPR11 DFPR3 DFER11 DFER3 2 DZs10 DZs2 DZp10 DZp2 CZs10 CZs2 CZp10 CZp2 DSG2 CSG2 DFEPS DFPR10 DFPR2 DFER10 DFER2 1 DZs9 DZs1 DZp9 DZp1 CZs9 CZs1 CZp9 CZp1 DSG1 CSG1 CFESS DFPR9 DFPR1 DFER9 DFER1 0 DZs8 DZs0 DZp8 DZp0 CZs8 CZs0 CZp8 CZp0 DSC0 CSG0 DFESS DFPR8 DFPR0 DFER8 DFER0 Drum error detector Module Name Digital filter DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR9 DFRUDR8 5 4 3 2 1 0 DFRUDR7 DFRUDR6 DFRUDR5 DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0 DFRLDR1 DFRLDR1 DFRLDR1 DFRLDR1 DFRLDR1 DFRLDR1 DFRLDR9 DFRLDR8 5 4 3 2 1 0 DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0 DFCS1 DPCS1 DPPR15 DPPR7 DPER15 DPER7 CFPR15 CFPR7 CFER15 CFER7 DFCS0 DPCS0 DPPR14 DPPR6 DPER14 DPER6 CFPR14 CFPR6 CFER14 CFER6 DFOVF DPOVF DPPR13 DPPR5 DPER13 DPER5 CFPR13 CFPR5 CFER13 CFER5 DFRFON DF-R/UNR OPCNT N/V DPPR12 DPPR4 DPER12 DPER4 CFPR12 CFPR4 CFER12 CFER4 HSWES DPPR11 DPPR3 DPPR19 DPER19 DPER11 DPER3 CFPR11 CFPR3 CFER11 CFER3 DPPR10 DPPR2 DPPR18 DPER18 DPER10 DPER2 CFPR10 CFPR2 CFER10 CFER2 DFRCS1 DPPR9 DPPR1 DPPR17 DPER17 DPER9 DPER1 CFPR9 CFPR1 CFER9 CFER1 DFRCS0 DPPR8 DPPR0 DPPR16 DPER16 DPER8 DPER0 CFPR8 CFPR0 CFER8 CFER0 Capstan error detector CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR9 CFRUDR8 5 4 3 2 1 0 CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0 CFRLDR1 CFRLDR1 CFRLDR1 CFRLDR1 CFRLDR1 CFRLDR1 CFRLDR9 CFRLDR8 5 4 3 2 1 0 CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0 CFCS1 CPCS1 CFCS0 CPCS0 CFOVF CPOVF CFRFON CF-R/UNR CPCNT CR/RF SELCFG2 CFRCS1 CFRCS0 Rev.3.00 Jan. 10, 2007 page 905 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'D05A H'D05B H'D05C H'D05D H'D05E H'D05F H'D060 H'D061 H'D062 H'D064 H'D065 H'D066 H'D066 H'D067 H'D067 H'D068 H'D069 H'D06A H'D06B H'D06C H'D06C H'D06D H'D06E DFCTR* DFCRB DFCRB CHCR W R W W 8 8 8 8 16 16 16 FTPRB W 16 16 FTPRA* FTCTR* FTPRA* FTCTR* FPDRB W R W R W 16 16 16 16 16 16 16 16 HSM1 HSM2 HSLP FPDRA R/W R/W W W 8 8 8 16 16 16 16 CPPR1 CPER1 CPER2 W W W 8 8 16 16 16 16 CPPR2 R/W W Bus Access Width 7 16 16 CPH15 CPH7 CPER15 CPER7 FLB FRT LOB3 PPGA7 6 CPH14 CPH6 CPER14 CPER6 FLA 5 CPH13 CPH5 CPER13 CPER5 EMPB 4 CPH12 CPH4 CPER12 CPER4 EMPA EDG LOB0 3 CPH11 CPH3 CPH19 CPER19 CPER11 CPER3 OVWB ISEL LOA3 2 CPH10 CPH2 CPH18 CPER18 CPER10 CPER2 OVWA SOFG LOA2 AFFA PPGA2 1 CPH9 CPH1 CPH17 CPER17 CPER9 CPER1 CLRB OFG LOA1 VpulseA PPGA1 0 CPH8 CPH0 CPH16 CPER16 CPER8 CPER0 CLRA HSW timing VFF/NFF generator * Assign LOA0 to the MlevelA same address. PPGA0 FTRPA8 FTCTR8 FTPRA0 FTCTR0 MlevelB PPGB0 FTPRB8 FPTRB0 DFCRA0 DFCTR0 DFCRB0 SIG0 4-head specialeffects playback Additional V X-value, TRK-value Module Name Capstan error detector FGR2OFF LOP LOB2 LOB1 ADTRGA STRIGA PPGA6 PPGA5 NarrowFF VFFA A PPGA4 PPGA3 FTPRA15 FTRPA14 FTRPA13 FTRPA12 FTRPA11 FTRPA10 FTRPA9 FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTPRA7 FTCTR7 PPGB7 FTPRA6 FTCTR6 FTPRA5 FTCTR5 FTPRA4 FTCTR4 FTPRA3 FTCTR3 FTPRA2 FTCTR2 AFFB PPGB2 FTPRA1 FTCTR1 VpulseB PPGB1 ADTRGB STRIGB PPGB6 PPGB5 NarrowFF VFFB B PPGB4 PPGB3 FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB7 ISEL2 V/N FTPRB6 CCLR FTPRB5 CKSL FTPRB4 DFCRA4 DFCTR4 DFCRB4 HAH FPTRB3 DFCRA3 DFCTR3 DFCRB3 SIG3 FPTRB2 DFCRA2 DFCTR2 DFCRB2 SIG2 FPTRB1 DFCRA1 DFCTR1 DFCRB1 SIG1 HSWPOL CRH H'D06F H'D070 H'D071 H'D072 H'D073 H'D074 H'D078 H'D079 H'D07A H'D07B H'D07C H'D07D ADDVR XDR R/W W 8 16 16 XR7 XR6 TRD6 CAPRF XR5 TRD5 AT/MU HMSK XR4 TRD4 TRK/X Hi-Z XR11 XR3 TRD11 TRD3 CUT XR10 XR2 TRD10 TRD2 VPON XR9 XR1 TRD9 TRD1 DVRER1 POL XR8 XR0 TRD8 TRD0 DVREF0 TRDR W 16 16 TRD7 XTCR DPWDR R/W R/W 8 16 16 16 EXC/REF XCS DPWDR11 DPWDR10 DPWDR9 DPWDR8 Drum 12bit PWM DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0 DPOL CPOL DDC CDC DHIZ CHIZ DH/L CH/L DSFDF CSF/DF DCK2 CCK2 DCK1 CCK1 DCK0 DPWCR CPWCR CPWDR W W R/W 8 8 16 16 16 CCK0 Capstan 12-bit CPWDR11 CPWDR10 CPWDR9 CPWDR8 PWM CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 Rev.3.00 Jan. 10, 2007 page 906 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'D080 H'D081 H'D082 H'D083 H'D084 H'D085 H'D086 H'D087 H'D088 H'D089 H'D08A H'D08B H'D08C H'D08D H'D090 H'D091 H'D092 H'D093 H'D094 H'D095 H'D096 H'D097 H'D098 H'D099 H'D09A H'D09B H'D09C H'D09D H'D09E H'D0A0 H'D0A1 H'D0A2 H'D0A3 H'D0A4 H'D0B0 H'D0B1 H'D0B2 H'D0B3 H'D0B4 H'D0B5 H'D0B6 RFM RFM2 CTVC CTLR CDVC CDIVR1 CDIVR2 CTMR FGCR SPMR SPCR SPDR SVMCR CTLGR VTR HTR HRTR HPWR NWR NDR SYNCR R/W R/W R/W W R/W W W W W R/W R/W R/W R/W R/W W W W W W W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 RFC R/W 16 16 CRF W 16 16 DI/O BTPR RFD R/W R/W W 8 8 16 16 16 RCDR5 W 16 16 RCDR4 W 16 16 RCDR3 W 16 16 RCDR2 W 16 16 CTCR CTLM RCDR1 R/W W R/W W Bus Access Width 7 8 8 16 16 16 NT/PAL ASM CMT17 CMT27 CMT37 CMT47 CMT57 VCTR2 LSP7 REF15 REF7 CRF15 CRF7 RFC15 RFC7 RCF (TBC)* CEX CTL7 MCGain CDV16 CDV26 6 FLSC REC/PB CMT16 CMT26 CMT36 CMT46 CMT56 VCTR1 LSP6 REF14 REF6 CRF14 CRF6 RFC14 RFC6 VNA CEG CTL6 5 FLSB FW/RV CMT15 CMT25 CMT35 CMT45 CMT55 VCTR0 LSP5 REF13 REF5 CRF13 CRF5 RFC13 RFC5 CVS CTL5 CMK CDV15 CDV25 CPM5 4 FSLA MD4 CMT14 CMT24 CMT34 CMT44 CMT54 LSP4 REF12 REF4 CRF12 CRF4 RFC12 RFC4 REX CTL4 CMN CDV14 CDV24 CPM4 3 CCS MD3 CMT1B CMT13 CMT2B CMT23 CMT3B CMT33 CMT4B CMT43 CMT5B CMT53 BPON LSP3 REF11 REF3 CRF11 CRF3 RFC11 RFC3 CRD CTL3 DVTRG CDV13 CDV23 CPM3 2 LCTL MD3 CMT1A CMT12 CMT2A CMT22 CMT3A CMT32 CMT4A CMT42 CMT5A CMT52 BPS LSP2 REF10 REF2 CRF10 CRF2 RFC10 RFC2 OD/EV CFG CTL2 CRF CDV12 CDV22 CPM2 COMP SPCR2 SPDR2 1 UNCTL MD1 CMT19 CMT11 CMT29 CMT21 CMT39 CMT31 CMT49 CMT41 CMT59 CMT51 BPF LSP1 REF9 REF1 CRF9 CRF1 RFC9 RFC1 VST HSW CTL1 CPS1 CDV11 CDV21 CPM1 H.Amp.S W SPCR1 SPDR1 0 SLWM MD0 CMT18 CMT10 CMT28 CMT20 CMT38 CMT30 CMT48 CMT40 CMT58 CMT50 DI/O LSP0 REF8 REF0 CRF8 CRF0 RFC8 RFC0 VEG FDS CTL CTL0 CPS0 CDV10 CDV20 CPM0 DRF C.Rot SPCR0 SPDR0 Servo port control * The TBC bit is available only in the H8S/2194 C Group. Frequency divider Reference signal generator Module Name CTL circuit CTLSTOP HRTR7 NDR7 HRTR6 NDR6 CFGCOM EXCELON DPGSW P SPCR4 SPDR4 SPCR3 SPDR3 SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 VTR5 HRTR5 NWR5 NDR5 CTLFB VTR4 HRTR4 NWR4 NDR4 CTLGR3 VTR3 HTR3 HRTR3 HPWR3 NWR3 NDR3 NID/VD CTLGR2 VTR2 HTR2 HRTR2 HPWR2 NWR2 NDR2 NOIS CTLGR1 VTR1 HTR1 HRTR1 HPWR1 NWR1 NDR1 FLD CTLGR0 VTR0 HTR0 HRTR0 HPWR0 NWR0 NDR0 SYCT Sync detector Rev.3.00 Jan. 10, 2007 page 907 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'D0B8 H'D0B9 H'D0BA H'D0BB H'D0C0 H'D0C1 H'D0C2 H'D0C3 H'D0C4 H'D0C5 H'D0C6 H'D0C7 H'D0C8 H'D0C9 H'D0CA H'D0CB H'D0CC H'D0CD H'D0CE H'D0CF H'D0D0 H'D0D1 H'D0D2 H'D0D3 H'D0D4 H'D0D5 H'D0D6 H'D0D7 H'D0D8 H'D0D9 H'D0DA H'D0DB H'D0DC H'D0DD H'D0DE H'D0DF H'D0E0 H'D0E1 H'D0E2 H'D0E3 STAR EDAR SCR2 SCSR2 SIENR1 SIENR2 SIRQR1 SIRQR2 R/W R/W R/W R/W R/W Bus Access Width 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 TEIE TEI ABTIE STA4 EDA4 GAP1 SOL STA3 EDA3 GAP0 ORER STA2 EDA2 CKS2 WT STA1 EDA1 CKS1 ABT STA0 EDA0 CKS0 STF IEDR3 6 IEDR2 5 IEDR1 4 IECAP3 3 IECAP2 2 IECAP1 1 IEHSW2 IESNC 0 IEHSW1 IESTL Module Name Servo interrupt control IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 IRRSNC IRRCTL 32-byte buffer SCI2 32 byte R/W Data Buffer R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.3.00 Jan. 10, 2007 page 908 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'D100 H'D101 H'D102 H'D103 H'D104 H'D105 H'D104 H'D105 H'D106 H'D107 H'D108 H'D109 H'D10A H'D10B H'D10C H'D10D H'D10E H'D10F H'D110 H'D111 H'D111 H'D112 H'D113 H'D113 H'D118 H'D119 H'D11A H'D11B H'D11C H'D11D H'D11E H'D11F H'D120 H'D121 H'D122 H'D126 H'D127 H'D128 H'D129 H'D12A H'D12C H'D12D TIER TCSRX FRCH FRCL OXRAH* OCRAL* OCRBH* OCRBL* TCRX TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL TMB TCB TLB LMR LTC RCR TMRM1 TMRM2 TMRCP1 TMRCP2 TMRL1 TMRL2 TMRL3 TMRCS PWDRL PWDRU PWCR PWR0 PWR1 PWR2 PWR3 PW8CR ICR1 PCSR R/W R W R/W R W R/W R/W R R W W W R/W W W R/W W W W W R/W R R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R 8/16 16 R 8/16 16 R 8/16 16 R/W R/W R 8 8 8/16 16 16 16 R/W 8/16 16 R/W 8/16 16 R/W R/W R/W R/W Bus Access Width 7 8 8 8/16 16 16 16 ICIAE ICFA 6 ICIBE ICFB 5 ICICE ICFC 4 ICIDE ICFD 3 OCIAE OCFA 2 OCIBE OCFB 1 OVIE OVF 0 ICSA Module Name Timer X1 * OCRA and OCRB addresses FRCH7 FRCH6 FRCH5 FRCH4 FRCH3 FRCH2 FRCH1 FRCH0 are the FRCL7 FRCL6 FRCL5 FRCL4 FRCL3 FRCL2 FRCL1 FRCL0 same. Switched OCRAH7 OCRAH6 OCRAH5 OCRAH4 OCRAH3 OCRAH2 OCRAH1 OCRAH0 by OCSR OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0 bit in IOCR. OCRBH7 CORBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0 CCLRA OCRBL7 IEDGA OCRBL6 IEDGB ICSC ICRAH6 ICRAL6 ICRBH6 ICRBL6 ICRCH6 ICRCL6 ICRDH6 ICRDL6 TMBIF TCB16 TLB16 LMIE LTC6 RCR6 AC/BR RS11 TMRC16 TMRC26 TMR16 TMR26 TMR36 TMRI2E OCRBL5 IEDGC ICSD ICRAH5 ICRAL5 ICRBH5 ICRBL5 ICRCH5 ICRCL5 ICRDH5 ICRDL5 TMPIE TCB15 TLB15 LTC5 RCR5 RLD PS10 TMRC15 TMRC25 TMR15 TMR25 TMR35 TMRI1E CORBL4 IEDGD OCRS ICRAH4 ICRAL4 ICRBH4 ICRBL4 ICRCH4 ICRCL4 ICRDH4 ICRDL4 TCB14 TLB14 LTC4 RCR4 RLCK PS31 TMRC14 TMRC24 TMR14 TMR24 TMR34 TMRI3 CORBL3 BUFEA OEA ICRAH3 ICRAL3 ICRBH3 ICRBL3 ICRCH3 ICRCL3 ICRDH3 ICRDL3 TCB13 TLB13 LMR3 LTC3 RCR3 PS21 PS30 TMRC13 TMRC23 TMR13 TMR23 TMR33 TMRI2 CORBL2 FUFEB OEB ICRAH2 ICRAL2 ICRBH2 ICRBL2 ICRCH2 ICRCL2 ICRDH2 ICRDL2 TMP12 TCB12 TLB12 LMR2 LTC2 RCR2 PC20 CP/SLM TMRC12 TMRC22 TMR12 TMR22 TMR32 TMRI1 CORBL1 CKS1 OLVLA ICRAH1 ICRAL1 ICRBH1 ICRBL1 ICRCH1 ICRCL1 ICRDH1 ICRDL1 TMP11 TCB11 TLB11 LMR1 LTC1 RCR1 CORBL0 CKS0 OLVLB ICRAH0 ICRAL0 ICRBH0 ICRBL0 ICRCH0 ICRCL0 ICRDH0 ICRDL0 TCB10 TCB10 TLB10 LMR0 LTC0 RCR0 Timer R Timer L Timer B ICSB ICRAH7 ICRAL7 ICRBH7 ICRBL7 ICRCH7 ICRCL7 ICRDH7 ICRDL7 TMB17 TCB17 TLB17 LMIF LTC7 RCR7 CLR2 LAT TMRC17 TMRC27 TMR17 TMR27 TMR37 TMRI3E RLD/CAP CPS CAPF TMRC11 TMRC21 TMR11 TMR21 TMR31 SLW TMRC10 TMRC20 TMR10 TMR20 TMR30 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 14-bit PWM PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PW07 PW17 PW27 PW37 ICR17 ICIF PW06 PW16 PW26 PW36 ICR16 ICIE PW05 PW15 PW25 PW35 ICR15 ICEG PW04 PW14 PW24 PW34 ICR14 NCon/off PW03 PW13 PW23 PW33 PWC3 ICR13 PW02 PW12 PW22 PW32 PWC2 ICR12 DCS2 PW01 PW11 PW21 PW31 PWC1 ICR11 DCS1 PWMCR0 PW00 PW10 PW20 PW30 PWC0 CIR10 DCS0 PSU 8-bit PWM Rev.3.00 Jan. 10, 2007 page 909 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'D130 H'D131 H'D132 H'D133 H'D134 H'D135 H'D136 H'D138 H'D138 H'D139 H'D139 H'D13A H'D13B H'D13C H'D148 H'D149 H'D14A H'D14B H'D14C H'D14D H'D14E H'D158 H'D159 H'D15E H'D15E H'D15F H'D15F H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD TRCR TMA TCA WTCSR WTCNT R/W R/W R R/W R/W 8 8 8 8/16 8/16 8 8 8 16 16 TAR2 R/W 8 8 TAR1 R/W 8 8 ADRH ADRL AHRH AHRL ADCR ADCSR ADTSR TLK TCK TLJ TCJ TMJ TMJC TMJS SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 ICCR ICSR ICDR* SARX* ICMR* SAR* TAR0 R/W R/W R/W W R W R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8/16 8/16 8/16 8/16 8/16 8/16 8/16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ICE ESTP ICDR7 SVAX6 MLS SVA6 TA023 TA015 TA007 TA123 TA115 TA107 TA223 TA215 TA207 TMAOV TCA7 OVF IEIC STOP ICDR6 SVAX5 WAIT SVA5 TA022 TA014 TA006 TA122 TA114 TA106 TA222 TA214 TA206 TMAIE TCA6 WT/IT MST IRTR ICDR5 SVAX4 CKS2 SVA4 TA021 TA013 TA005 TA121 TA113 TA105 TA221 TA213 TA205 TCA5 TME TRS AASX ICDR4 SVAX3 CKS1 SVA3 TA020 TA012 TA004 TA120 TA112 TA104 TA220 TA212 TA204 TCA4 RSTS SDIR ACKE AL ICDR3 SVAX2 CKS0 SVA2 TA019 TA011 TA003 TA119 TA111 TA103 TA219 TA211 TA203 TMA3 TCA3 SINV BBSY AAS ICDR2 SVAX1 BC2 SVA1 TA018 TA010 TA002 TA118 TA110 TA102 TA218 TA210 TA202 TRC2 TMA2 TCA2 IRIC ADZ ICDR1 SVAX0 BC1 SVA0 TA017 TA009 TA001 TA117 TA109 TA101 TA217 TA209 TA201 TRC1 TMA1 TCA1 CKS1 TRC0 TMA0 TCA0 CKS0 WDT Timer A TA216 TA208 TA116 TA108 SMIF SCP ACKB ICDR0 FSX BC0 FS TA016 TA008 ATC IIC interface * Access varies depending on ICE bit. TDRE RDRF ORER FER PER TEMD MPB MPBT TEI RIE TE RE MPIE TEIE CKE1 CKE0 R 16 8 R/W R Bus Access Width 7 16 8 ADR9 ADR1 AHR9 AHR1 CK SEND TLR27 TLR17 TDR27 TDR17 PS11 BUZZ1 TMJ2I C/A 6 ADR8 ADR0 AHR8 AHR0 HEND TLR26 TLR16 TDR26 TDR16 PS10 BUZZ0 TMJ1I CHR 5 ADR7 AHR7 HCH1 ADIE TLR25 TLR15 TDR25 TDR15 ST MON1 PE 4 ADR6 AHR6 HCH0 SST TLR24 TLR14 TDR24 TDR14 8/16 MON0 O/E STOP 3 ADR5 AHR5 SCH3 HST TLR23 TLR13 TDR23 TDR13 PS21 2 ADR4 AHR4 SCH2 BUSY TLR22 TLR12 TDR22 TDR12 PS20 TMJ2IE MP 1 ADR3 AHR3 SCH1 SCNL TRGS1 TLR21 TLR11 TDR21 TDR11 TGL TMJ1IE CKS1 TRGS0 TLR20 TLR10 TDR20 TDR10 T/R (PS22)* CKS0 * The PS22 bit is available only in the H8S/2194 C Group. Clock synchroniz ation/startstop sync SCI Timer J 0 ADR2 AHR2 SCH0 Module Name A/D RST/NMI CKS2 Rev.3.00 Jan. 10, 2007 page 910 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFEE H'FFF0 H'FFF1 H'FFF2 PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PMR0 PMR1 PMR2 PMR3 PCR1 PCR2 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PMR4 PMR5 PMR6 PMR7 PMR8 PUR1 PUR2 PUR3 RTPEGR RTPSR SYSCR MDCR SBYCR LPWRCR R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bus Access Width 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PDR07 PDR17 PDR27 PDR37 PDR47 PDR67 PDR77 PDR87 PMR07 PMR17 PMR27 PMR37 PCR17 PCR27 PCR37 PCR47 PCR67 PCR77 PCR87 PMR67 PMR77 PUR17 PUR27 PUR37 RTPSR7 SSBY DTON MSTP15 MSTP7 6 PDR06 PDR16 PDR26 PDR36 PDR46 PDR66 PDR76 PDR86 PMR06 PMR16 PMR26 PMR36 PCR16 PCR26 PCR36 PCR46 PCR66 PCR76 PCR86 PMR66 PMR76 PUR16 PUR26 PUR36 RTPSR6 STS2 LSON MSTP14 MSTP6 IICX IRQ5EG 5 PDR05 PDR15 PDR25 PDR35 PDR45 PDR65 PDR75 PDR85 PMR05 PMR15 PMR25 PMR35 PCR15 PCR25 PCR35 PCR45 PCR65 PCR75 PCR85 PMR65 PMR75 PUR15 PUR25 PUR35 RTPSR5 INTM1 STS1 NESEL MSTP13 MSTP5 IICRST IRQ4EG IRQ5E IRQ5F 4 PDR04 PDR14 PDR24 PDR34 PDR44 PDR64 PDR74 PDR84 PMR04 PMR14 PMR34 PCR14 PCR24 PCR34 PCR44 PCR64 PCR74 PCR84 PMR64 PMR74 PUR14 PUR24 PUR34 RTPSR4 INTM0 STS0 MSTP12 MSTP4 IRQ3EG IRQ4E IRQ4F 3 PDR03 PDR13 PDR23 PDR33 PDR43 PDR53 PDR63 PDR73 PDR83 PMR03 PMR13 PMR33 PCR13 PCR23 PCR33 PCR43 PCR53 PCR63 PCR73 PCR83 PMR53 PMR63 PMR73 PMR83 PUR13 PUR23 PUR33 RTPSR3 XRST MSTP11 MSTP3 FLASHE IRQ2EG IRQ3E IRQ3F 2 PDR02 PDR12 PDR22 PDR32 PDR42 PDR52 PDR62 PDR72 PDR82 PMR02 PMR12 PMR32 PCR12 PCR22 PCR32 PCR42 PCR52 PCR62 PCR72 PCR82 PMR52 PMR62 PMR72 PMR82 PUR12 PUR22 PUR32 RTPSR2 NMIEG1 MSTP10 MSTP2 IRQ1EG IRQ2E IRQ2F 1 PDR01 PDR11 PDR21 PDR31 PDR41 PDR51 PDR61 PDR71 PDR81 PMR01 PMR11 PMR31 PCR11 PCR21 PCR31 PCR41 PCR51 PCR61 PCR71 PCR81 PMR51 PMR61 PMR71 PMR81 PUR11 PUR21 PUR31 0 PDR00 PDR10 PDR20 PDR30 PDR40 PDR50 PDR60 PDR70 PDR80 PMR00 PMR10 PMR20 PMR30 PCR10 PCR20 PCR30 PCR40 PCR50 PCR60 PCR70 PCR380 PMR40 PMR50 PMR60 PMR70 PMR80 PUR10 PUR20 PUR30 Port pull-up select register Port mode register Port mode register Port control register Port mode register Module Name Port data register RTPEGR1 RTPEGR0 RTP TRG select RTPSR1 RTPSR0 NMIEG0 SCK1 SA1 MSTP9 MSTP1 MDS0 SCK0 SA0 MSTP8 MSTP0 System control register MSTPCRH R/W MSTPCRL R/W STCR IEGR IENR IRQR R/W R/W R/W R/W IRQ0EG1 IRQ0EG0 IRQ edge IRQ1E IRQ1F IRQ0E IRQ0F IRQ enable IRQ status Rev.3.00 Jan. 10, 2007 page 911 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers Register Address* Name H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFF8 H'FFF9 F'FFFA F'FFFB ICRA ICRB ICRC ICRD FLMCR1 FLMCR2 EBR1 EBR2 FLMCR1 FLMCR2 EBR1 EBR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bus Access Width 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ICRA7 ICRB7 ICRC7 ICRD7 FWE FLER EB7 FWE FLER EB7 6 ICRA6 ICRB6 ICRC6 ICRD6 SWE EB6 SWE EB6 5 ICRA5 ICRB5 ICRC5 ICRD5 EB5 ESU1 ESU2 EB13 EB5 4 ICRA4 ICRB4 ICRC4 ICRD4 EB4 PSU1 PSU2 EB12 EB4 3 ICRA3 ICRB3 ICRC3 ICRD3 EV EB3 EV1 EV2 EB11 EB3 2 ICRA2 ICRB2 ICRC2 ICRD2 PV EB2 PV1 PV2 EB10 EB2 1 ICRA1 ICRB1 ICRC1 ICRD1 E ESU EB9 EB1 E1 E2 EB9 EB1 0 ICRA0 ICRB0 ICRC0 ICRD0 P PSU EB8 EB0 P1 P2 EB8 EB0 Only for FLASH version in the H8S/2194 C Only for FLASH version. Module Name IRQ priority control Note: * Lower 16 bits of the address. Rev.3.00 Jan. 10, 2007 page 912 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers B.2 Function List DGKp: Drum Digital Filter DGKp: Drum Digital Filter DGKs: Drum Digital Filter DGKs: Drum Digital Filter 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H'D000: Gain Constant H'D001: Gain Constant H'D002: Gain Constant H'D003: Gain Constant Bit : Initial value : R/W : 15 14 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined H'D004: Coefficient H'D005: Coefficient H'D006: Coefficient H'D007: Coefficient H'D008: Coefficient H'D009: Coefficient H'D00A: Coefficient H'D00B: Coefficient Bit : Initial value : R/W : 15 DAp: Drum Digital Filter DAp: Drum Digital Filter DBp: Drum Digital Filter DBp: Drum Digital Filter DAs: Drum Digital Filter DAs: Drum Digital Filter DBs: Drum Digital Filter DBs: Drum Digital Filter 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined Rev.3.00 Jan. 10, 2007 page 913 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D00C: Offset H'D00D: Offset H'D00E: Offset H'D00F: Offset Bit : Initial value : R/W : 15 DOfp: Drum Digital Filter DOfp: Drum Digital Filter DOfs: Drum Digital Filter DOfs: Drum Digital Filter 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined H'D010: Gain Constant H'D011: Gain Constant H'D012: Gain Constant H'D013: Gain Constant Bit : Initial value : R/W : 15 14 CGKp: Capstan Digital Filter CGKp: Capstan Digital Filter CGKs: Capstan Digital Filter CGKs: Capstan Digital Filter 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined Rev.3.00 Jan. 10, 2007 page 914 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D014: Coefficient CAp: Capstan Digital Filter H'D015: Coefficient CAp: Capstan Digital Filter H'D016: Coefficient CBp: Capstan Digital Filter H'D017: Coefficient CBp: Capstan Digital Filter H'D018: Coefficient CAs: Capstan Digital Filter H'D019: Coefficient CAs: Capstan Digital Filter H'D01A: Coefficient CBs: Capstan Digital Filter H'D01B: Coefficient CBs: Capstan Digital Filter Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined H'D01C: Offset H'D01D: Offset H'D01E: Offset H'D01F: Offset Bit : Initial value : R/W : 15 COfp: Capstan Digital Filter COfp: Capstan Digital Filter COfs: Capstan Digital Filter COfs: Capstan Digital Filter 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined Rev.3.00 Jan. 10, 2007 page 915 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D020: Delay Initialization Register DZs: Digital filter H'D021: Delay Initialization Register DZs: Digital filter H'D022: Delay Initialization Register DZp: Digital filter H'D023: Delay Initialization Register DZp: Digital filter H'D024: Delay Initialization Register CZs: Digital filter H'D025: Delay Initialization Register CZs: Digital filter H'D026: Delay Initialization Register CZp: Digital filter H'D027: Delay Initialization Register CZp: Digital filter Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev.3.00 Jan. 10, 2007 page 916 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter Bit : Initial value : R/W : 7 1 6 DROV 0 R/(W)* 5 DPHA 0 R/(W) 4 DZPON 0 R/W 3 DZSON 0 R/W 2 DSG2 0 R/W 1 DSG1 0 R/W 0 DSG0 0 R/W Drum system gain control bit DSG2 0 DSG1 DSG0 Description 0 0 x1 1 x2 1 0 x4 1 x8 0 0 x16 1 (x32)* 1 0 (x64)* 1 Invalid (do not set) 1 Note: * Optional Drum speed system Z-1 initialization bit 0 1 Speed system Z-1 reflects DZs value. Speed system Z-1 does not relect DZs value. Drum phase system Z-1 initialization bit 0 1 Phase system Z-1 reflects DZp value. Phase system Z-1 does not relect DZp value. Drum phase system filter computation start bit 0 1 Phase system filter computation is OFF. Phase system computation result Y is not added to Es. Phase system filter computation is ON. Drum system range over flag 0 1 Filter computation result does not exceed 12 bits. Filter computation result exceeds 12 bits. Note: * Only 0 can be written. Rev.3.00 Jan. 10, 2007 page 917 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D029: Capstan System Digital Filter Control Register CFIC: Digital Filter Bit : Initial value : R/W : 7 1 6 CROV 0 R/(W)* 5 CPHA 0 R/(W) 4 CZPON 0 R/W 3 CZSON 0 R/W 2 CSG2 0 R/W 1 CSG1 0 R/W 0 CSG0 0 R/W Capstan system gain control bit CSG1 CSG0 Description 0 0 x1 1 x2 1 0 x4 1 x8 1 0 0 x16 1 (x32)* 1 0 (x64)* 1 Invalid (do not set) Note: * Setting optional Capstan speed system Z-1 initialization bit 0 1 Speed system Z-1 reflects CZs value. Speed system Z-1 does not relect CZs value. CSG2 0 Capstan phase system Z-1 initialization bit 0 1 Phase system Z-1 reflects CZp value. Phase system Z-1 does not relect CZp value. Capstan phase system filter computation start bit 0 1 Phase system filter computation is OFF. Phase system computation result Y is not added to Es. Phase system filter computation is ON. Capstan system range over flag 0 1 Filter computation result does not exceed 12 bits. Filter computation result exceeds 12 bits. Note: * Only 0 can be written. Rev.3.00 Jan. 10, 2007 page 918 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D02A: Digital Filter Control Register Bit : Initial value : R/W : 7 1 6 1 5 PTON 0 R/W 4 CP/DP 0 R/W DFUCR: Digital Filter 3 CFEPS 0 R/W 2 DFEPS 0 R/W 1 CFESS 0 R/W 0 DFESS 0 R/W Drum speed system error data transfer bit 0 Transfer data by NCDFG signal latch. 1 Transfer data at the time of error data write. Capstan speed system error data transfer bit 0 Transfer data by DVCFG signal latch. 1 Transfer data at the time of error data write. Drum phase system error data transfer bit 0 Transfer data by HSW (NHSW) signal latch. 1 Transfer data at the time of error data write. Capstan phase system error data transfer bit 0 Transfer data by DVCFG2 signal latch. 1 Transfer data at the time of error data write. PWM output select bit 0 Output drum phase system computation result (CAPPWM) 1 Output capstan phase system computation result (DRMPWM) Phase system computation result PWM output bit 0 Output normal filter computation result to PWM pin. 1 Output only phase system computation result to PWM pin. H'D030: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector H'D031: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev.3.00 Jan. 10, 2007 page 919 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D032: DFG Speed Error Data Register DFER: Drum Error Detector H'D033: DFG Speed Error Data Register DFER: Drum Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. H'D034: DFG Lock Upper Data Register H'D035: DFG Lock Upper Data Register Bit : Initial value : R/W : 15 14 13 12 11 10 9 DFRUDR: Drum Error Detector DFRUDR: Drum Error Detector 8 7 6 5 4 3 2 1 0 0 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W H'D036: DFG Lock Lower Data Register DFRLDR: Drum Error Detector H'D037: DFG Lock Lower Data Register DFRLDR: Drum Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev.3.00 Jan. 10, 2007 page 920 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D038: Drum Speed Error Detection Control Register DFVCR: Drum Error Detector Bit : Initial value : R/W : 7 DFCS1 0 R/W 6 DFCS0 0 R/W 5 DFOVF 0 R/(W)*1 4 3 DFRFON DF-R/UNR 0 R/W 0 R 2 DPCNT 0 R/W 1 DFRCS1 0 (R)/W*2 0 DFRCS0 0 (R)/W*2 Drum lock counter setting bit DFRCS1 DFRCS0 Description 0 0 Underflow by 1 lock detection 1 Underflow by 2 lock detections 1 0 Underflow by 3 lock detections 1 Underflow by 4 lock detections Drum phase system filter computation auto start bit 0 1 Drum lock flag 0 1 Drum speed system is not locked. Drum speed system is locked. Filter computation by drum lock detection is not excuted. Filter computation of phase system is executed at the time of drum lock detection. Error data limit function select bit 0 1 Limit function OFF Limit function ON Counter overflow flag 0 1 Clock source select bit DFCS1 DFCS0 Description 0 0 s 1 s/2 1 0 s/4 1 s/8 Normal status Counter overflows. Notes: 1. Only 0 can be written. 2. When read, counter value is read. Rev.3.00 Jan. 10, 2007 page 921 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D039: Drum Phase Error Detection Control Register DPGCR: Drum Error Detector Bit : Initial value : R/W : 7 DPCS1 0 R/W 6 DPCS0 0 R/W 5 DPOVF 0 R/(W)* 4 N/V 0 R/W 3 HSWES 0 R/W Edge select bit 0 1 Latch at rising edge Latch at falling edge 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Error data latch signal select bit 0 1 HSW (VideoFF) signal NHSW (NarrowFF) signal Counter overflow flag 0 1 Clock source select bit DPCS1 DPCS0 Description 0 0 s 1 s/2 1 0 s/3 1 s/4 Normal status Counter overflows. Note: * Only 0 can be written. H'D03A: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D03C: Specified Drum Phase Preset Data Register 1 DPPR1: Drum Error Detector Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 W 2 0 W 1 0 W 0 0 W Rev.3.00 Jan. 10, 2007 page 922 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D03D: Drum Phase Error Data Register 1 DPER1: Drum Error Detector Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R*/W 2 0 R*/W 1 0 R*/W 0 0 R*/W Note: * Note that only detected error data can be read. H'D03E: Drum Phase Error Data Register 2 DPER2: Drum Error Detector Bit : Initial value : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. H'D050: Specified CFG Speed Preset Data Register CFPR: Capstan Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D052: CFG Speed Error Data Register CFER: Capstan Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. H'D054: CFG Lock Upper Data Register CFRUDR: Capstan Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W 1 W Rev.3.00 Jan. 10, 2007 page 923 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D056: CFG Lock Lower Data Register CFRLDR: Capstan Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D058: Capstan Speed Error Detection Control Register CFVCR: Capstan Error Detector Bit : Initial value : R/W : 7 CFCS1 0 R/W 6 CFCS0 0 R/W 5 CFOVF 0 R/(W)*1 4 3 2 CFRFON CF-R/UNR CPCNT 0 R/W 0 R 0 R/W 1 CFRCS1 0 (R)/W*2 0 CFRCS0 0 (R)/W*2 Capstan lock counter setting bit CFRCS1 CFRCS0 Description 0 0 Underflow by 1 lock detection 1 Underflow by 2 lock detections 1 0 Underflow by 3 lock detections 1 Underflow by 4 lock detections Capstan phase system filter computation auto start bit 0 1 Capstan lock flag 0 1 Capstan speed system is not locked. Capstan speed system is locked. Filter computation by capstan lock detection is not excuted. Filter computation of phase system is executed at the time of drum lock detection. Error data limit function select bit 0 1 Limit function OFF Limit function ON Counter overflow flag 0 1 Clock source select bit CFCS1 CFCS0 Description 0 0 s 1 s/2 1 0 s/4 1 s/8 Normal status Counter overflows. Notes: 1. Only 0 can be written. 2. When read, counter value is read. Rev.3.00 Jan. 10, 2007 page 924 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D059: Capstan Phase Error Detection Control Register CPGCR: Capstan Error Detector Bit : Initial value : R/W : 7 CPCS1 0 R/W 6 CPCS0 0 R/W 5 CPOVF 0 R/(W)* 4 CR/RF 0 R/W 3 SELCFG2 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Preset, latch signal select bit 0 1 Preset by CAPREF30 signal and latch by DVCTL signal Preset by REF30P signal and latch by DVCFG2 signal Preset signal select bit 0 1 Preset by REF30P signal Preset by CRRF signal Counter overflow flag 0 1 Clock source select bit CPCS1 CPCS0 Description 0 0 s 1 s/2 1 0 s/4 1 s/8 Normal status Counter overflows. Note: * Only 0 can be written. H'D05A: Specified Capstan Phase Preset Data Register 2 CPPR2: Capstan Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D05C: Specified Capstan Phase Preset Data Register 1 CPPR1: Capstan Error Detector Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 W 2 0 W 1 0 W 0 0 W Rev.3.00 Jan. 10, 2007 page 925 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D05D: Capstan Phase Error Data Register 1 CPER1: Capstan Error Detector Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R*/W 2 0 R*/W 1 0 R*/W 0 0 R*/W Note: * Note that only detected error data can be read. H'D05E: Capstan Phase Error Data Register 2 CPER2: Capstan Error Detector Bit : Initial value : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. Rev.3.00 Jan. 10, 2007 page 926 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D060: HSW Mode Register 1 HSM1: HSW Timing Generator Bit : Initial value : R/W : 7 FLB 0 R 6 FLA 0 R 5 EMPB 1 R 4 EMPA 1 R 3 OVWB 0 R/(W)* 2 OVWA 0 R/(W)* 1 CLRB 0 R/W 0 CLRA 0 R/W FIFO1 pointer clear 0 1 Normal operation Clear FIFO1 pointer FIFO2 pointer clear 0 1 Normal operation Clear FIFO2 pointer FIFO1 overwrite flag 0 Normal operation 1 Data is written to FIFO1 while it is full. Write 0 to clear the flag. FIFO2 overwrite flag 0 Normal operation 1 Data is written to FIFO2 while it is full. Write 0 to clear the flag. FIFO1 empty flag 0 1 FIFO2 empty flag 0 1 FIFO1 full flag 0 1 FIFO2 full flag 0 1 FIFO2 is not full FIFO2 is full FIFO1 is not full FIFO1 is full Data remains in FIFO2 FIFO2 is empty Data remains in FIFO1 FIFO1 is empty Note: * Only 0 can be written. Rev.3.00 Jan. 10, 2007 page 927 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D061: HSW Mode Register 2 HSM2: HSW Timing Generator Bit : Initial value : R/W : 7 FRT 0 R/W 6 FGR20FF 0 R/W 5 LOP 0 R/W 4 EDG 0 R/W 3 ISEL1 0 R/W 2 SOFG 0 R/W 1 OFG 0 R 0 VFF/NFF 0 R/W VideoFF/NarrowFF output switchover bit 0 1 VideoFF output NarrowFF output Output FIFO group flag 0 1 Outputting pattern by FIFO1 Outputting pattern by FIFO2 FIFO output group select bit 0 1 20-level output by FIFO1 and FIFO2 10-level output by FIFO1 only Interrupt select bit 0 1 Interrupt request is generated by rising of FIFO STRIG signal Interrupt request is generated by FIFO match signal DFG edge select bit 0 1 Mode select bit 0 1 Signal mode Loop mode Calculated by DFG rising edge Calculated by DFG falling edge FRG2 clear stop bit 0 1 Free-run bit 0 1 5-bit DFG counter and 16-bit timer 16-bit FRC 16-bit counter clear by DFG reference register 2 is enabled 16-bit counter clear by DFG reference register 2 is disabled Rev.3.00 Jan. 10, 2007 page 928 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D062: HSW Loop Stage Setting Register HSLP: HSW Timing Generator Bit : 7 LOB3 Initial value : R/W : * R/W 6 LOB2 * R/W 5 LOB1 * R/W 4 LOB0 * R/W 3 LOA3 * R/W 2 LOA2 * R/W 1 LOA1 * R/W 0 LOA0 * R/W FIFO1 stage setting bit HSM2 Bit 5 LOP 0 1 Bit 3 LOA3 * 0 HSLP Bit 2 Bit 1 LOA2 LOA1 * * 0 0 1 1 0 1 1 0 0 1 1 0 1 Legend: * Don't care. FIFO2 stage setting bit HSM2 Bit 5 LOP 0 1 Bit 7 LOB3 * 0 HSLP Bit 6 Bit 5 LOB2 LOB1 * * 0 0 1 1 0 1 1 0 0 1 1 0 1 Legend: * Don't care. Description Bit 4 LOB0 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Bit 0 LOA0 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single mode Output stage 0 of FIFO1 Output stage 0 and 1 of FIFO1 Output stage 0 to 2 of FIFO1 Output stage 0 to 3 of FIFO1 Output stage 0 to 4 of FIFO1 Output stage 0 to 5 of FIFO1 Output stage 0 to 6 of FIFO1 Output stage 0 to 7 of FIFO1 Output stage 0 to 8 of FIFO1 Output stage 0 to 9 of FIFO1 Setting disabled Single mode Output stage 0 of FIFO2 Output stage 0 and 1 of FIFO2 Output stage 0 to 2 of FIFO2 Output stage 0 to 3 of FIFO2 Output stage 0 to 4 of FIFO2 Output stage 0 to 5 of FIFO2 Output stage 0 to 6 of FIFO2 Output stage 0 to 7 of FIFO2 Output stage 0 to 8 of FIFO2 Output stage 0 to 9 of FIFO2 Setting disabled Rev.3.00 Jan. 10, 2007 page 929 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D064: FIFO Output Pattern Register 1 FPDRA: HSW Timing Generator Bit : Initial value : R/W : Bit : Initial value : R/W : 15 -- 1 -- 7 PPGA7 * W 14 ADTRGA * W 6 PPGA6 * W 13 12 STRIGA NarrowFFA * W 5 PPGA5 * W * W 4 PPGA4 * W 11 VFFA * W 3 PPGA3 * W 10 AFFA * W 2 PPGA2 * W 9 VpulseA * W 1 PPGA1 * W 8 MlevelA * W 0 PPGA0 * W Legend: * Undetermined H'D066: FIFO Timing Pattern Register 1 FTPRA: HSW Timing Generator Bit : 15 14 13 12 11 10 9 8 FTPRA8 7 FTPRA7 6 FTPRA6 5 FTPRA5 4 FTPRA4 3 FTPRA3 2 FTPRA2 1 FTPRA1 0 FTPRA0 FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9 Initial value : R/W : * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Legend: * Undetermined H'D066: FIFO Timer Capture Register 1 FTCTR: HSW Timing Generator Bit : 15 14 13 12 11 10 9 8 FTCTR8 7 FTCTR7 6 FTCTR6 5 FTCTR5 4 FTCTR4 3 FTCTR3 2 FTCTR2 1 FTCTR1 0 FTCTR0 FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 Initial value : R/W : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R H'D068: FIFO Output Pattern Register 2 FPDRB: HSW Timing Generator Bit : Initial value : R/W : Bit : Initial value : R/W : 15 -- 1 -- 7 PPGB7 * W 14 ADTRGB * W 6 PPGB6 * W 13 12 STRIGB NarrowFFB * W 5 PPGB5 * W * W 4 PPGB4 * W 11 VFFB * W 3 PPGB3 * W 10 AFFB * W 2 PPGB2 * W 9 VpulseB * W 1 PPGB1 * W 8 MlevelB * W 0 PPGB0 * W Note: * Undetermined Rev.3.00 Jan. 10, 2007 page 930 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D06A: FIFO Timing Pattern Register 2 FTPRB: HSW Timing Generator Bit : 15 14 13 12 11 10 9 8 FTPRB8 7 FTPRB7 6 FTPRB6 5 FTPRB5 4 FTPRB4 3 FTPRB3 2 FTPRB2 1 FTPRB1 0 FTPRB0 FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 Initial value : R/W : * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W * W Note: * Undetermined H'D06C: DFG Reference Register 1 DFCRA: HSW Timing Generator Bit : Initial value : R/W : 7 ISEL2 0 W 6 CCLR 0 W 5 CKSL 0 W 4 DFCRA4 * W 3 DFCRA3 * W 2 DFCRA2 * W 1 DFCRA1 * W 0 DFCRA0 * W 16-bit counter clock source select bit 0 1 s/4 s/8 DFG counter clear bit 0 Normal operation 1 Clear 5-bit DFG counter Interrupt select bit 0 Interrupt request is generated by clear signal of 16-bit timer counter 1 Interrupt request is generated by VD signal in PB mode H'D06C: DFG Reference Count Register DFCTR: HSW Timing Generator Bit : Initial value : R/W : 7 -- 6 -- 5 -- 4 DFCTR4 0 R 3 DFCTR3 0 R 2 DFCTR2 0 R 1 DFCTR1 0 R 0 DFCTR0 0 R 1 -- 1 -- 1 -- H'D06D: DFG Reference Register 2 DFCRB: HSW Timing Generator Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 DFCRB4 * W 3 DFCRB3 * W 2 1 DFCRB2 DFCRB1 * W * W 0 DFCRB0 * W Note: * Undetermined Rev.3.00 Jan. 10, 2007 page 931 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D06E: Special Effect Playback Control Register CHCR: 4-head Special Effect Playback Circuit Bit : Initial value : R/W : 7 V/N 0 W 6 HSWPOL 0 W 5 CRH 0 W 4 HAH 0 W 3 SIG3 0 W Signal control bits SIG3 0 SIG2 0 1 SIG1 * 0 1 1 0 1 Note: * Don't care. H.AmpSW synchronization control bit 0 Synchronous 1 Asynchronous C.Rotary synchronization control bit 0 Synchronous 1 Asynchronous COMP polarity select bit 0 Positive 1 Negative HSW output signal select bit 0 VideoFF signal output 1 Narrow FF signal output 0 1 0 1 SIG0 * 0 1 0 1 * Output pin C.Rotary H.Amp SW L L HSW L HSW H L HSW H HSW HSW EX-OR COMP COMP HSW EX-NOR COMP COMP HSW EX-OR RTP0 RTP0 HSW EX-NOR RTP0 RTP0 2 SIG2 0 W 1 SIG1 0 W 0 SIG0 0 W Rev.3.00 Jan. 10, 2007 page 932 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D06F: Additional V Control Register ADDVR: Additional V Signal Generator Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 HMSK 0 R/W 3 Hi-Z 0 R/W 2 CUT 0 R/W 1 VPON 0 R/W 0 POL 0 R/W Additional V output control bits CUT VPON POL Description 0 0 * Low level 1 0 Negative polarity (Figure 28.46) 1 Positive polarity (Figure 28.45) 1 * 0 Immediate level (high-impedance when Hi-Z bit = 1) 1 High level Legend: * Don't care. High impedance bit 0 3-level output from Vpulse pin 1 Vpulse pin is set as 3-state (H/L/Hi-Z) pin OSCH mask bit 0 OSCH added 1 OSCH not added H'D070: X-Value Data Register XDR: X-Value, TRK-Value Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D072: TRK-Value Data Register TRDR: X-Value, TRK-Value Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 TRD11 TRD10 TRD9 TRD8 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev.3.00 Jan. 10, 2007 page 933 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D074: X-Value/TRK-Value Control Register XTCR: X-Value, TRK-Value Adjustment Circuit Bit : Initial value : R/W : 7 -- 1 -- 6 CAPRF 0 W 5 AT/MU 0 W 4 TRK/X 0 W 3 EXC/REF 0 W 2 XCS 0 W 1 DVREF1 0 R/W 0 DVREF0 0 R/W REF30P frequency division rate select bit DVREF1 DVREF0 Description 0 0 1-division 1 2-division 1 0 3-division 1 4-division Clock source select bit 0 s 1 s/2 Reference signal select bit 0 Generated by REF30P signal 1 Generated by external referece signal Capstan phase adjustment register select bit 0 CAPREF30 is generated only by XDR setting value 1 CAPREF30 is generated by XDR and TRDR setting values Capstan phase adjustment auto/manual select bit 0 1 Manual mode Auto mode External sync signal edge select bit 0 Generated at EXCAP rising edge 1 Generated at EXCAP rising and falling edge H'D078: Drum 12-Bit PWM Data Register DPWDR: Drum 12-Bit PWM Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- Initial value : R/W : 1 -- 1 -- 1 -- 1 DPWDR11 DPWDR10 DPWDR9 DPWDR8 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W -- -- -- -- Rev.3.00 Jan. 10, 2007 page 934 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D07A: Drum 12-Bit PWM Control Registor DPWCR: Drum 12-Bit PWM Bit : Initial value : R/W : 7 DPOL 0 W 6 DDC 1 W 5 DHiZ 0 W 4 DH/L 0 W 3 DSF/DF 0 W 2 DCK2 0 W 1 DCK1 1 W 0 DCK0 0 W Carrier frequency select bits CK2 0 CK1 0 1 1 0 1 CK0 0 1 0 1 0 1 0 1 Output data select bit 0 1 Modulate error data from digital filter circuit Modulate data written in data register Carrier frequency select bits /2 /4 /8 /16 /32 /64 /128 (Do not set) Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by PWMs and output from the CAPPWM and DRMPWM pins. However, it is possible to output only drum phase filter results from CAPPWM pin and only capstan phase filter result from DRMPWM pin, by DFUCR settings of the digital filter circuit. See the section explaining the digital filter computation circuit. Fixed output bit, PWM pin output bit DC 1 Hi-Z 0 1 0 * Legend: * Don't care. H/L 0 1 * * Fixed output bit, PWM pin output bit Low level output from PWM pin High level output form PWM pin High impedance from PWM pin PWM modulated signal output Polarity switchover bit 0 1 Positive polarity Negative polarity output H'D07B: Capstan 12-Bit PWM Control Register CPWCR: Capstan 12-Bit PWM Bit : Initial value : R/W : 7 CPOL 0 W 6 CDC 1 W 5 CHiZ 0 W 4 CH/L 0 W 3 CSF/DF 0 W 2 CCK2 0 W 1 CCK1 1 W 0 CCK0 0 W Rev.3.00 Jan. 10, 2007 page 935 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D07C: Capstan 12-Bit PWM Data Register CPWDR: Capstan 12-Bit PWM Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- Initial value : R/W : 1 -- 1 -- 1 -- 1 CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W -- -- -- -- H'D080: CTL Control Register CTCR: CTL Circuit Bit : 7 NT/PL Initial value : R/W : 0 W 6 FSLC 0 W 5 FSLB 1 W 4 FSLA 1 W 3 CCS 0 W 2 LCTL 0 W 1 UNCTL 0 R 0 SLWM 0 W Mode select bit 0 Normal mode 1 Slow mode CTL undetected bit 0 Detected 1 Undetected Long CTL bit 0 Clock source (CCS) operates at the setting value 1 Clock source (CCS) operates for further 8-division after operating at the setting value Clock source select bit 0 s 1 s/2 Operating frequency select bits FSLC FSLB FSLA Description 0 0 0 Reserved (do not set) 1 Reserved (do not set) 1 0 fosc = 8 MHz 1 fosc = 10 MHz (Initial value) 1 * * Reserved (do not set) Legend: * Don't care. NTSC/PAL select bit 0 NTSC mode (frame rate: 30 Hz) 1 PAL mode (frame rate: 25 Hz) Rev.3.00 Jan. 10, 2007 page 936 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D081: CTL Mode Register CTLM: CTL Circuit Bit : 7 ASM Initial value : R/W : 0 R/W 6 REC/PB 0 R/W 5 FW/RV 0 R/W 4 MD4 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W CTL mode select bits Direction bit 0 FORWARD 1 REVERSE Record/playback mode bits ASM REC/PB Description 0 0 Playback mode (PLAYBACK) 1 Record mode (RECORD) 1 0 Assemble mode 1 Invalid (do not set) H'D082: REC-CTL Duty Data Register 1 RCDR1: CTL Circuit Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D084: REC-CTL Duty Data Register 2 RCDR2: CTL Circuit Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev.3.00 Jan. 10, 2007 page 937 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D086: REC-CTL Duty Data Register 3 RCDR3: CTL Circuit Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D088: REC-CTL Duty Data Register 4 RCDR4: CTL Circuit Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D08A: REC-CTL Duty Data Register 5 RCDR5: CTL Circuit Bit : Initial value : R/W : 15 -- 1 -- 14 -- 1 -- 13 -- 1 -- 12 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev.3.00 Jan. 10, 2007 page 938 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D08C: Duty I/O Register DI/O: CTL Circuit Bit : Initial value : R/W : 7 VCTR2 1 W 6 VCTR1 1 W 5 VCTR0 1 W 4 -- 1 -- 3 BPON 0 W 2 BPS 0 W 1 BPF 0 R/(W)* 0 DI/O 1 R/W Duty I/O register Bit pattern detection flag 0 Bit pattern (8-bit) is not detected 1 Bit pattern (8-bit) is detected Bit pattern detection start bit 0 Normal status 1 Starts 8-bit bit pattern detection Bit pattern detection ON/OFF bit 0 Bit pattern detection OFF 1 Bit pattern detection ON VISS interrupt setting bits VCTR2 VCTR1 VCTR0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Number of 1-pulse for detection 2 4 (SYNC mark) 6 8 (mark A, short) 12 (mark A, long) 16 24 (mark B) 32 Note: * Only 0 can be written. H'D08D: Bit Pattern Register BTPR: CTL Circuit Bit : Initial value : R/W : 7 LSP7 1 R*/W 6 LSP6 1 R*/W 5 LSP5 1 R*/W 4 LSP4 1 R*/W 3 LSP3 1 R*/W 2 LSP2 1 R*/W 1 LSP1 1 R*/W 0 LSP0 1 R*/W Note: * Writes are disabled during bit pattern detection. Rev.3.00 Jan. 10, 2007 page 939 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D090: Reference Frequency Register 1 RFD: Reference Signal Generator Bit : Initial value : R/W : 15 1 W 14 1 W 13 1 W 12 1 W 11 1 W 10 1 W 9 1 W 8 1 W 7 1 W 6 1 W 5 1 W 4 1 W 3 1 W 2 1 W 1 1 W 0 1 W REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 H'D092: Reference Frequency Register 2 CRF: Reference Signal Generator Bit : Initial value : R/W : 15 1 W 14 1 W 13 1 W 12 1 W 11 1 W 10 1 W 9 1 W 8 1 W 7 1 W 6 1 W 5 1 W 4 1 W 3 1 W 2 1 W 1 1 W 0 1 W CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0 H'D094: REF30 Counter Register RFC: Reference Signal Generator Bit : Initial value : R/W : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.3.00 Jan. 10, 2007 page 940 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator Bit : Initial value : R/W : 7 RCS 0 W 6 VNA 0 W 5 CVS 0 W 4 REX 0 W 3 CRD 0 W 2 OD/EV 0 W 1 VST 0 W 0 VEG 0 W VideoFF edge select bit 0 Set at VideoFF signal rising 1 Set at VideoFF signal falling VideoFF counter set 0 VideoFF signal turns counter set OFF 1 VideoFF signal turns counter set ON ODD/EVEN edge switchoverselect bit 0 Generated at field signal rising (EVEN) 1 Generated at field signal rising (ODD) DVCFG2 synchronization select bit 0 At mode switching 1 DVCFG2 signal synchronized External signal synchronization select bit 0 VD signal or free-run 1 External signal sync Manual select bit 0 VD sync 1 Free-run Mode select bit 0 Manual mode 1 Auto mode Clock source select bit 0 s/2 1 s/4 Rev.3.00 Jan. 10, 2007 page 941 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D097: Reference Frequency Mode Register 2 RFM2: Reference Signal Generator Bit : Initial value : R/W : 7 (TBC)* 1 (R/W)* 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 FDS 0 R/W TBC select bit 0 Reference signal is generated with VD 1 Reference signal is generated in free-run Note: * The TBC bit is readable/writable only in the H8S/2194C Group. This bit cannot be modified in the H8S/2194 Group, and the reference signal is therefore generated in free-run. Field select bit 0 Generated by selected ODD or EVEN VD signal 1 Generated by VD signal immediately after mode transition H'D098: DVCTL Control Register CTVC: Frequency Divider Bit : Initial value : R/W : 7 CEX 0 W 6 CEG 0 W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 CFG * R 1 HSW * R 0 CTL * R CTL flag 0 REC or PB-CTL level is low 1 REC or PB-CTL level is high HSW flag 0 HSW level is low 1 HSW level is high CFG flag 0 CFG level is low 1 CFG level is high External sync signal edge select bit 0 Rising edge 1 Falling edge DVCTL signal generation select bit 0 Generated by PB-CTL signal 1 Generated by external input signal Note: * Undetermined Rev.3.00 Jan. 10, 2007 page 942 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D099: CTL Frequency Division Register CTLR: Frequency Divider Bit : Initial value : R/W : 7 CTL7 0 W 6 CTL6 0 W 5 CTL5 0 W 4 CTL4 0 W 3 CTL3 0 W 2 CTL2 0 W 1 CTL1 0 W 0 CTL0 0 W H'D09A: DVCFG Control Register CDVC: Frequency Divider Bit : Initial value : R/W : 7 MCGin 0 R/W* 6 -- 1 -- 5 CMK 1 R 4 CMN 0 W 3 DVTRG 0 W 2 CRF 0 W 1 CPS1 0 W 0 CPS0 0 W CFG mask timer clock select bit CPS1 0 1 CPS0 0 1 0 1 Description s/1024 s/512 s/256 s/128 CFG frequency division edge select bit 0 Execute frequency division operation at CFG rising edge 1 Execute frequency division operation at CFG rising and falling edges PB (ASM)-to-REC transition timing sync ON/OFF select bit 0 PB (ASM)-to-REC transition timing sync ON 1 PB (ASM)-to-REC transition timing sync OFF CFG mask select bit 0 Capstan mask timing function ON 1 Capstan mask timing function OFF CFG mask status bit 0 Mask is released by capstan mask timer 1 Mask is set by capstan mask timer Mask CFG flag 0 CFG normal operation 1 DVCFG is detected while mask is set (race detection) Note: * Only 0 can be written Rev.3.00 Jan. 10, 2007 page 943 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D09B: CFG Frequency Division Register 1 CDIVR1: Frequency Divider Bit : Initial value : R/W : 7 -- 1 -- 6 CDV16 0 W 5 CDV15 0 W 4 CDV14 0 W 3 CDV13 0 W 2 CDV12 0 W 1 CDV11 0 W 0 CDV10 0 W H'D09C: CFG Frequency Division Register 2 CDIVR2: Frequency Divider Bit : Initial value : R/W : 7 -- 1 -- 6 CDV26 0 W 5 CDV25 0 W 4 CDV24 0 W 3 CDV23 0 W 2 CDV22 0 W 1 CDV21 0 W 0 CDV20 0 W H'D09D: DVCFG Mask Interval Register CTMR: Frequency Divider Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 CPM5 1 W 4 CPM4 1 W 3 CPM3 1 W 2 CPM2 1 W 1 CPM1 1 W 0 CPM0 1 W H'D09E: FG Control Register FGCR: Frequency Divider Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 DRF 0 W DFG edge select bit 0 NCDFG signal rising edge is selected 1 NCDFG signal falling edge is selected Rev.3.00 Jan. 10, 2007 page 944 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0A0: Servo Port Mode Register SPMR: Servo Port Bit : Initial value : R/W : 7 CTLSTOP 0 R/W 6 -- 1 -- 5 4 3 CFGCOMP EXCTLON DPGSW 0 R/W 0 R/W 0 R/W 2 COMP 0 R/W 1 H.Amp.SW 0 R/W 0 C.Rot 0 R/W C.Rotary pin function switch bit 0 C.Rotary/PS0 pin functions as C.Rotary output pin 1 C.Rotary/PS0 pin functions as PS0 I/O pin H.AmpSW pin function switch bit 0 H.AmpSW/PS1 pin functions as H.AmpSW output pin 1 H.AmpSW/PS1 pin functions as PS1 I/O pin COMP pin function switch bit 0 COMP/PS2 pin functions as COMP input pin 1 COMP/PS2 pin functions as PS2 I/O pin DPG pin functionswitch bit 0 Separate input for drum control system input (DPG/PS3 pin functions as DPG input pin) 1 Weight input for drum control system input (DPG/PS3 pin functions as PS3 I/O pin) EXCTL pin function switch bit 0 EXCTL/PS4 pin functions as EXCEL input pin 1 EXCTL/PS4 pin functions as PS4 I/O pin CFG input method switch bit 0 Zero cross type comparator method for CFG signal input 1 Digital signal input method for CFG signal input CTLSTOP bit 0 CTL circuit operates 1 CTL circuit does not operate H'D0A1: Servo Control Register SPCR: Servo Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SPCR4 0 W 3 SPCR3 0 W 2 SPCR2 0 W 1 SPCR1 0 W 0 SPCR0 0 W SPCRn Description 0 PSn pin functions as input pin 1 PSn pin functions as output pin Rev.3.00 Jan. 10, 2007 page 945 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0A2: Servo Data Register SPDR: Servo Port Controller Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SPDR4 0 R/W 3 SPDR3 0 R/W 2 SPDR2 0 R/W 1 SPDR1 0 R/W 0 SPDR0 0 R/W H'D0A3: Servo Monitor Control Register SVMCR: Servo Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 4 3 2 1 0 SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W SVMCR2 SVMCR1 SVMCR0 Description 0 0 0 REF30 signal is output from SV1 output pin 1 CAPREF30 signal is output from SV1 output pin 1 0 CREF signal is output from SV1 output pin 1 CTLMONI signal is output from SV1 output pin 1 0 0 DVCFG signal is output from SV1 output pin 1 CFG signal is output from SV1 output pin 1 0 DFG signal is output from SV1 output pin 1 DPG signal is output from SV1 output pin SVMCR5 SVMCR4 SVMCR3 Description 0 0 0 REF30 signal is output from SV2 output pin 1 CAPREF30 signal is output from SV2 output pin 1 0 CREF signal is output from SV2 output pin 1 CTLMONI signal is output from SV2 output pin 1 0 0 DVCFG signal is output from SV2 output pin 1 CFG signal is output from SV2 output pin 1 0 DFG signal is output from SV2 output pin 1 DPG signal is output from SV2 output pin Rev.3.00 Jan. 10, 2007 page 946 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0A4: CTL Gain Control Register CTLGR: Servo Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 CTLE/A 0 R/W 4 CTLFB 0 R/W 3 CTLGR3 0 R/W 2 CTLGR2 0 R/W 1 CTLGR1 0 R/W 0 CTLGR0 0 R/W CTL amp gain setting bit CTLGR3 CTLGR2 CTLGR1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 CTLGR0 CTL outpu gain 0 34.0 dB 1 36.5 dB 0 39.0 dB 1 41.5 dB 0 44.0 dB 1 46.5 dB 0 49.0 dB 1 51.5 dB 0 54.0 dB 1 56.5 dB 0 59.0 dB 1 61.5 dB 0 64.0 dB* 1 66.5 dB* 0 69.0 dB* 1 71.5 dB* Note: * With a setting of 64.0dB or more, the CTLAMP is in a very sensitive status. When configuring the set board, be concerned about countermeasure against noise around the control head signal input port. Also, thoroughly set the filter between the CTLAMP and CTLSMT. CTL amp feedback SW bit 0 CTLFB SW is OFF 1 CTLFB SW is ON CTL select bit 0 AMP output 1 EXCTL H'D0B0: Vertical Sync Signal Threshold Value Register VTR: Sync Detector (Servo) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 VTR5 0 W 4 VTR4 0 W 3 VTR3 0 W 2 VTR2 0 W 1 VTR1 0 W 0 VTR0 0 W Rev.3.00 Jan. 10, 2007 page 947 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0B1: Horizontal Sync Signal Threshold Value Register HTR: Sync Detector (Servo) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 HTR3 0 W 2 HTR2 0 W 1 HTR1 0 W 0 HTR0 0 W H'D0B2: H Pulse Adjustment Start Time Setting Register HRTR: Sync Detector (Servo) Bit : Initial value : R/W : 7 HRTR7 0 W 6 HRTR6 0 W 5 HRTR5 0 W 4 HRTR4 0 W 3 HRTR3 0 W 2 HRTR2 0 W 1 HRTR1 0 W 0 HRTR0 0 W H'D0B3: H Pulse Width Setting Register HPWR: Sync Detector (Servo) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 HPWR3 0 W 2 HPWR2 0 W 1 HPWR1 0 W 0 HPWR0 0 W H'D0B4: Noise Detection Window Setting Register NWR: Sync Detector (Servo) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 NWR5 0 W 4 NWR4 0 W 3 NWR3 0 W 2 NWR2 0 W 1 NWR1 0 W 0 NWR0 0 W H'D0B5: Noise Detection Register NDR: Sync Detector (Servo) Bit : Initial value : R/W : 7 NDR7 0 W 6 NDR6 0 W 5 NDR5 0 W 4 NDR4 0 W 3 NDR3 0 W 2 NDR2 0 W 1 NDR1 0 W 0 NDR0 0 W Rev.3.00 Jan. 10, 2007 page 948 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0B6: Sync Signal Control Register SYNCR: Sync Detector (Servo) Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NIS/VD 1 R/W 2 NOIS 0 R/(W)* 1 FLD 0 R 0 SYCT 0 R/W Sync signal polarity select bit SYCT 0 Description Polarity Positive 1 Negative Field detection flag 0 Odd field 1 Even field Noise detection flag 0 Noise count is less than four times of NDR setting value 1 Noise count is over four times of NDR setting value Interrupt select bit 0 Noise level interrupt 1 VD interrupt Note: * Only 0 can be written. Rev.3.00 Jan. 10, 2007 page 949 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt Bit : Initial value : R/W : 7 IEDRM3 0 R/W 6 IEDRM2 0 R/W 5 IEDRM1 0 R/W 4 IECAP3 0 R/W 3 IECAP2 0 R/W 2 IECAP1 0 R/W 1 IEHSW2 0 R/W 0 IEHSW1 0 R/W HSW timing generator (OVW, match, STRIG) interrupt enable bit 0 Interrupt request is disabled by IRRHSW1 1 Interrupt request is enabled by IRRHSW1 HSW timing generation (counter clear, capture) interrupt enable bit 0 Interrupt request is disabled by IRRHSW2 1 Interrupt request is enabled by IRRHSW2 Capstan speed error detection (OVF, latch) interrupt enable bit 0 Interrupt request is disabled by IRRCAP1 1 Interrupt request is enabled by IRRCAP1 Capstan speed error detection (lock detection) interrupt enable bit 0 Interrupt request is disabled by IRRCAP2 1 Interrupt request is enabled by IRRCAP2 Capstan phase error detection interrupt enable bit 0 Interrupt request is disabled by IRRCAP3 1 Interrupt request is enabled by IRRCAP3 Drum speed error detection (OVF, latch) interrupt enable bit 0 Interrupt request is disabled by IRRDRM1 1 Interrupt request is enabled by IRRDRM1 Drum speed error detection (lock detection) interrupt enable bit 0 Interrupt request is disabled by IRRDRM2 1 Interrupt request is enabled by IRRDRM2 Drum phase error detection interrupt enable bit 0 Interrupt request is disabled by IRRDRM3 1 Interrupt request is enabled by IRRDRM3 Rev.3.00 Jan. 10, 2007 page 950 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0B9: Servo Interrupt Enable Register 2 SIENR2: Servo Interrupt Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 IESNC 0 R/W 0 IECTL 0 R/W CTL interrupt enable bit 0 Interrupt request is disabled by IRRCTL 1 Interrupt request is enabled by IRRCTL Vertical sync signal interrupt enable bit 0 Interrupt (vertical sync signal interrupt) request is disabled by IRRSNC 1 Interrupt (vertical sync signal interrupt) request is enabled by IRRSNC Rev.3.00 Jan. 10, 2007 page 951 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0BA: Servo Interrupt Request Register 1 SIRQR1: Servo Interrupt Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* HSW timing generator (OVW, match, STRIG) interrupt request bit 0 HSW timing generator (OVM, match, STRIG) interrupt request is not generated 1 HSW timing generator (OVM, match, STRIG) interrupt request is generated HSW timing generator (counter clear, capture) interrupt request bit 0 HSW timing generator (counter clear, capture) interrupt request is not generated 0 HSW timing generator (counter clear, capture) interrupt request is generated Capstan speed error detector (OVF, latch) interrupt request bit 0 Capstan speed error detector (OVF, latch) interrupt request in not generated 1 Capstan speed error detector (OVF, latch) interrupt request in generated Capstan speed error detector (lock detection) intrerrupt request bit 0 Capstan speed error detector (lock detection) interrupt request is not generated 1 Capstan speed error detector (lock detection) interrupt request is generated Capstan phase error detector (OVF, latch) interrupt request bit 0 Capstan phase error detector (OVF, latch) interrupt request is not generated 1 Capstan phase error detector (OVF, latch) interrupt request is generated Drum speed error detector (OVF, latch) interrupt request bit 0 Drum speed error detector (OVF, latch) interrupt request is not generated 1 Drum speed error detector (OVF, latch) interrupt request is generated Drum speed error detector (lock detection) interrupt request bit 0 Drum speed error detector (lock detection) interrupt request is not generated 1 Drum speed error detector (lock detection) interrupt request is generated Drum phase error detector interrupt request bit 0 Drum phase error detector interrupt request is not generated 1 Drum phase error detector interrupt request is generated Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 952 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0BB: Servo Interrupt Request Register 2 SIRQR2: Servo Interrupt Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 IRRSNC 0 R/(W)* 0 IRRCTL 0 R/(W)* CTL interrupt request bit 0 CTL interrupt request is not generated 1 CTL interrupt request is generated Vertical sync signal interrupt request bit 0 Sync signal detector (VD, noise) interrupt request is not generated 1 Sync signal detector (VD, noise) interrupt request is generated Note: * Only 0 can be written to clear the flag. H'D0E0: Start Address Register STAR: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STA4 0 R/W 3 STA3 0 R/W 2 STA2 0 R/W 1 STA1 0 R/W 0 STA0 0 R/W H'D0E1: End Address Register EDAR: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 EDA4 0 R/W 3 EDA3 0 R/W 2 EDA2 0 R/W 1 EDA1 0 R/W 0 EDA0 0 R/W Rev.3.00 Jan. 10, 2007 page 953 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0E2: Serial Control Register 2 SCR2: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 TEIE 0 R/W 6 ABTIE 0 R/W 5 -- 1 -- 4 GAP1 0 R/W 3 GAP0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Transfer clock select bits CKS2 CKS1 CKS0 SCK2 pin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SCK2 input External clock SCK2 output Clock source Sprescaler S Prescaler frequency Transfer clock frequency division rate = 10 MHz = 5 MHz /256 25.6 s 51.2 s /64 6.4 s 12.8 s /32 3.2 s 6.4 s /16 1.6 s 3.2 s /8 /4 /2 0.8 s 0.4 s 1.6 s 0.8 s 0.4 s -- -- -- -- Transfer data interval select bits GAP1 GAP0 Transfer data interval 0 0 No interval 0 1 8-clock interval 1 0 24-clock interval 1 1 56-clock interval Transfer interrupt enable bit 0 Transfer interrupt request is disabled 1 Transfer interrupt request is enabled Transfer end interrupt enable bit 0 Transfer-end interrupt request is disabled 1 Transfer-end interrupt request is enabled Rev.3.00 Jan. 10, 2007 page 954 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D0E3: Serial Control Status Register 2 SCSR2: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 TEI 0 R/(W)* 6 -- 1 -- 5 -- 1 -- 4 SOL 0 R/W 3 ORER 0 R/(W)* 2 WT 0 R/(W)* 1 ABT 0 R/(W)* 0 STF 0 R/W Start flag 0 Read: Write: 1 Read: Write: Transfer stops Transfer aborted and SCI2 initialized Transfer in progress, or CS input standby Transfer starts Abort flag 0 [Clear condition] When 0 is written after reading 1 1 [Setting condition] When CS pin output level becomes high during transfer Wait flag 0 [Clear condition] When 0 is written after reading 1 1 [Setting condition] When read/write instruction to serial data buffer (32-bit) is generated while transfer is in progress or during CS input standby Overrun error flag 0 [Clear condition] When 0 is written after reading 1 1 [Setting condition] When extra pulse is over-applied to correct transfer clock or clock input is generated after transfer end, when using external clock Extension data bit 0 Read: SO2 pin output level is low Write: SO2 pin output level is changed to low 1 Read: SO2 pin output level is high Write: SO2 pin output level is changed to high Transfer end interrupt request flag 0 [Clear condition] When 0 is written after reading 1 1 [Setting condition] When transmission or reception ends Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 955 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D100: Timer Interrupt Enable Register ITER: Timer X1 Bit : 7 ICIAE Initial value : R/W : 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 ICSA 0 R/W Input capture input select A bit 0 1 FTIA pin input is selected for input capture A input HSW is selected for input capture A input Output compare interrupt enable bit 0 1 OFV interrupt request (FOVI) is disabled OFV interrupt request (FOVI) is enabled Output compare interrupt B enable bit 0 1 OCFB interrupt request (OCIB) is disabled OCFB interrupt request (OCIB) is enabled Output compare interrupt A enable bit 0 1 OCFA interrupt request (OCIA) is disabled OCFA interrupt request (OCIA) is enabled Input capture D interrupt enable bit 0 1 ICFD interrupt request (ICID) is disabled ICFD interrupt request (ICID) is enabled Input capture C interrupt enable bit 0 1 ICFC interrupt request (ICIC) is disabled ICFC interrupt request (ICIC) is enabled Input capture B interrupt enable bit 0 1 ICFB interrupt request (ICIB) is disabled ICFB interrupt request (ICIB) is enabled Input capture A interrupt enable bit 0 1 ICFA interrupt request (ICIA) is disabled ICFA interrupt request (ICIA) is enabled Rev.3.00 Jan. 10, 2007 page 956 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D101: Timer Control/Status Register X TCSRX: Timer X1 Bit : 7 ICFA Initial value : R/W : 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/ W Counter clear 0 1 Timer overflow 0 [Clearing condition] When 0 is written to OVF after reading OVF = 1 [Setting conditio] When FRC changes from H'FFFF to H'0000 FRC clearing is disabled FRC clearing is enabled 1 Output compare flag B 0 [Clearing condition] When 0 is written to OCFB after reading OCFB = 1 [Setting condition] When FRC = OCRB 1 Output compare flag A 0 [Clearing condition] When 0 is written to OCFA after reading OCFA = 1 [Setting condition] When FRC = OCRA 1 Input capture flag D 0 [Clearing condition] When 0 is written to ICFD after reading ICFD = 1 [Setting condition] When input capture signal is generated 1 Input capture flag C 0 [Clearing condition] When 0 is written to ICFC after reading ICFC = 1 [Setting condition] When input capture signal is generated 1 Input capture flag B 0 [Clearing condition] When 0 is written to ICFB after reading ICFB = 1 [Setting condition] When FRC value is transferred to ICRB by input capture signal 1 Input capture flag A 0 [Clearing condition] When 0 is written to ICFA after reading ICFA = 1 [Setting condition] When FRC value is transferred to ICRA by input capture signal 1 Note: * Only 0 can be written to bits 7 to 1 to clear the flags. Rev.3.00 Jan. 10, 2007 page 957 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D102: Free Running Counter H FRCH: Timer X1 H'D103: Free Running Counter L FRCL: Timer X1 FRC Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRCH FRCL H'D104: Output Compare Register AH, BH OCRAH, OCRBH: Timer X1 H'D105: Output Compare Register AL, BL OCRAL, OCRBL: Timer X1 OCRA, OCRB Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAH, OCRBH OCRAL, OCRBL Rev.3.00 Jan. 10, 2007 page 958 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D106: Timer Control Register X TCRX: Timer X1 Bit : 7 IEDGA Initial value : R/W : 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W Clock selct bit CKS1 0 0 1 1 CKS0 0 1 0 1 Clock select Internal clock: count at /4 Internal clock: count at /16 Internal clock: count at /64 DVCFG: Edge detection p ulse selected by CFG frequency division timer 0 CKS0 0 R/W Buffer enable B 0 1 Buffer enable A 0 1 ICRC is not used as buffer register for ICRA ICRC is used as buffer register for ICRA ICRC is not used as buffer register for ICRB ICRC is used as buffer register for ICRB Input capture edge select D 0 1 Capture at falling edge of input capture input D Capture at rising edge of input capture input D Input capture edge select C 0 1 Capture at falling edge of input capture input C Capture at rising edge of input capture input C Input capture edge select B 0 1 Capture at falling edge of input capture input B Capture at rising edge of input capture input B Input capture edge select A 0 1 Capture at falling edge of input capture input A Capture at rising edge of input capture input A Rev.3.00 Jan. 10, 2007 page 959 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D107: Timer Output Compare Control Register TOCR: Timer X1 Bit : 7 ICSB Initial value : R/W : 0 R/W 6 ICSC 0 R/W 5 ICSD 0 R/W 4 OSRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W Output level B 0 1 Output level A 0 1 Output enable B 0 1 Output enable A 0 1 Output compare A output is disabled Output compare A output is enabled Output compare B output is disabled Output compare B output is enabled Low level High level Low level High level Output compare register select 0 1 OCRA register is selected OCRB register is selected Input capture input select D 0 1 FTID pin is selected for input capture D input NHSW is selected for input capture D input Input capture input select C 0 1 FTIC pin is selected for input capture C input DVCTL is selected for input capture C input Input capture input select B 0 1 FTIB pin is selected for input capture B input VD is selected for input capture B input Rev.3.00 Jan. 10, 2007 page 960 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D108: Input Capture Register AH ICRAH: Timer X1 H'D109: Input Capture Register AL ICRAL: Timer X1 H'D10A: Input Capture Register BH ICRBH: Timer X1 H'D10B: Input Capture Register BL ICRBL: Timer X1 H'D10C: Input Capture Register CH ICRCH: Timer X1 H'D10D: Input Capture Register CL ICRCL: Timer X1 H'D10E: Input Capture Register DH ICRDH: Timer X1 H'D10F: Input Capture Register DL ICRDL: Timer X1 ICRA, ICRB, ICRC, ICRD Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL Rev.3.00 Jan. 10, 2007 page 961 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D110: Timer Mode Register B TMB: Timer B Bit : 7 TMB17 Initial value : R/W : 0 R/W 6 TMBIF 0 R/(W)* 5 TMBIE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMB12 0 R/W 1 TMB11 0 R/W 0 TMB10 0 R/W Clock select bit TMB12 0 0 0 0 1 1 1 1 TMB11 0 0 1 1 0 0 1 1 TMB10 0 1 0 1 0 1 0 1 Clock select Internal clock: Count at /16384 Internal clock: Count at /4096 Internal clock: Count at /1024 Internal clock: Count at /512 Internal clock: Count at /128 Internal clock: Count at /32 Internal clock: Count at /8 Count at rising/falling edge of external event (TMBI)* Note: * External event edge selection is set at PMR51 in port mode register 5 (PMR5). See section 13.2.4, Port Register 5 (PMR5). Timer B interrupt enable bit 0 1 Timer B interrupt request is disabled Timer B interrupt request is enabled Timer B interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When TCB overflows Auto reload function select bit 0 1 Interval function is selected Auto reload function is selected Note: * Only 0 can be written to clear the flag. H'D111: Timer Counter B TCB: Timer B Bit : 7 TCB17 Initial value : R/W : 0 R 6 TCB16 0 R 5 TCB15 0 R 4 TCB14 0 R 3 TCB13 0 R 2 TCB12 0 R 1 TCB11 0 R 0 TCB10 0 R Rev.3.00 Jan. 10, 2007 page 962 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D111: Timer Load RegisterB TLB: TimerB Bit : 7 TLB17 Initial value : R/W : 0 W 6 TLB16 0 W 5 TLB15 0 W 4 TLB14 0 W 3 TLB13 0 W 2 TLB12 0 W 1 TLB11 0 W 0 TLB10 0 W H'D112: Timer L Mode Register LMR: Timer L Bit : 7 LMIF Initial value : R/W : 0 R/(W)* 6 LMIE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 IMR3 0 R/W 2 IMR2 0 R/W 1 IMR1 0 R/W 0 IMR0 0 R/W Clock select bit R2 0 LMR1 0 1 1 0 1 Legend: * Don't care. Up/down count control 0 1 Up count control Down count control LMR0 0 1 * * * Clock select Count at rising edge of PB and REC-CTL Count at falling edge of PB and REC-CTL Count DVCFG2 Internal clock: Count at /128 Internal clock: Count at /64 Timer L interrupt enable bit 0 1 Timer L interrupt request is disabled Timer L interrupt request is enabled Timer L interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When LTC overflow, underflow or compare match clear occurs Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 963 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D113: Linear Time Counter LTC: Timer L Bit : 7 LTC7 Initial value : R/W : 0 R 6 LTC6 0 R 5 LTC5 0 R 4 LTC4 0 R 3 LTC3 0 R 2 LTC2 0 R 1 LTC1 0 R 0 LTC0 0 R H'D113: Reload/Compare Match Register RCR: Timer L Bit : 7 RCR7 Initial value : R/W : 0 W 6 RCR6 0 W 5 RCR5 0 W 4 RCR4 0 W 3 RCR3 0 W 2 RCR2 0 W 1 RCR1 0 W 0 RCR0 0 W Rev.3.00 Jan. 10, 2007 page 964 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D118: Timer R Mode Register 1 TMRM1: Timer R Bit : 7 CLR2 Initial value : R/W : 0 R/W 6 AC/BR 0 R/W 5 RLD 0 R/W 4 RLCK 0 R/W 3 PS21 0 R/W 2 PS20 0 R/W 1 RLD/CAP 0 R/W 0 CPS 0 R/W TMRU-1 capture signal select bit 0 1 Capture signal at CFG rising edge Capture signal at IRQ3 edge TMRU-1 operation mode select bit 0 1 TMRU-1 functions as reload timer TMRU-1 functions as capture timer TMRU-2 clock source select bits PS21 0 1 PS20 0 1 0 1 TMRU-2 clock source select Count at TMRU-1 underflow PSS, count at /256 PSS, count at /128 PSS, count at /64 TMRU-2 reload timing select bit 0 1 Reload at CFG rising edge Reload at TMRU underflow Execution/non-execution of reload by TMRU-2 0 1 TMRU-2 is not used as reload timer TMRU-2 is used as reload timer Acceleration/deceleration select bit 0 1 Deceleration Acceleration TMRU-2 clear select bit 0 1 TMRU-2 is not cleard at the time of capture TMRU-2 is cleard at the time of capture Rev.3.00 Jan. 10, 2007 page 965 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D119: Timer R Mode Register TMRM2: Timer R Bit : 7 LAT Initial value : R/W : 0 R/W 6 PS11 0 R/W 5 PS10 0 R/W 4 PS31 0 R/W 3 PS30 0 R/W 2 CP/SLM 0 R/W 1 CAPF 0 R/(W)* 0 SLW 0 R/(W)* Slow tracking mono-multi flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When slow tracking mono-multi ends while CP/SLM bit = 1 Capture signal flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When TMRU-2 capture signal is generated while CP/SLM bit = 0 Interrupt select bit 0 1 Interrupt request by TMRU-2 capture signal is enabled Interrupt request by slow tracking mono-multi end is enabled TMRU-3 clock source select bits PS31 0 1 PS30 0 1 0 1 TMRU-3 clock source select Count at rising edge of DVCTL from frequency divider PSS, count at /4096 PSS, count at /2048 PSS, count at /1024 TMRU-1 clock source select bits PS11 0 1 PS10 0 1 0 1 TMRU-1 clock source select Count at CFG rising edge PSS, count at /4 PSS, count at /256 PSS, count at /512 TMRU-2 captrue signal select bits LAT 0 1 CPS * 0 1 Legend: * Don't care. TMRU-2 capture signal select Capture at TMRU-3 underflow Capture at CFG rising edge Capture at IRQ3 edge Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 966 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D11A: Timer R Capture Register 1 TMRCP1: Time R Bit : 7 6 5 4 3 2 1 0 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 Initial value : R/W : 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R H'D11B: Timer R Capture Register 2 TMRCP2: Time R Bit : 7 6 5 4 3 2 1 0 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : R/W : 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R H'D11C: Timer R Load Register 1 TMRL1: Timer R Bit : 7 TMR17 Initial value : R/W : 1 W 6 TMR16 1 W 5 TMR15 1 W 4 TMR14 1 W 3 TMR13 1 W 2 TMR12 1 W 1 TMR11 1 W 0 TMR10 1 W H'D11D: Timer R Load Register 2 TMRL2: Timer R Bit : 7 TMR27 Initial value : R/W : 1 W 6 TMR26 1 W 5 TMR25 1 W 4 TMR24 1 W 3 TMR23 1 W 2 TMR22 1 W 1 TMR21 1 W 0 TMR20 1 W H'D11E: Timer R Load Register 3 TMRL3: Timer R Bit : 7 TMR37 Initial value : R/W : 1 W 6 TMR36 1 W 5 TMR35 1 W 4 TMR34 1 W 3 TMR33 1 W 2 TMR32 1 W 1 TMR31 1 W 0 TMR30 1 W Rev.3.00 Jan. 10, 2007 page 967 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D11F: Timer R Control/Status Register TMRCS: Timer R Bit : 7 TMRI3E Initial value : R/W : 0 R/W 6 TMRI2E 0 R/W 5 TMRI1E 0 R/W 4 TMRI3 0 R/(W)* 3 TMRI2 0 R/(W)* 2 TMRI1 0 R/(W)* 1 -- 1 -- 0 -- 1 -- TMRI1 interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When TMRU-1 underflows TMRI2 interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When TMRU-2 underflows or when capstan motor acceleration/deceleration operation ends TMRI3 interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When interrupt source selected at CP/SLM bit in TMRM2 is generated TMRI1 interrupt enable bit 0 1 TMRI1 interrupt request is disabled TMRI1 interrupt request is enabled TMRI2 interrupt enable bit 0 1 TMRI2 interrupt request is disabled TMRI2 interrupt request is enabled TMRI3 interrupt enable bit 0 1 TMRI3 interrupt request is disabled TMRI3 interrupt request is enabled Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 968 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D120: PWM Data Register L PWDRL: 14-Bit PWM Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D121: PWM Data Register U PWDRU: 14-Bit PWM Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 0 W 0 W 0 W 0 W 0 W 0 W H'D122: PWM Control Register PWCR: 14-Bit PWM Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PWCR0 0 R/W Clock select bit 0 Input clock is /2 (t = 2/) Generate PWM waveform with conversion frequency of 16384/ and minimum pulse width of 1/ Input clock is /4 (t = 4/) Generate PWM waveform with conversion frequency of 32768/ and minimum pulse width of 2/ 1 Note: * t: PWM input clock frequency H'D126: 8-Bit PWM Data Register 0 PWR0: 8-Bit PWM Bit : Initial value : R/W : 7 PW07 0 W 6 PW06 0 W 5 PW05 0 W 4 PW04 0 W 3 PW03 0 W 2 PW02 0 W 1 PW01 0 W 0 PW00 0 W Rev.3.00 Jan. 10, 2007 page 969 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D127: 8-Bit PWM Data Register 1 PWR1: 8-Bit PWM Bit : Initial value : R/W : 7 PW17 0 W 6 PW16 0 W 5 PW15 0 W 4 PW14 0 W 3 PW13 0 W 2 PW12 0 W 1 PW11 0 W 0 PW10 0 W H'D128: 8-Bit PWM Data Register 2 PWR2: 8-Bit PWM Bit : Initial value : R/W : 7 PW27 0 W 6 PW26 0 W 5 PW25 0 W 4 PW24 0 W 3 PW23 0 W 2 PW22 0 W 1 PW21 0 W 0 PW20 0 W H'D129: 8-Bit PWM Data Register 3 PWR3: 8-Bit PWM Bit : Initial value : R/W : 7 PW37 0 W 6 PW36 0 W 5 PW35 0 W 4 PW34 0 W 3 PW33 0 W 2 PW32 0 W 1 PW31 0 W 0 PW30 0 W H'D12A: 8-Bit PWM Control Register PW8CR: 8-Bit PWM Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PWC3 0 R/W 2 PWC2 0 R/W 1 PWC1 0 R/W 0 PWC0 0 R/W Output polarity select bits 0 1 Note: Positive polarity Negative polarity n = 3 to 0 H'D12C: Input Capture Register 1 ICR1: PSU Bit : Initial value : R/W : 7 ICR17 0 R 6 ICR16 0 R 5 ICR15 0 R 4 ICR14 0 R 3 ICR13 0 R 2 ICR12 0 R 1 ICR11 0 R 0 ICR10 0 R Rev.3.00 Jan. 10, 2007 page 970 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D12D: Prescaler Unit Control/Status Register PCSR: PSU Bit : Initial value : R/W : 7 ICIF 0 R/(W)* 6 ICIE 0 R/W 5 ICEG 0 R/W 4 NCon/off 0 R/W 3 -- 1 -- 2 DCS2 0 R/W 1 DCS1 0 R/W 0 DCS0 0 R/W Frequency division clock output select bits DCS2 0 DCS1 0 1 1 0 1 DCS0 0 1 0 1 0 1 0 1 Noise cancel ON/OFF bit 0 1 IC pin edge select bit 0 1 Falling edge of IC pin input is detected Rising edge of IC pin input is detected Noise cancel function of IC pin is disabled Noise cancel function of IC pin is enabled Frequency division clodk output select PSS, output /32 PSS, output /16 PSS, output /8 PSS, output /4 PSW, output W/32 PSW, output W/16 PSW, output W/8 PSW, output W/4 Input capture interrupt enable bit 0 1 Interrupt request by input capture is disabled Interrupt request by input capture is enabled Input capture interrupt flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When input capture is executed at IC pin edge Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 971 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D130: Software Trigger A/D Result Register H ADRH: A/D Converter H'D131: Software Trigger A/D Result Register L ADRL: A/D Converter ADRH Bit : Initial value : R/W : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 -- 0 -- ADRL 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 H'D132: Hardware Trigger A/D Result Register H AHRH: A/D Converter H'D133: Hardware Trigger A/D Result Register L AHRL: A/D Converter AHRH Bit : Initial value : R/W : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 -- 0 -- AHRL 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0 Rev.3.00 Jan. 10, 2007 page 972 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D134: A/D Control Register ADCR: A/D Converter Bit : Initial value : R/W : 7 CK 0 R/W 6 -- 1 -- 5 HCH1 0 R/W 4 HCH0 0 R/W 3 SCH3 0 R/W 2 SCH2 0 R/W 1 SCH1 0 R/W 0 SCH0 0 R/W Software channel select bits SCH3 SCH2 SCH1 SCH0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 * * Analog input channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB Software-triggered conversion channel is not selected Legend: * Don't care. Note: If conversion is started by software when SCH3 to SCH0 are set to 11**, the conversion result is undetermined. Hardware- or external-triggered conversion, however, will be performed on the channel selected by HCH1 and HCH0. Hardware channel select bits HCH1 HCH2 Analog input channel 0 0 AN8 1 AN9 1 0 ANA 1 ANB Clock select 0 Conversion frequency = 266 states 1 Conversion frequency = 134 states Rev.3.00 Jan. 10, 2007 page 973 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D135: A/D Control/Status Register ADCSR: A/D Converter Bit : Initial value : R/W : 7 SEND 0 R/(W)* 6 HEND 0 R//(W)* 5 ADIE 0 R/W 4 SST 0 R/W 3 HST 0 R 2 BUSY 0 R 1 SCNL 0 R 0 -- 1 -- Software-triggered A/D conversion cancel flag 0 No contention for A/D conversion 1 Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered A/D conversion. Busy flag 0 No contention for A/D conversion 1 Indicates an attempt to execute software-triggerd A/D conversion was canceled by the start of hardwaretriggered A/D conversion. Hardware A/D status flag 0 Read: Hardware- or external -triggered A/D conversion is not in progress Write: Hardware- or external-triggered A/D conversion is aborted 1 Hardware- or external-triggered A/D conversion has ended or been stopped Software A/D start flag 0 Read: Indicates that software-triggered A/D conversion has ended or been stopped Write: Software-triggered A/D conversion is aborted 1 Read: Indicates that software-triggered A/D conversion is in progress Write: Starts software-triggered A/D conversion A/D interrupt enable bit 0 Interrupt (ADI) upon A/D conversion end is disabled 1 Interrupt (ADI) upon A/D conversion end is enabled Hardware A/D end flag 0 [Clearing condition] When 0 is written after reading 1 1 [Setting condition] When hardware- or external-triggered A/D conversion has ended Software A/D end flag 0 [Clearing condition] When 0 is written after reading 1 1 [Setting condition] When software-triggered A/D conversion has ended Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 974 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D136: A/D Trigger Select Register ADTSR: A/D Converter Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 TRGS1 0 R/W 0 TRGS0 0 R/W Trigger select bits TRGS1 TRGS0 0 0 Hardware- or external-triggered A/D conversion is disabled 1 Hardware-triggered (ADTRG) A/D conversion is selected 1 0 Hardware-triggered (DFG) A/D conversion is selected 1 External-triggered (ADTRG) A/D conversion is selected H'D138: Timer Load Register K TLK: Timer J Bit : 7 TLR27 Initial value : R/W : 1 W 6 TLR26 1 W 5 TLR25 1 W 4 TLR24 1 W 3 TLR23 1 W 2 TLR22 1 W 1 TLR21 1 W 0 TLR20 1 W H'D138: Timer Counter K TCK: Timer J Bit : 7 TDR27 Initial value : R/W : 1 R 6 TDR26 1 R 5 TDR25 1 R 4 TDR24 1 R 3 TDR23 1 R 2 TDR22 1 R 1 TDR21 1 R 0 TDR20 1 R H'D139: Timer Load Register J TLJ: Timer J Bit : 7 TLR17 Initial value : R/W : 1 W 6 TLR16 1 W 5 TLR15 1 W 4 TLR14 1 W 3 TLR13 1 W 2 TLR12 1 W 1 TLR11 1 W 0 TLR10 1 W Rev.3.00 Jan. 10, 2007 page 975 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D139: Timer Counter J TCJ: Timer J Bit : 7 TDR17 Initial value : R/W : 1 R 6 TDR16 1 R 5 TDR15 1 R 4 TDR14 1 R 3 TDR13 1 R 2 TDR12 1 R 1 TDR11 1 R 0 TDR10 1 R Rev.3.00 Jan. 10, 2007 page 976 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D13A: Timer Mode Register J TMJ: Timer J Bit : 7 PS11 Initial value : R/W : 0 R/W 6 PS10 0 R/W 5 ST 0 R/W 4 8/16 0 R/W 3 PS21 0 R/W 2 PS20 0 R/W 1 TGL 0 R 0 T/R 0 R/W Timer output/remote-controller output select bit 0 TMJ-1 timer output 1 TMJ-1 toggle output (data transmitted from remote controller) TMJ-2 toggle flag 0 TMJ-2 toggle output is 0 1 TMJ-2 input clock select bits PS22*3 PS21 PS20 1 0 1 0 1 0 1 0 * * TMJ-2 toggle output is 1 TMJ-2 input clock select Counthing by the PSS, /16384 Counthing by the PSS, /2048 Counting at underflowing of the TMJ-1 Counting at the leading edge or the trailing edge of the external clock inputs (IRQ2)*1 Counting by the PSS, /1024*2 Legend: * Don't care. Notes: 1. The edge selection for the external clock inputs is made by setting the edge select register (IEGR). See section 6.2.4, IRQ Edge Select Register (IEGR) for more information. 2. Available only in the H8S/2194C Group. 8-bit/16-bit operation select bit 0 1 TMJ-1 and TMJ-2 operate separately TMJ-1 and TMJ-2 operate together as 16-bit Remote-controlled operation start bit 0 1 TMJ-1 input clock select bits PS11 0 1 PS10 0 1 0 1 PSS, count at /512 PSS, count at /256 PSS, count at /4 Count at rising/falling edge of external clock (IRQ1) TMJ-1 input clock select Stop TMJ-1 clock supply in remote control mode Start TMJ-1 clock supply in remote control mode Note: * External clock edge selection is set in edge select register (IEGR). See section explaining edge select register (IEGR). When using external clock in remote control mode, set opposite edges for IRQ1 and IRQ2 edges (eg. When falling edge is set for IRQ1, set rising edge for IRQ2). Rev.3.00 Jan. 10, 2007 page 977 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D13B: Timer J Control Register TMJC: Timer J Bit : 7 BUZZ1 Initial value : R/W : 0 R/W 6 BUZZ0 0 R/W 5 MON1 0 R/W 4 MON0 0 R/W 3 -- 1 -- 2 TMJ2IE 0 R/W 1 TMJ1IE 0 R/W 0 (PS22)* 1 (R/W)* H8S/2194 Group: When ths is read, 1 will always be readout. Writes are disabled. H8S/2194C Group: This bit, together with bit 3 and 2 (PS21,PS20) in TMJ, selects the input clock for TMJ-2. TMJ1I interrupt enable bit 0 1 TMJ1I interrupt request is disabled TMJ1I interrupt request is enabled TMJ2I interrupt enable bit 0 1 Monitor output select bits MON1 0 1 MON0 0 1 * Legend: * Don't care. Buzzer output select bits BUZZ1 0 1 BUZZ0 0 1 0 1 Output signal /4096 /8192 Output monitor signal Output Timer J BUZZ signal Frequency when = 10 MHz TMJ2I interrupt request is disabled TMJ2I interrupt request is enabled Monitor output select PB or REC-CTL DVCTL Output TCA7 2.44 kHz 1.22 kHz Note: * Bit 0 is readable/writable only in the H8S/2194C Group. Rev.3.00 Jan. 10, 2007 page 978 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D13C: Timer J Status Register TMJS: Timer J Bit : 7 TMJ2I Initial value : R/W : 0 R/(W)* 6 TMJ1I 0 R/(W)* 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- TMJ1I interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When TMJ-1 underflows TMJ2I interrupt request flag 0 1 [Clearing condition] When 0 is written after reading 1 [Setting condition] When TMJ-2 underflows Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 979 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D148: Serial Mode Register SMR1: SCI1 Bit : 7 C/A Initial value : R/W : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W Clock select CKS1 0 1 CKS0 0 1 0 1 Multiprocessor mode 0 1 Stop bit length 0 1 1 Stop bit*1 2 Stop bit*2 Multiprocessor function is disabled Multiprocessor format is selected Clock select clock /4 clock /16 clock /64 clock 0 CKS0 0 R/W Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. Parity mode 0 1 Even parity*1 Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 1 8-bit data 7-bit data Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSB-first/MSB-first selection is not available. Communication mode 0 1 Start-stop synchronous mode Clock synchronouns mode Rev.3.00 Jan. 10, 2007 page 980 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D149: Bit Rate Register BRR1: SCI1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : Rev.3.00 Jan. 10, 2007 page 981 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D14A: Serial Control Register SCR1: SCI1 Bit : 7 TIE Initial value : R/W : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable bits CKE1 0 CKE0 0 1 1 0 1 Clock select Start-stop synchronous mode Internal clock/SCK1 pin function as I/O port*1 Clock synchronous mode Internal clock/SCK1 pin function as serial clock output*1 Start-stop synchronous mode Internal clock/SCK1 pin function as clock output*2 Clock synchronous mode Internal clock/SCK1 pin function as serial clock output Start-stop synchronous mode External clock/SCK1 pin function as clock input*3 Clock synchronous mode External clock/SCK1 pin function as serial clock input Start-stop synchronous mode External clock/SCK1 pin function as clock input*3 Clock synchronous mode External clock/SCK1 pin function as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable bit 0 1 Transmit-end interrupt (TEI) request is disabled* Transmit-end interrupt (TEI) request is enabled* Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Multiprocessor interrupt enable bit 0 Multiprocessor interrupts are disabled (normal reception performed) [Clearing conditions] (1) When the MPIE bit is cleared to 0 (2) When data with MPB = 1 is received Multiprocessor interrupt are enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR1 are disabled until data with the multiprocessor bit set to 1 is received. 1 Note: * When receive data including MPB = 0 is reveived, receive data transfer from RSR to RDR1, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR1, is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR1 is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR1 are set to 1) and FER and ORER flag setting is enabled. Receive enable bit 0 1 Reception is disabled*1 Reception is enabled*2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR1 setting must be performed to decide the reception format before setting the RE bit to 1. Transmit enable bit 0 1 Transmission is disabled*1 Transmission is enabled*2 Notes: 1. The TDRE flag in SSR1 is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and TDRE flag in SSR1 is cleared to 0. SMR1 setting must be performed to decide the transmission format before setting the TE bit to 1. Receive interrupt enable bit 0 1 Reveive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is disabled* Reveive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Transmit interrupt enable bit 0 1 Transmit-data-empty interrupt (TXI) request is disabled* Transmit-data-empty interrupt (TXI) request is enabled Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Rev.3.00 Jan. 10, 2007 page 982 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D14B: Transmit Data Register TDR1: SCI1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : Rev.3.00 Jan. 10, 2007 page 983 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D14C: Serial Status Register SSR1: SCI1 Bit : 7 TDRE Initial value : R/W : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer 0 1 Multiprocessor bit 0 1 [Clearing condition]* When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is reveived Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Note: * Retains its previous state when the RE bit in SCR1 is cleared to 0 with multiprocessor format. Transmit end 0 1 [Clearing condition] When 0 is written in TDRE after reading TDRE = 1 [Setting conditions] (1) When the TE bit in SCR1 is 0 (2) When TDRE = 1 at trasmission of the last bit of a 1-byte serial transmit character Parity error 0 1 [Clearing condition]*1 When 0 is written in PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR1*2 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Framing error 0 1 [Clearing condition]*1 When 0 is written in FER after reading FER = 1 [Setting condition] When the SCI1 checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0.*2 Overrun errro 0 1 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. [Clearing condition]*1 When 0 is written in ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 *2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR1, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Receive data register full 0 1 [Clearing condition] When 0 is written in RDRF after reading RDRF = 1 [Setting condition] When serial reception ends normally adn receive data is transferred from RSR to RDR1 Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit data register empty 0 1 [Clearing condition] When 0 is written in TDRE after reading TDRE = 1 [Setting conditions] (1) When the TE bit in SCR1 is 0 (2) When data is transferred from TDR1 to TSR and data can be written to TDR1 Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 984 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D14D: Receive Data Register RDR1: SCI1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : H'D14E: Serial Interface Mode Register SCMR1: SCI1 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Serial communication inteface mode select 0 1 Data invert 0 TDR1 contents are transmitted without modification Receive data is stored in RDR1 without modification TDR1 contents are onverted before being transmitted Receive data is stored in RDR1 in inverted form Normal SCI mode Reserved mode 1 Data transfer direction 0 1 TDR1 contents are transmitted LSB-first Receive data is stored in RDR1 LSB-first TDR1 contents are transmitted MSB-first Receive data is stored in RDR1 MSB-first Rev.3.00 Jan. 10, 2007 page 985 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D158: I C Bus Control Register ICCR: IIC Bus Interface Bit : 7 ICE Initial value : R/W : 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 ACKE 0 R/W 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 1 W 2 Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1 Writing is ignored I2C bus interface interrupt request flag 0 Waiting for transfer, or transfer in progress [Clearing condition] When 0 is written in IRIC after reading IRIC = 1 Interrupt requested [Setting conditions] 2 * I C bus format master mode (1) When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) (2) When a wait is inserted between the data and acknowledge bit when WAIT = 1 (3) At the end of data transfer (at the rise of the 9th transmit clock pulse, and at the fall of the 8th transmit/ receive clock pulse when a wait is inserted) (4) When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) (5) When 1 is reveived as teh acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) 2 * I C bus format slave mode (1) When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (2) When the general call address is detected (when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (3) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) (4) When a stop condition is detected (when the STOP or ESTP flag is set to 1) * Synchronous serial format (1) At the end of data transfer (when the TDRE or RDRF flag is set to 1) (2) When a start condition is detected with serial format selected When conditions are occurred such that the TDRE or RDRF flag is set to 1 1 Bus busy 0 Bus is free [Clearing condition] 1 Bus is busy [Setting condition] Acknowledge bit judgment selection 0 The value of the acknowledge bit is ignored, and continuous transfer is performed 1 If the acknowledge bit is 1, continuous transfer is interrupted Master/slave select Transmit/receive select MST 0 1 TRS 0 1 0 1 Slave reveive mode Slave transmit mode Master receive mode Master transmit mode When a stop condition is detected When a start condition is detected I2C bus interface interrupt enable 0 Interrupt request is disabled 1 Interrupt request is enabled I2C bus interface enable 0 I2C bus interface module disabled, with SCL and SDA signal pins set to port function. Initialization of the internal state of the I2C module. SAR and SARX can be accessed 1 I2C bus interface module enabled for transfer operation (pins SCL and SDA are driving the bus) Note: * Only 0 can be written to clear the falg. Rev.3.00 Jan. 10, 2007 page 986 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D159: I C Bus Status Register ICSR: IIC Bus Interface Bit : 7 ESTP Initial value : R/W : 0 R/(W)* 6 STOP 0 R/(W)* 5 IRTR 0 R/(W)* 4 AASX 0 R/(W)* 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 R/(W)* 0 ACKB 0 R/W 2 Acknowledge bit 0 Receive mode: 0 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has acknowldeged the data (signal is 0) 1 Receive mode; 1 is output at acknowledge output timing General call address recognition flag 0 General call address not recognized [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in ADZ after reading ADZ = 1 (3) In master mode 1 General call address recognized [Setting condition] When the general call address is detected in slave receive mode Slave address recognition flag 0 Slave address or general call address not recognized [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AAS after reading AAS = 1 (3) In master mode 1 Slave address or general call address recognized [Setting condition] When the slave address or general call address is detected in slave receive mode Arbitration lost flag 0 Bus arbitration won [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] (1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode (2) If the internal SCL line is high at the fall of SCL in master transmit mode Second slave address recognition flag 0 Second slave address not recognized [Clearing conditions] (1) When 0 is written in AASX after reading AASX = 1 (2) When a start condition is detected (3) In master mode 1 Second slave address recognized [Setting condition] When the second slave address is detected in slave receive mode while FSX = 0 I2C bus interface continuous transmission/reception interrupt request flag 0 Waiting for transfer, or transfer in progress [Clearing conditions] (1) When 0 is written in IRTR after reading IRTR = 1 (2) When the IRIC flag is cleared to 0 1 Continuous transfer state [Setting conditions] 2 * In I C bus interface slave mode When the TDRE or RDRF flag is set to 1 when AASX = 1 * In other mode When the TDRE or RDRF flag is set to 1 Normal stop condition detection flag 0 No normal stop condition [Clearing conditions] (1) When 0 is written in STOP after reading STOP = 1 (2) When the IRIC flag is cleared to 0 2 1 * In I C bus format slave mode Normal stop condition detected [Setting condition] When a stop condition is detected after completion of frame transfer * In other mode No meaning Error stop condition detection flage 0 No error stop condition [Clearing conditions] (1) When 0 is written in ESTP after reading ESTP = 1 (2) When the IRIC flag is cleared to 0 2 1 * In I C bus format slave mode Error stop condition detected [Setting condition] When a stop condition is detected during frame transfer * In other mode No meaning Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 987 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D15E: I C Bus Data Register ICDR: IIC Bus Interface Bit : 7 ICDR7 Initial value : R/W : -- R/W 6 ICDR6 -- R/W 5 ICDR5 -- R/W 4 ICDR4 -- R/W 3 ICDR3 -- R/W 2 ICDR2 -- R/W 1 ICDR1 -- R/W 0 ICDR0 -- R/W 2 H'D15E: Second Slave Address Register SARX: IIC Bus Interface Bit : 7 SVAX6 Initial value : R/W : 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W Format select Used combined with SAR FS bit. Rev.3.00 Jan. 10, 2007 page 988 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D15F: I C Bus Mode Register ICMR: IIC Bus Interface Bit : 7 MLS Initial value : R/W : 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W Bit counter BC2 BC1 BC0 Bit/frame Clock sync I2C bus format serial format 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 2 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W 0 0 1 0 0 1 0 1 0 1 0 1 0 1 Transfer clock select bits IICX* CKS2 CKS1 CKS0 Clock 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 Transfer rate = 5 MHz = 8 MHz = 10 MHz 179 kHz 286 kHz 357 kHz 125 kHz 200 kHz 250 kHz 104 kHz 167 kHz 208 kHz 78.1 kHz 125 kHz 156 kHz 62.5 kHz 100 kHz 125 kHz 50.0 kHz 80.0 kHz 100 kHz 44.6 kHz 71.4 kHz 89.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 89.3 kHz 143 kHz 179 kHz 62.5 kHz 100 kHz 125 kHz 52.1 kHz 83.3 kHz 104 kHz 39.1 kHz 62.5 kHz 78.1 kHz 31.3 kHz 50.0 kHz 62.5 kHz 25.0 kHz 40.0 kHz 50.0 kHz 22.3 kHz 35.7 kHz 44.6 kHz 19.5 kHz 31.3 kHz 39.1 kHz Note: * See STCR Bit 6. Wait insertion bit 0 Data and acknowledge bits transferred consecutively 1 Wait inserted between data and acknowledge bits MSB-first/LSB-first select 0 MSB-first 1 LSB-first Rev.3.00 Jan. 10, 2007 page 989 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'D15F: Slave Address Register SAR: IIC Bus Interface Bit : 7 SVA6 Initial value : R/W : 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W Format select bit SAR SARX Bit 0 Bit 0 FS FX 0 0 1 Format select 1 0 1 I C bus format * SAR and SARX slave addresses recognized 2 I C bus format * SAR slave address recognized * SARX slave address ignored 2 I C bus format * SAR slave address ignored * SARX slave address recognized 2 I C bus format * SAR and SARX slave addresses ignored 2 H'FFB0: Trap Address Register 0 TAR0: ATC H'FFB3: Trap Address Register 1 TAR1: ATC H'FFB6: Trap Address Register 2 TAR2: ATC Bit : 7 A23 Initial value : R/W : Bit : 0 R/W 7 A15 Initial value : R/W : Bit : 0 R/W 7 A7 Initial value : R/W : 0 R/W 6 A22 0 R/W 6 A14 0 R/W 6 A6 0 R/W 5 A21 0 R/W 5 A13 0 R/W 5 A5 0 R/W 4 A20 0 R/W 4 A12 0 R/W 4 A4 0 R/W 3 A19 0 R/W 3 A11 0 R/W 3 A3 0 R/W 2 A18 0 R/W 2 A10 0 R/W 2 A2 0 R/W 1 A17 0 R/W 1 A9 0 R/W 1 A1 0 R/W 0 A16 0 R/W 0 A8 0 R/W 0 -- 0 -- Rev.3.00 Jan. 10, 2007 page 990 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFB9: Address Trap Control Register ATCR: ATC Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TRC2 0 R/W 1 TRC1 0 R/W 0 TRC0 0 R/W Trap control 0 0 Address trap function 0 is disabled 1 Address trap function 0 is enabled Trap control 1 0 Address trap function 1 is disabled 1 Address trap function 1 is enabled Trap control 2 0 Address trap function 2 is disabled 1 Address trap function 2 is enabled Rev.3.00 Jan. 10, 2007 page 991 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFBA: Timer Mode Register A TMA: Timer A Bit : 7 TMAOV Initial value : R/W : 0 R/(W)* 6 TMAIE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W Clock select bits TMA3 TMA2 TMA1 TMA0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: = f osc Clock source, prescaler select bit 0 1 Timer A clock source is PSS Timer A clock source is PSW 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler frequency division rate (interval timer) Operation mode or overflow frequency (time-base) PSS, /16384 PSS, /8192 PSS, /4096 PSS, /1024 PSS, /512 PSS, /256 PSS, /64 PSS, /16 1s 0.5 s 0.25 s 0.03125 s Clear PSW and TCA to H'00 Interval timer mode Clock time base mode Timer A interrupt enable bit 0 1 Timer A overflow flag 0 [Clearing condition] When 0 is written to TMAOV after reading TMAOV = 1 [Setting condition] When TCA overflows Interrupt request by Timer A (TMAI) is disabled Interrupt request by Timer A (TMAI) is enabled 1 Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 992 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFBB: Timer Counter A TCA: TimerA Bit : 7 TCA7 Initial value : R/W : 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R H'FFBC: Watchdog Timer Control/Status Register WTCSR: WDT Bit : Initial value : R/W : 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 RSTS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Reset or NMI 0 NMI interrupt request is disabled 1 Internal reset request is generated Timer enable bit 0 1 WTCNT is initialized to H'00 and halted WTCNT counts Timer mode select bit 0 1 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when WTCNT overflows Watchdog timer mode: Sends the CPU a reset or NMI interrupt request when WTCNT overflows Overflow flag 0 [Clearing conditions] (1) Write 0 in the TME bit (2) Read WTCSR when OVF = 1, then write 0 in OVF [Setting condition] When WTCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.) 1 Note: * Only 0 can be written to clear the flag. Rev.3.00 Jan. 10, 2007 page 993 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFBD: Watchdog Timer Counter WTCNT: WDT Bit : Initial value : R/W : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W H'FFC0: Port Data Register 0 PDR0: I/O Port Bit : Initial value : R/W : 7 PDR07 -- R 6 PDR06 -- R 5 PDR05 -- R 4 PDR04 -- R 3 PDR03 -- R 2 PDR02 -- R 1 PDR01 -- R 0 PDR00 -- R H'FFC1: Port Data Register 1 PDR1: I/O Port Bit : Initial value : R/W : 7 PDR17 0 R/W 6 PDR16 0 R/W 5 PDR15 0 R/W 4 PDR14 0 R/W 3 PDR13 0 R/W 2 PDR12 0 R/W 1 PDR11 0 R/W 0 PDR10 0 R/W H'FFC2: Port Data Register 2 PDR2: I/O Port Bit : Initial value : R/W : 7 PDR27 0 R/W 6 PDR26 0 R/W 5 PDR25 0 R/W 4 PDR24 0 R/W 3 PDR23 0 R/W 2 PDR22 0 R/W 1 PDR21 0 R/W 0 PDR20 0 R/W H'FFC3: Port Data Register 3 PDR3: I/O Port Bit : Initial value : R/W : 7 PDR37 0 R/W 6 PDR36 0 R/W 5 PDR35 0 R/W 4 PDR34 0 R/W 3 PDR33 0 R/W 2 PDR32 0 R/W 1 PDR31 0 R/W 0 PDR30 0 R/W Rev.3.00 Jan. 10, 2007 page 994 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFC4: Port Data Register 4 PDR4: I/O Port Bit : Initial value : R/W : 7 PDR47 0 R/W 6 PDR46 0 R/W 5 PDR45 0 R/W 4 PDR44 0 R/W 3 PDR43 0 R/W 2 PDR42 0 R/W 1 PDR41 0 R/W 0 PDR40 0 R/W H'FFC5: Port Data Register 5 PDR5: I/O Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PDR53 0 R/W 2 PDR52 0 R/W 1 PDR51 0 R/W 0 PDR50 0 R/W H'FFC6: Port Data Register 6 PDR6: I/O Port Bit : Initial value : R/W : 7 PDR67 0 R/W 6 PDR66 0 R/W 5 PDR65 0 R/W 4 PDR64 0 R/W 3 PDR63 0 R/W 2 PDR62 0 R/W 1 PDR61 0 R/W 0 PDR60 0 R/W H'FFC7: Port Data Register 7 PDR7: I/O Port Bit : Initial value : R/W : 7 PDR77 0 R/W 6 PDR76 0 R/W 5 PDR75 0 R/W 4 PDR74 0 R/W 3 PDR73 0 R/W 2 PDR72 0 R/W 1 PDR71 0 R/W 0 PDR70 0 R/W H'FFC8: Port Data Register 8 PDR8: I/O Port Bit : Initial value : R/W : 7 PDR87 0 R/W 6 PDR86 0 R/W 5 PDR85 0 R/W 4 PDR84 0 R/W 3 PDR83 0 R/W 2 PDR82 0 R/W 1 PDR81 0 R/W 0 PDR80 0 R/W Rev.3.00 Jan. 10, 2007 page 995 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFCD: Port Mode Register 0 PMR0: I/O Port Bit : Initial value : R/W : 7 PMR07 0 R/W 6 PMR06 0 R/W 5 PMR05 0 R/W 4 PMR04 0 R/W 3 PMR03 0 R/W 2 PMR02 0 R/W 1 PMR01 0 R/W 0 PMR00 0 R/W P07/AN7 to P00/IRQ0 rin function select bits 0 1 Note: P0n/ANn pin functions as P0n input port P0n/ANn pin functions as ANn input port n = 7 to 0 H'FFCE: Port Mode Register 1 PMR1: I/O Port Bit : Initial value : R/W : 7 PMR17 0 R/W 6 PMR16 0 R/W 5 PMR15 0 R/W 4 PMR14 0 R/W 3 PMR13 0 R/W 2 PMR12 0 R/W 1 PMR11 0 R/W 0 PMR10 0 R/W P15/IRQ5 to P10/IRQ0 pin function select bits 0 1 P1n/IRQn pin functions as P1n I/O port P1n/IRQn pin functions as IRQn input port Note: n = 5 to 0 P16/IC pin function select bit 0 1 P16/IC pin functions as P16 I/O port P16/IC pin functions as IC input port P17/TMOW pin function select bit 0 1 P17/TMOW pin functions as P17 I/O port P17/TMOW pin functions as TMOW output port Rev.3.00 Jan. 10, 2007 page 996 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFCF: Port Mode Register 2 PMR2: I/O Port Bit : Initial value : R/W : 7 PMR27 0 R/W 6 PMR26 0 R/W 5 PMR25 0 R/W 4 -- 1 -- 0 1 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PMR20 0 R/W P26/SO2 pin PMOS control bit P26/SO2 pin functions as CMOS output P26/SO2 pin functions as NMOS open drain output P25/SI2 pin function select bit 0 1 P25/SI2 pin functions as P25 I/O port P25/SI2 pin functions as S12 input port P26/SO2 pin function select bit 0 1 P26/SO2 pin functions as P26 I/O port P26/SO2 pin functions as SO2 output port P27/SCK2 pin function select bit 0 1 P27/SCK2 pin functions as P27 I/O port P27/SCK2 pin functions as SCK2 I/O port Rev.3.00 Jan. 10, 2007 page 997 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFD0: Port Mode Register 3 PMR3: I/O Port Bit : Initial value : R/W : 7 PMR37 0 R/W 6 PMR36 0 R/W 5 PMR35 0 R/W 4 PMR34 0 R/W 3 PMR33 0 R/W 2 PMR32 0 R/W 1 PMR31 0 R/W 0 PMR30 0 R/W P30/CS pin function select bit 0 1 P30/CS pin functions as P30 I/o port P30/CS pin functions as CS input port P31/STRB pin function select bit 0 1 P31/STRB pin functions as P31 I/O port P31/STRB pin functions as STRB output port P35/PWM3 to P32/PWM0 pin function select bit 0 1 P36/BUZZ pin function select bit 0 1 P36/BUZZ pin functions as P36 I/O port P36/BUZZ pin functions as BUZZ output port P3n/PWMm pin functions as P3n I/O port P3n/PWMm pin functions as PWMm output port Note: n = 5 to 2, m = 3 to 0 P37/TMO pin function select bit 0 1 P37/TMO pin functions as P37 I/O port P37/TMO pin functions as TMO output port Notes: If the TMO pin is used for remote control sending, a careless timer output pulse may be output when the remote control mode is set after the output has been switched to the TMO output. Perform the switching and setting in the following order. [1] Set the remote control mode. [2] Set the TMJ-1 and 2 counter data of the timer J. [3] Switch the P37/TMO pin to the TMO output pin. [4] Set the ST bit to 1. H'FFD1: Port Control Register 1 PCR1: I/O Port Bit : Initial value : R/W : 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W 0 1 P1n pin functions as input port P1n pin functions as output port Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 998 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFD2: Port Control Register 2 PCR2: I/O Port Bit : Initial value : R/W : 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W 0 1 P2n pin functions as input port P2n pin functions as output port Note: n = 7 to 0 H'FFD3: Port Control Register 3 PCR3: I/O Port Bit : Initial value : R/W : 7 PCR37 0 W 6 PCR36 0 W 5 PCR35 0 W 4 PCR34 0 W 3 PCR33 0 W 2 PCR32 0 W 1 PCR31 0 W 0 PCR30 0 W 0 1 P3n pin functions as input port P3n pin functions as output port Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 999 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFD4: Port Control Register 4 PCR4: I/O Port Bit : Initial value : R/W : 7 PCR47 0 W 6 PCR46 0 W 5 PCR45 0 W 4 PCR44 0 W 3 PCR43 0 W 2 PCR42 0 W 1 PCR41 0 W 0 PCR40 0 W 0 1 P4n pin functions as input port P4n pin functions as output port Note: n = 7 to 0 H'FFD5: Port Control Register 5 PCR5: I/O Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W 0 1 P5n pin functions as input port P5n pin functions as output port Note: n = 3 to 0 H'FFD6: Port Control Register 6 PCR6: I/O Port Bit : Initial value : R/W : 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W PMR6n 0 1 PCR6n 0 1 * Port Control Register 6 P6n/RPn pin functions as P6n general purpose input port P6n/RPn pin functions as P6n general purpose output port P6n/RPn pin functions as RPn realtime output port Legend: * Don't care. Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 1000 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFD7: Port Control Register 7 PCR7: I/O Port Bit : Initial value : R/W : 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 PCR72 0 W 1 PCR71 0 W 0 PCR70 0 W 0 1 P7n pin functions as input port P7n pin functions as output port Note: n = 7 to 0 H'FFD8: Port Control Register 8 PCR8: I/O Port Bit : Initial value : R/W : 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W 0 1 P8n pin functions as input port P8n pin functions as output port Note: n = 7 to 0 H'FFDB: Port Mode Register 4 PMR4: I/O Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 0 1 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PMR40 0 R/W P40/PWM14 pin function select bit P40/PWM14 pin functions as P40 I/O port P40/PWM14 pin functions as PWM14 output port Rev.3.00 Jan. 10, 2007 page 1001 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFDC: Port Mode Register 5: PMR5: I/O Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PMR53 0 R/W 2 PMR52 0 R/W 1 PMR51 0 R/W 0 -- 1 -- Timer B event input edge select 0 1 The timer B event input detects the falling edge The timer B event input detects the rising edge P52/TMBI pin function select bit 0 1 P52/TMBI pin function as P52 I/O port P52/TMBI pin functions as TMBI input port P53/TRIG pin function select bit 0 1 P53/TRIG pin function as P53 I/O port P53/TRIG pin function as TRIG input port H'FFDD: Port Mode Register 6 PMR6: I/O Port Bit : Initial value : R/W : 7 PMR67 0 R/W 6 PMR66 0 R/W 5 PMR65 0 R/W 4 PMR64 0 R/W 3 PMR63 0 R/W 2 PMR62 0 R/W 1 PMR61 0 R/W 0 PMR60 0 R/W P67/RP7 to P60/RP0 pin function select bit 0 1 P6n/RPn pin functions as P6n I/O port P6n/RPn pin functions as RPn output port Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 1002 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFDE: Port Mode Register 7 PMR7: I/O Port Bit : Initial value : R/W : 7 PMR77 0 R/W 6 PMR76 0 R/W 5 PMR75 0 R/W 4 PMR74 0 R/W 3 PMR73 0 R/W 2 PMR72 0 R/W 1 PMR71 0 R/W 0 PMR70 0 R/W P77/PPG7 to P70/PPG0 pin function select bit 0 1 P7n/PPGn pin functions as P7n I/O port P7n/PPGn pin functions as PPGn output port Note: n = 7 to 0 H'FFDF: Port Mode Register 8 PMR8: I/O Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PMR83 0 R/W 2 PMR82 0 R/W 1 PMR81 0 R/W 0 PMR80 0 R/W P80/EXTTRG pin function select bit 0 1 P80/EXTTRG pin functions as P80 I/O port P80/EXTTRG pin functions as EXTTRG input port P81/EXCAP pin function select bit 0 1 P81/EXCAP pin functions as P81 I/O port P81/EXCAP pin functions as EXCAP input port P82/SV1 pin function select bit 0 1 P82/SV1 pin functions as P82 I/O port P82/SV1 pin functions as SV1 output port P83/SV2 pin function select bit 0 1 P83/SV2 pin functions as P83 I/O port P83/SV2 pin functions as SV2 output port Rev.3.00 Jan. 10, 2007 page 1003 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFE1: Pull-Up MOS Select Register 1 PUR1: I/O Port Bit : Initial value : R/W : 7 PUR17 0 R/W 6 PUR16 0 R/W 5 PUR15 0 R/W 4 PUR14 0 R/W 3 PUR13 0 R/W 2 PUR12 0 R/W 1 PUR11 0 R/W 0 PUR10 0 R/W 0 1 P1n pin has no pull-up MOS transistor P1n pin has pull-up MOS transistor Note: n = 7 to 0 H'FFE2: Pull-Up MOS Select Register 2 PUR2: I/O Port Bit : Initial value : R/W : 7 PUR27 0 R/W 6 PUR26 0 R/W 5 PUR25 0 R/W 4 PUR24 0 R/W 3 PUR23 0 R/W 2 PUR22 0 R/W 1 PUR21 0 R/W 0 PUR20 0 R/W 0 1 P2n pin has no pull-up MOS transistor P2n pin has pull-up MOS transistor Note: n = 7 to 0 H'FFE3: Pull-Up MOS Select Register 3 PUR3: I/O Port Bit : Initial value : R/W : 7 PUR37 0 R/W 6 PUR36 0 R/W 5 PUR35 0 R/W 4 PUR34 0 R/W 3 PUR33 0 R/W 2 PUR32 0 R/W 1 PUR31 0 R/W 0 PUR30 0 R/W 0 1 P3n pin has no pull-up MOS transistor P3n pin has pull-up MOS transistor Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 1004 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFE4: Realtime Output Trigger Edge Select Register RTPEGR: I/O Port Bit : Initial value : R/W : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 0 RTPEGR1 RTPEGR0 0 R/W 0 R/W Realtime output trigger edge select bit RTPEGR1 RTPEGR0 0 1 0 1 0 1 Realtime output trigger edge select Trigger input is disabled Rising edge of trigger input is selected Falling edge of trigger input is selected Rising and falling edges of trigger input is selected H'FFE5: Realtime Output Trigger Select Register RTPSR: I/O Port Bit : Initial value : R/W : 7 RTPSR7 0 R/W 6 RTPSR6 0 R/W 5 RTPSR5 0 R/W 4 RTPSR4 0 R/W 3 RTPSR3 0 R/W 2 RTPSR2 0 R/W 1 RTPSR1 0 R/W 0 RTPSR0 0 R/W 0 1 External trigger (TRIG pin) input is selected Internal triggfer (HSW) input is selected Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 1005 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFE8: System Control Register SYSCR: System Control Bit : 7 -- Initial value : R/W : 0 -- 6 -- 0 -- 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 1 0 -- 1 -- NMIEG1 NMIEG0 0 R/W 0 R/W NMI edge select bits NMIEG1 0 1 NMIEG0 0 1 * Legend: * Don't care. External reset 0 1 Reset is generated by watchdog timer overflow Reset is generaed by external reset input NMI edge select Interrupt request is generated at falling edge of NMI input Interrupt request is generated at rising edge of NMI input Interrupt request is generated at rising or falling edge of NMI input Interrupt control mode INTM1 0 1 INTM0 0 1 0 1 Interrupt control mode Interrupt control Interrupt is controlled by I bit Interrupt is controlled by I and UI bits and ICR Cannot be used in the H8S/2194 Group Cannot be used in the H8S/2194 Group 0 1 2 3 H'FFE9: Mode Control Register MDCR: System Control Bit : 7 -- Initial value : R/W : 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 MDS0 --* R Mode select 0 Note: * Determined by MD0 pin. Rev.3.00 Jan. 10, 2007 page 1006 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFEA: Standby Control Register SBYCR: System Control Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 -- 0 -- 2 -- 0 -- 1 SCK1 0 R/W 0 SCK0 0 R/W System clock select SCK1 0 0 1 1 Standby timer select bits STS2 0 0 0 0 1 1 STS1 0 0 1 1 0 0 STS0 0 1 0 1 0 1 Standby time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states SCK0 0 1 0 1 System clock select Bus master is in high-speed mode Medium-speed clock is /16 Medium-speed clock is /32 Medium-speed clock is /64 * 16 states*1 1 1 Legend: * Don't care. Note: 1. The standby time is 32 states when transited to medium-speed mode /32 (SCK = 1, SCK = 0).Do not select 16 states for Flash ROM version. Software standby 0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode Transition to stadby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or mediumspeed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode 1 Rev.3.00 Jan. 10, 2007 page 1007 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFEB: Low-Power Control Register LPWRCR: System Control Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 NESEL 0 R/W 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 SA1 0 R/W 0 SA0 0 R/W Subactive mode clock select SA1 0 0 1 SA0 0 1 * Subactive mode clock select Operating clock of CPU is w/8 Operating clock of CPU is w/4 Operating clock of CPU is w/2 Legend: * Don't care. Noise elimination sampling frequency select 0 1 Sampling at divided by 16 Sampling at divided by 4 Low-speed on flag 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode * After watch mode is cleared, a transition is made to high-speed mode * When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode, subactive mode, sleep mode or standby mode. * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode. * After watch mode is cleared, a transition is made to subactive mode 1 Direct transfer on flag 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or standby mode * When a SLEEP instruction is executed in subactive mode, a transition is made directily to high-speed mode, or a transition is made to subsleep mode 1 Rev.3.00 Jan. 10, 2007 page 1008 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFEC: Module Stop Control Register MSTPCRH: System Control H'FFED: Module Stop Control Register MSTPCRL: System Control MSTPCRH Bit : Initial value : R/W : 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module stop 0 1 Module stop mode is released Module stop mode is set H'FFEE: Serial Timer Control Register STCR: System Control Bit : Initial value : R/W : 7 -- 0 -- 6 IICX 0 R/W 5 IICRST 0 R/W 4 -- 0 -- 3 FLSHE 0 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Flash memory control register enable bit 0 1 Flash memory control register is not selected Flash memory control register is selected I2C controller reset bit 0 1 I2C bus interface controller is not reset I2C bus interface controller is reset I2C transfer clock select Used combined with ICMR CKS2 to CKS0 Rev.3.00 Jan. 10, 2007 page 1009 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFF0: IRQ Edge Select Register IEGR: Interrupt Controller Bit : 7 -- Initial value : R/W : 0 -- 6 IRQ5EG 0 R/W 5 IRQ4EG 0 R/W 4 IRQ3EG 0 R/W 3 IRQ2EG 0 R/W 2 1 0 IRQ1EG IRQ0EG1 IRQ0EG0 0 R/W 0 R/W 0 R/W IRQ0 pin detected dege select bits IRQ0EG1 0 0 1 IRQ0EG0 0 1 * IRQ0 pin detected edge select Interrupt request generaed at falling edge of IRQ0 pin input Interrupt request generaed at rising edge of IRQ0 pin input Interrupt request generaed at bath falling and rising edge of IRQ0 pin input Legend: * Don't care. IRQ5 to IRQ1 pins detected edge select bits 0 1 Interrupt request generated at falling edge of IRQn pin input Interrupt request generated at rising edge of IRQn pin input Note: n = 5 to 1 H'FFF1: IRQ Enable Register IENR: Interrupt Controller Bit : Initial value : R/W : 7 -- 0 -- 6 -- 0 -- 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ5 to IRQ0 enable bits 0 1 Note: IRQn interrupt is disabled IRQn interrupt is enabled n = 5 to 0 Rev.3.00 Jan. 10, 2007 page 1010 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFF2: IRQ Status Register IRQR: Interrupt Controller Bit : Initial value : R/W : 7 -- 0 -- 6 -- 0 -- 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ5 to IRQ0 flag 0 [Clearing condition] Cleared by reading IRQnF set to 1, then writing 0 in IRQnF When IRQn interrupt exception handling is executed [Setting conditions] (1) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnEG = 0) (2) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnEG = 0) (3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is set (IRQ0EG1 = 1) 1 Note: n = 5 to 0 Note: * Only 0 can be written to clear the flag. H'FFF3: Interrupt Control Register A ICRA: Interrupt Controller H'FFF4: Interrupt Control Register B ICRB: Interrupt Controller H'FFF5: Interrupt Control Register C ICRC: Interrupt Controller H'FFF6: Interrupt Control Register D ICRD: Interrupt Controller Bit : Initial value : R/W : 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W 3 ICR3 0 R/W 2 ICR2 0 R/W 1 ICR1 0 R/W 0 ICR0 0 R/W Interrupt control level 0 1 Corresponding interrupt source is control level 0 (non-priority) Corresponding interrupt source is control level 1 (priority) Note: n = 7 to 0 Rev.3.00 Jan. 10, 2007 page 1011 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFF8: Flash Memory Control Register 1 FLMCR1: FLASH ROM (H8S/2194 FLASH Version Only) Bit : Initial value : R/W : 7 FWE --* R 6 SWE 0 R/W 5 -- 0 -- 4 -- 0 -- 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Program 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program-verify 0 1 Program-verify mode cleared Transition to program-verufy mode [Setting condition] When FWE = 1 and SWE = 1 Erase-verify 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Software write enable 0 1 Writes are disabled Writes are enabled [Setting condition] When FWE = 1 Flash write enable 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev.3.00 Jan. 10, 2007 page 1012 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFF8: Flash Memory Control Register 1 FLMCR1: FLASH ROM (H8S/2194C FLASH Version Only) Bit : Initial value : R/W : 7 FWE --* R 6 SWE 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W Program 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program verify 0 1 Program-verify mode cleared Transition to program-verufy mode [Setting condition] When FWE = 1 and SWE = 1 Erase verify 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Program setup bit 1 0 1 Program-setup cleared Program-setup [Setting condition] When FWE = 1 and SWE = 1 Erase setup bit 1 0 1 Erase-setup cleared Erase-setup [Setting condition] When FWE = 1 and SWE = 1 Software write enable 0 1 Writes are disabled Writes are enabled [Setting condition] When FWE = 1 Flash write enable 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev.3.00 Jan. 10, 2007 page 1013 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFF9: Flash Memory Control Register 2 FLMCR2: FLASH ROM (H8S/2194 FLASH Version Only) Bit : Initial value : R/W : 7 FLER 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- Program setup 0 1 Program setup cleared Program setup [Setting condition] When FWE = 1, and SWE = 1 3 -- 0 -- 2 -- 0 -- 1 ESU 0 R/W 0 PSU 0 R/W Erase setup 0 1 Erase setup cleared Erase setup [Setting condition] When FWE = 1, and SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memeory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 7.6.3, Error Protection 1 Rev.3.00 Jan. 10, 2007 page 1014 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFF9: Flash Memory Control Register 2 FLMCR2: FLASH ROM (H8S/2194C FLASH Version Only) Bit : Initial value : R/W : 7 FLER 0 R 6 -- 0 -- 5 ESU2 0 R/W 4 PSU2 0 R/W 3 EV2 0 R/W 2 PV2 0 R/W 1 E2 0 R/W 0 P2 0 R/W Program 2 0 1 Erase 2 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, and SWE = 1,and ESU2 = 1 Program mode cleared Transition to program-mode [Setting condition] When FWE = 1, and SWE = 1,and ESU2 = 1 Program-verify 2 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1, and SWE = 1 Erase-verify 2 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1, and SWE = 1 Program setup bit 2 0 1 Program-setup cleared Program-setup [Setting condition] When FWE = 1, and SWE = 1 Erase setup bit 2 0 1 Erase-setup cleared Erase-setup [Setting condition] When FWE = 1, and SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memeory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 8.6.3, Error Protection 1 Rev.3.00 Jan. 10, 2007 page 1015 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFFA: Erase Block Select Register 1 EBR1: FLASH ROM (H8S/2194 FLASH Version Only) Bit : EBR1 Initial value : R/W : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 EB9 0 R/W 0 EB8 0 R/W H'FFFA: Erase Block Select Register 1 EBR1: FLASH ROM (H8S/2194C FLASH Version Only) Bit : EBR1 Initial value : R/W : 7 -- 0 -- 6 -- 0 -- 5 EB13 0 R/W 4 EB12 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W H'FFFB: Erase Block Select Register 2 EBR2: FLASH ROM (H8S/2194 FLASH Version Only) Bit : EBR2 Initial value : R/W : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Division of Erase Block Block (size) 128-kbyte version EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF Rev.3.00 Jan. 10, 2007 page 1016 of 1038 REJ09B0328-0300 Appendix B Internal I/O Registers H'FFFB: Erase Block Select Register 2 EBR2: FLASH ROM (H8S/2194C FLASH Version Only) Bit : EBR2 Initial value : R/W : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Division of Erase Block Block (size) 256-kbyte version EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) EB10 (32 kbytes) EB11 (32 kbytes) EB12 (32 kbytes) EB13 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF H'020000 to H'027FFF H'028000 to H'02FFFF H'030000 to H'037FFF H'038000 to H'03FFFF Rev.3.00 Jan. 10, 2007 page 1017 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Appendix C Pin Circuit Diagrams C.1 Pin Circuit Diagrams Circuit diagrams for all pins except power supply pins are shown in table C.1. Legend G G IN OUT PMOS NMOS OUT IN Clocked gate signal transmitted when G = 1 Signal transmitted when G = 0 Legend: RD: RST: LPM: Hi-Z: Read signal Reset signal Power-down mode signal (1 in standby, watch, and subactive modes) High impedance SLEEP: Sleep mode signal Note: Numbers given for resistance values, etc., are reference values. Rev.3.00 Jan. 10, 2007 page 1018 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Table C.1 Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P00/AN0 to P07/AN7 Circuit Diagram PMR0n * RD Sleep At Reset Mode Hi-Z Retained Hi-Z SCH3 to SCH0 AN8 to ANB Hi-Z Retained Hi-Z HCH1, HCH0 P10/IRQ0 to P15/IRQ5 P16/IC PUR1n * PCR1n PDR1n Hi-Z PMR1n PCR1n RD Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z When IRQ0 to IRQ5 and IC input are selected, pin input should be fixed high or low. INT PMR1n Notes: INT = IRQ0 to IRQ5, IC n = 0 to 6 Rev.3.00 Jan. 10, 2007 page 1019 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P17/TMOW Circuit Diagram PUR17 * PCR17 Sleep At Reset Mode Hi-Z TMOW PDR17 PMR17 PCR17 Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD P20/SI1 PUR20 * PCR20 PDR20 Hi-Z RXE PCR20 RD Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z SI1 RXE Legend: RXE: Input control signal determined by SCR and SMR. When SI1 input is selected, pin input should be fixed high or low. Rev.3.00 Jan. 10, 2007 page 1020 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P21/SO1 Circuit Diagram PUR21 * PCR21 SO1 PDR21 TXE PCR21 Sleep At Reset Mode Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD Legend: TXE: Output control signal determined by SCR and SMR. P22/SCK1 PUR22 * PCR22 SCKO PDR22 CKOE PCR22 Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD SCKI CKIE Legend: SCKO: Transfer clock output SCKI: Transfer clock input CKOE: Transfer clock output control signal determined by SMR CKIE: Transfer clock input control signal determined by SMR and SCR When SCK1 is set to input, pin input should be fixed high or low. Rev.3.00 Jan. 10, 2007 page 1021 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P23/SDA P24/SCL Circuit Diagram PUR2n * PCR2n PDR2n Sleep At Reset Mode Hi-Z IICE PCR2n Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD IICE SDA/SCL SDA/SCL IICE Legend: IICE: I2C bus enable signal Note: n = 3, 4 P26/SO2 PUR26 * PCR26 SO2 PDR26 PDR26 PCR26 Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD Rev.3.00 Jan. 10, 2007 page 1022 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P25/SI2 Circuit Diagram PUR25 * PCR25 PDR25 Sleep At Reset Mode Hi-Z PMR25 PCR25 RD Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z SI2 PMR25 When SI2 input is selected, pin input should be fixed high or low. Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z P27/SCK2 PUR27 * PCR27 SCKO PDR27 PMR27 EXCK PCR27 SCKI RD Legend: SCKO: Transfer clock output SCKI: Transfer clock input EXCK: External clock input control signal determined by SMR1 or SMR2 Note: n = 3, 6 When SCK2 is set to input, pin input should be fixed high or low. Rev.3.00 Jan. 10, 2007 page 1023 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P30/CS Circuit Diagram PUR30 * PCR30 PDR30 Sleep At Reset Mode Hi-Z PMR30 PCR30 RD Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z When CS input is selected, pin input should be fixed high or low. CS PMR30 P31/STRB P32/PWM0 P33/PWM1 P34/PWM2 P35/PWM3 P36/BUZZ P37/TMO PUR3n * PCR3n OUT PDR3n PMR3n PCR3n Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD Legend: OUT: P31/STRB: SC12 strobe output P32/PWM0: 8-bit PWM0 output P33/PWM1: 8-bit PWM1 output P34/PWM2: 8-bit PWM2 output P35/PWM3: 8-bit PWM3 output P36/BUZZ: Timer J buzzer output P37/TMO: Timer J timer output Note: n = 1 to 7 Rev.3.00 Jan. 10, 2007 page 1024 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P40/PWM14 Circuit Diagram OUT Sleep At Reset Mode Hi-Z PDR40 PMR40 PCR40 Retained Subactive mode: Functions Other modes: Hi-Z RD OUT PWM14 P41/FTIA P42/FTIB P43/FTIC P44/FTID PDR4n Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z Note: * As pins FTIA to FTID are always active except in the standby and watch modes, a high or low level should be input to them. PCR4n RD IN Legend: IN = FTIA, FTIB, FTIC, FTID* Note: n = 1 to 4 P45/FTOA P46/FTOB OUT PDR4n TOE PCR4n Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z RD Legend: OUT: P45/FTOA: Timer X1 output compare output FTOA P46/FTOB: Timer X1 output compare output FTOB TOE: Output control signal determined by TOCR Note: n = 5, 6 Rev.3.00 Jan. 10, 2007 page 1025 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P47 Circuit Diagram PDR47 Sleep At Reset Mode Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z PCR47 RD P50/ADTRG PDR50 Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z TRGE PCR50 RD ADTRG TRGE Legend: TRGE: A/D trigger input control signal When ADTRG input is selected, pin input should be fixed high or low. Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z P51 PDR51 PCR51 RD Rev.3.00 Jan. 10, 2007 page 1026 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P52/TMBI P53/TRIG Circuit Diagram PDR5n Sleep At Reset Mode Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z PMR5n PCR5n RD IN PMR5n Legend: IN = TMBI, TRIG Note: n = 2, 3 When TMBI and TRIG input are selected, pin input should be fixed high or low. PDRS6n P60/RP0 to P67/RP7 Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z PCRS6n RD Note: n = 0 to 7 P70/PPG0 to P77/PPG7 PPGn PDR7n PMR7n PCR7n Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z RD Note: n = 0 to 7 Rev.3.00 Jan. 10, 2007 page 1027 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Pin Names P80/ EXTTRG P81/EXCAP Circuit Diagram PDR8n Sleep At Reset Mode Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z PMR8n PCR8n RD IN PMR8n Legend: IN = EXTTRG, EXCAP Note: n = 0, 1 When EXTTRG and EXCAP input are selected, pin input should be fixed high or low. OUT PDR8n PMR8n PCR8n P82/SV1 P83/SV2 Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z RD Legend: OUT = SV1, SV2 Note: n = 2, 3 P84 to P87 PDR8n Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z PCR8n RD Note: n = 4 to 7 Csync Module STOP Pin input should be fixed high or low. Rev.3.00 Jan. 10, 2007 page 1028 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Hi-Z Pin Names COMP/PS2 Circuit Diagram SPDR2 Sleep At Reset Mode Hi-Z Hi-Z SPMR2 SPCR2 RD When COMP input is selected, pin input should be fixed high or low. COMP SPMR2 AUDIOFF VIDEOFF OUT Hi-Z Hi-Z Hi-Z LPM Legend: LPM: power-down mode signal CAPPWM DRMPWM Vpulse 15 k Typ Low output LPM Threelevel control circuit Low output Low output Low output Low output Low output 15 k Typ Note: Resistance values are reference value RES MD0 NMI RST Low input (High) (High) When NMI is not used, pin input should be fixed high or low. Rev.3.00 Jan. 10, 2007 page 1029 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Hi-Z Pin Names C.Rotary/PS0 H.Ampsw/ PS1 Circuit Diagram OUT SPDRn SPMRn SPCRn Sleep At Reset Mode Hi-Z Hi-Z RD Notes: n = 0, 1 OUT = C.Rotary, H.Ampsw EXCTL/PS4 SPDR4 Hi-Z Hi-Z Hi-Z SPMR4 SPCR4 RD EXCTL SPMR4 When EXCTL input is selected, pin input should be fixed high or low. + VREF CFG BIAS CFGCOMP P250 REF M250 CFGCOMP S O R stp F/F CFG + + RES+ModuleSTOP VREF Rev.3.00 Jan. 10, 2007 page 1030 of 1038 REJ09B0328-0300 Appendix C Pin Circuit Diagrams Pin States Power-Down Modes Other than Sleep Mode Hi-Z Pin Names DFG DPG/PS3 Circuit Diagram DPG SW DFG DFG Sleep At Reset Mode Hi-Z DPG DPG /PS3 DPG SW PDRn RES + LPM PMRn PCRn RD CTL (+) CTL (-) CTLREF CTLBias CTLFB CTLAmp (O) CTLSMT (i) AMPON (PB-CTL) AMPSHORT (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 +- + - + PB-CTL (+) PB-CTL (-) CTL (-) CTL (+) CTLREF CTLBias CTLFB CTLAmp (o) CTLSMT (i) Note Note: Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i). X2 1 M Typ Oscillation Oscillation Oscillation X1 Note: Resistance values are reference values. When the subclock is not used, set X1 = high and X2 = open. Oscillation Oscillation Low output OSC2 OSC1 LPM Rev.3.00 Jan. 10, 2007 page 1031 of 1038 REJ09B0328-0300 Appendix D Port States in the Difference Processing States Appendix D Port States in the Difference Processing States D.1 Pin Circuit Diagrams Port States Overview Reset Active Sleep Standby Watch Subactive Subsleep High impedance Retained Retained Retained Retained Retained Retained Retained Retained Table D.1 Port P07 to P00 High High High High High High imped-ance imped-ance imped-ance imped-ance imped-ance impedance P17 to P10 High Functions imped-ance P27 to P20 High Functions imped-ance P37 to P30 High Functions imped-ance P47 to P40 High Functions imped-ance P53 to P50 High Functions imped-ance P67 to P60 High Functions imped-ance P77 to P70 High Functions imped-ance P87 to P80 High Functions imped-ance Retained Retained Retained Retained Retained Retained Retained Retained High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance High High Functions imped-ance imped-ance Rev.3.00 Jan. 10, 2007 page 1032 of 1038 REJ09B0328-0300 Appendix E Usage Notes Appendix E Usage Notes E.1 Power Supply Rise and Fall Order Figure E.1 shows the order in which the power supply pins rise when the chip is powered on, and the order in which they fall when the chip is powered down. If the power supply voltages cannot rise and fall simultaneously, power supply operations should be carried out in this order. At power-on, wait until the microcomputer section power supply (VCC) has risen to the prescribed voltage, then raise the other analog power supplies. At power-down, drop the analog power supplies first, followed by the microcomputer section power supply (VCC). When powering up and down, ensure that the voltage applied to the pins does not exceed the respective power supply voltage. VCC, AVCC SVCC Vin Vin VCC, AVCC SVCC Legend: VCC : Microcomputer section power supply voltage AVCC : A/D converter power supply voltage SVCC : Servo section power supply voltage Vin : Pin applied voltage Figure E.1 Power Supply Rise and Fall Order In power-down modes (except sleep mode), the analog power supplies can be turned off to reduce current dissipation. When the microcomputer section power supply (VCC) is dropped to the backup voltage in a power-down mode, the order shown in figure E.2 should be followed. Make sure that the voltage applied to the pins does not exceed the respective power supply voltage. The A/D converter power supply (AVCC) should be set to the same potential as the microcomputer section power supply (VCC). In all power-down modes except sleep mode, AVCC is turned off inside the device. At this time, the AVCC current dissipation is defined as AISTOP. Rev.3.00 Jan. 10, 2007 page 1033 of 1038 REJ09B0328-0300 Appendix E Usage Notes VCC, AVCC SVCC 5V 2.7 V Vin Legend: VCC : Microcomputer section power supply voltage AVCC : A/D converter power supply voltage SVCC : Servo section power supply voltage Vin : Pin applied voltage Figure E.2 Power Supply Control in Power-Down Modes E.2 Pin Handling when the High-Speed Switching Circuit for Four-Head Special Playback Is Not Used Table E.1 shows how the C.Rotary, H.AmpSW, and COMP pins should be handled when the switching circuit for four-head special-effects playback is not used. COMP is an input pin, and the other two are output pins. When the switching circuit for four-head special-effects playback is not used, the related pins should be handled as shown below. Table E.1 Pin Handling when the High-Speed Switching Circuit for Four-Head Special Playback Is Not Used Pin Name C.Rotary H.AMP SW COMP * Connection OPEN (output pin)* OPEN (output pin)* VSS Pin No. 103 104 105 Note: Output depends on the special-effects control register (CHCR) value. If the initial value is used, the output is low-level. Rev.3.00 Jan. 10, 2007 page 1034 of 1038 REJ09B0328-0300 Appendix E Usage Notes E.3 Sample External Circuits Examples of external circuits for the servo section, and sync signal detection circuit are shown in figures E.3, E.4. (1) Servo Section An example of the external circuit for the DRMPWM output and CAPPWM output pins is shown in figure E.3. R1 DRMPWM CAPPWN C1 Figure E.3 Sample External Circuit for Servo Section (2) Sync Signal Detection Circuit Section Figure E.4 shows an example of the external circuit for the sync signal detection circuit section. Csync 33 k 10 pF Note: The figures shown are reference values. Careful consideration should be given to board floating capacitance and wiring characteristics when deciding on the constants. Figure E.4 Example of External Circuit for Sync Signal Detection Circuit Section Rev.3.00 Jan. 10, 2007 page 1035 of 1038 REJ09B0328-0300 Appendix F List of Product Codes Appendix F List of Product Codes Table F.1 Product Codes List of H8S/2194 Group and H8S/2194C Group Package (Package Code) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) Product Type H8S/2194 Group H8S/2194 Mask ROM version F-ZTAT version H8S/2193 H8S/2192 H8S/2191 H8S/2194C Group H8S/2194C Mask ROM version Mask ROM version Mask ROM version Mask ROM version F-ZTAT version H8S/2194B H8S/2194A Mask ROM version Mask ROM version Part No. HD6432194 HD64F2194 HD6432193 HD6432192 HD6432191 Mark Code HD6432194 (***)F HD64F2194F HD6432193 (***)F HD6432192 (***)F HD6432191 (***)F HD6432194C HD6432194C (***)F HD64F2194C HD64F2194CF HD6432194B HD6432194B (***)F HD6432194A HD6432194A (***)F Note: (***) is the ROM code. Rev.3.00 Jan. 10, 2007 page 1036 of 1038 REJ09B0328-0300 Appendix G External Dimensions Appendix G External Dimensions The package dimention that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-QFP112-20x20-0.65 RENESAS Code PRQP0112JA-A Previous Code FP-112/FP-112V MASS[Typ.] 2.4g HD *1 D 57 84 85 56 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section 112 29 Reference Symbol Dimension in Millimeters 1 ZD 28 F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A AA bp b1 c c1 e x y ZD ZE L L1 Nom Max 20 20 2.70 22.9 23.2 23.5 22.9 23.2 23.5 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0 8 0.65 0.13 0.10 1.23 1.23 0.5 0.8 1.1 1.6 Min ZE A2 Figure G.1 Extermal Dimensions (FP-112) Rev.3.00 Jan. 10, 2007 page 1037 of 1038 REJ09B0328-0300 A c Appendix G External Dimensions Rev.3.00 Jan. 10, 2007 page 1038 of 1038 REJ09B0328-0300 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2194 Group, H8S/2194C Group, H8S/2194 F-ZTATTM, H8S/2194C F-ZTATTM Publication Date: 1st Edition, November 1998 Rev.3.00, January 10, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8S/2194 Group, H8S/2194C Group, H8S/2194 F-ZTATTM, H8S/2194C F-ZTATTM Hardware Manual |
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